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ASoC: OMAP: McBSP: Consolidate plat/mcbsp.h content
[mirror_ubuntu-bionic-kernel.git] / sound / soc / omap / mcbsp.c
CommitLineData
5e1c5ff4 1/*
71e822e9 2 * sound/soc/omap/mcbsp.c
5e1c5ff4
TL		 3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
71e822e9
PU		 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
5e1c5ff4
TL		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
bc5d0c89 20#include <linux/platform_device.h>
5e1c5ff4
TL		 21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
5e1c5ff4 27
ce491cf8 28#include <plat/mcbsp.h>
e95496d4 29#include <linux/pm_runtime.h>
5e1c5ff4 30
219f4316
PU		 31#include "mcbsp.h"
32
b4b58f58 33struct omap_mcbsp **mcbsp_ptr;
ac6747ca 34int omap_mcbsp_count;
bc5d0c89 35
09d28d2c
JN		 36#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
37#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
38
b0a330dc 39static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 40{
cdc71514
JN		 41 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
42
43 if (mcbsp->pdata->reg_size == 2) {
44 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
45 __raw_writew((u16)val, addr);
c8c99699 46 } else {
cdc71514
JN		 47 ((u32 *)mcbsp->reg_cache)[reg] = val;
48 __raw_writel(val, addr);
c8c99699 49 }
b4b58f58
CS		 50}
51
b0a330dc 52static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 53{
cdc71514
JN		 54 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
55
56 if (mcbsp->pdata->reg_size == 2) {
57 return !from_cache ? __raw_readw(addr) :
58 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 59 } else {
cdc71514
JN		 60 return !from_cache ? __raw_readl(addr) :
61 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 62 }
b4b58f58
CS		 63}
64
b0a330dc 65static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 66{
67 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68}
69
b0a330dc 70static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 71{
72 return __raw_readl(mcbsp->st_data->io_base_st + reg);
73}
d912fa92 74
8ea3200f 75#define MCBSP_READ(mcbsp, reg) \
c8c99699 76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 77#define MCBSP_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 79#define MCBSP_READ_CACHE(mcbsp, reg) \
80 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 81
d912fa92
EN		 82#define MCBSP_ST_READ(mcbsp, reg) \
83 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
84#define MCBSP_ST_WRITE(mcbsp, reg, val) \
85 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
86
5e1c5ff4
TL		 87static void omap_mcbsp_dump_reg(u8 id)
88{
b4b58f58
CS		 89 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
90
91 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
92 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 93 MCBSP_READ(mcbsp, DRR2));
b4b58f58 94 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 95 MCBSP_READ(mcbsp, DRR1));
b4b58f58 96 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 97 MCBSP_READ(mcbsp, DXR2));
b4b58f58 98 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 99 MCBSP_READ(mcbsp, DXR1));
b4b58f58 100 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 101 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 102 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 103 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 104 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 105 MCBSP_READ(mcbsp, RCR2));
b4b58f58 106 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 107 MCBSP_READ(mcbsp, RCR1));
b4b58f58 108 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 109 MCBSP_READ(mcbsp, XCR2));
b4b58f58 110 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 111 MCBSP_READ(mcbsp, XCR1));
b4b58f58 112 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 113 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 114 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 115 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 116 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 117 MCBSP_READ(mcbsp, PCR0));
b4b58f58 118 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 119}
120
0cd61b68 121static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 122{
e8f2af17 123 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 124 u16 irqst_spcr2;
5e1c5ff4 125
8ea3200f 126 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 127 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 128
d6d834b0
EN		 129 if (irqst_spcr2 & XSYNC_ERR) {
130 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
131 irqst_spcr2);
132 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 133 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 134 }
fb78d808 135
5e1c5ff4
TL		 136 return IRQ_HANDLED;
137}
138
0cd61b68 139static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 140{
e8f2af17 141 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 142 u16 irqst_spcr1;
143
8ea3200f 144 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 145 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
146
147 if (irqst_spcr1 & RSYNC_ERR) {
148 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
149 irqst_spcr1);
150 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 151 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 152 }
fb78d808 153
5e1c5ff4
TL		 154 return IRQ_HANDLED;
155}
156
5e1c5ff4
TL		 157/*
158 * omap_mcbsp_config simply write a config to the
159 * appropriate McBSP.
160 * You either call this function or set the McBSP registers
161 * by yourself before calling omap_mcbsp_start().
162 */
fb78d808 163void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 164{
b4b58f58 165 struct omap_mcbsp *mcbsp;
5e1c5ff4 166
bc5d0c89
EV		 167 if (!omap_mcbsp_check_valid_id(id)) {
168 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
169 return;
170 }
b4b58f58 171 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 172
b4b58f58
CS		 173 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
174 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 175
176 /* We write the given config */
8ea3200f
JK		 177 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
178 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
179 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
180 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
181 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
182 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
183 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
184 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
185 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
186 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
187 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 188 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 189 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
190 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 191 }
5e1c5ff4 192}
fb78d808 193EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 194
9504ba64
KVA		 195/**
196 * omap_mcbsp_dma_params - returns the dma channel number
197 * @id - mcbsp id
198 * @stream - indicates the direction of data flow (rx or tx)
199 *
200 * Returns the dma channel number for the rx channel or tx channel
201 * based on the value of @stream for the requested mcbsp given by @id
202 */
203int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
204{
205 struct omap_mcbsp *mcbsp;
206
207 if (!omap_mcbsp_check_valid_id(id)) {
208 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
209 return -ENODEV;
210 }
211 mcbsp = id_to_mcbsp_ptr(id);
212
213 if (stream)
214 return mcbsp->dma_rx_sync;
215 else
216 return mcbsp->dma_tx_sync;
217}
218EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
219
220/**
221 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
222 * @id - mcbsp id
223 * @stream - indicates the direction of data flow (rx or tx)
224 *
225 * Returns the address of mcbsp data transmit register or data receive register
226 * to be used by DMA for transferring/receiving data based on the value of
227 * @stream for the requested mcbsp given by @id
228 */
229int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
230{
231 struct omap_mcbsp *mcbsp;
232 int data_reg;
233
234 if (!omap_mcbsp_check_valid_id(id)) {
235 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
236 return -ENODEV;
237 }
238 mcbsp = id_to_mcbsp_ptr(id);
239
cdc71514 240 if (mcbsp->pdata->reg_size == 2) {
9504ba64 241 if (stream)
cdc71514 242 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 243 else
cdc71514 244 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 245 } else {
246 if (stream)
cdc71514 247 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 248 else
cdc71514 249 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 250 }
251
cdc71514 252 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64
KVA		 253}
254EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
255
d912fa92
EN		 256static void omap_st_on(struct omap_mcbsp *mcbsp)
257{
258 unsigned int w;
259
1743d14f
JN		 260 if (mcbsp->pdata->enable_st_clock)
261 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
d912fa92
EN		 262
263 /* Enable McBSP Sidetone */
264 w = MCBSP_READ(mcbsp, SSELCR);
265 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
266
d912fa92
EN		 267 /* Enable Sidetone from Sidetone Core */
268 w = MCBSP_ST_READ(mcbsp, SSELCR);
269 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
270}
271
272static void omap_st_off(struct omap_mcbsp *mcbsp)
273{
274 unsigned int w;
275
276 w = MCBSP_ST_READ(mcbsp, SSELCR);
277 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
278
d912fa92
EN		 279 w = MCBSP_READ(mcbsp, SSELCR);
280 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
281
1743d14f
JN		 282 if (mcbsp->pdata->enable_st_clock)
283 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
d912fa92
EN		 284}
285
286static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
287{
288 u16 val, i;
d912fa92
EN		 289
290 val = MCBSP_ST_READ(mcbsp, SSELCR);
291
292 if (val & ST_COEFFWREN)
293 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
294
295 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
296
297 for (i = 0; i < 128; i++)
298 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
299
300 i = 0;
301
302 val = MCBSP_ST_READ(mcbsp, SSELCR);
303 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
304 val = MCBSP_ST_READ(mcbsp, SSELCR);
305
306 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
307
308 if (i == 1000)
309 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
310}
311
312static void omap_st_chgain(struct omap_mcbsp *mcbsp)
313{
314 u16 w;
315 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 316
317 w = MCBSP_ST_READ(mcbsp, SSELCR);
318
319 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
320 ST_CH1GAIN(st_data->ch1gain));
321}
322
323int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
324{
325 struct omap_mcbsp *mcbsp;
326 struct omap_mcbsp_st_data *st_data;
327 int ret = 0;
328
329 if (!omap_mcbsp_check_valid_id(id)) {
330 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
331 return -ENODEV;
332 }
333
334 mcbsp = id_to_mcbsp_ptr(id);
335 st_data = mcbsp->st_data;
336
337 if (!st_data)
338 return -ENOENT;
339
340 spin_lock_irq(&mcbsp->lock);
341 if (channel == 0)
342 st_data->ch0gain = chgain;
343 else if (channel == 1)
344 st_data->ch1gain = chgain;
345 else
346 ret = -EINVAL;
347
348 if (st_data->enabled)
349 omap_st_chgain(mcbsp);
350 spin_unlock_irq(&mcbsp->lock);
351
352 return ret;
353}
354EXPORT_SYMBOL(omap_st_set_chgain);
355
356int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
357{
358 struct omap_mcbsp *mcbsp;
359 struct omap_mcbsp_st_data *st_data;
360 int ret = 0;
361
362 if (!omap_mcbsp_check_valid_id(id)) {
363 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
364 return -ENODEV;
365 }
366
367 mcbsp = id_to_mcbsp_ptr(id);
368 st_data = mcbsp->st_data;
369
370 if (!st_data)
371 return -ENOENT;
372
373 spin_lock_irq(&mcbsp->lock);
374 if (channel == 0)
375 *chgain = st_data->ch0gain;
376 else if (channel == 1)
377 *chgain = st_data->ch1gain;
378 else
379 ret = -EINVAL;
380 spin_unlock_irq(&mcbsp->lock);
381
382 return ret;
383}
384EXPORT_SYMBOL(omap_st_get_chgain);
385
386static int omap_st_start(struct omap_mcbsp *mcbsp)
387{
388 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
389
390 if (st_data && st_data->enabled && !st_data->running) {
391 omap_st_fir_write(mcbsp, st_data->taps);
392 omap_st_chgain(mcbsp);
393
394 if (!mcbsp->free) {
395 omap_st_on(mcbsp);
396 st_data->running = 1;
397 }
398 }
399
400 return 0;
401}
402
403int omap_st_enable(unsigned int id)
404{
405 struct omap_mcbsp *mcbsp;
406 struct omap_mcbsp_st_data *st_data;
407
408 if (!omap_mcbsp_check_valid_id(id)) {
409 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
410 return -ENODEV;
411 }
412
413 mcbsp = id_to_mcbsp_ptr(id);
414 st_data = mcbsp->st_data;
415
416 if (!st_data)
417 return -ENODEV;
418
419 spin_lock_irq(&mcbsp->lock);
420 st_data->enabled = 1;
421 omap_st_start(mcbsp);
422 spin_unlock_irq(&mcbsp->lock);
423
424 return 0;
425}
426EXPORT_SYMBOL(omap_st_enable);
427
428static int omap_st_stop(struct omap_mcbsp *mcbsp)
429{
430 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
431
432 if (st_data && st_data->running) {
433 if (!mcbsp->free) {
434 omap_st_off(mcbsp);
435 st_data->running = 0;
436 }
437 }
438
439 return 0;
440}
441
442int omap_st_disable(unsigned int id)
443{
444 struct omap_mcbsp *mcbsp;
445 struct omap_mcbsp_st_data *st_data;
446 int ret = 0;
447
448 if (!omap_mcbsp_check_valid_id(id)) {
449 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
450 return -ENODEV;
451 }
452
453 mcbsp = id_to_mcbsp_ptr(id);
454 st_data = mcbsp->st_data;
455
456 if (!st_data)
457 return -ENODEV;
458
459 spin_lock_irq(&mcbsp->lock);
460 omap_st_stop(mcbsp);
461 st_data->enabled = 0;
462 spin_unlock_irq(&mcbsp->lock);
463
464 return ret;
465}
466EXPORT_SYMBOL(omap_st_disable);
467
468int omap_st_is_enabled(unsigned int id)
469{
470 struct omap_mcbsp *mcbsp;
471 struct omap_mcbsp_st_data *st_data;
472
473 if (!omap_mcbsp_check_valid_id(id)) {
474 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
475 return -ENODEV;
476 }
477
478 mcbsp = id_to_mcbsp_ptr(id);
479 st_data = mcbsp->st_data;
480
481 if (!st_data)
482 return -ENODEV;
483
484
485 return st_data->enabled;
486}
487EXPORT_SYMBOL(omap_st_is_enabled);
488
7aa9ff56 489/*
451fd82d
PU		 490 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
491 * The threshold parameter is 1 based, and it is converted (threshold - 1)
492 * for the THRSH2 register.
7aa9ff56
EV		 493 */
494void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
495{
496 struct omap_mcbsp *mcbsp;
7aa9ff56 497
7aa9ff56
EV		 498 if (!omap_mcbsp_check_valid_id(id)) {
499 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
500 return;
501 }
502 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 503 if (mcbsp->pdata->buffer_size == 0)
504 return;
7aa9ff56 505
451fd82d
PU		 506 if (threshold && threshold <= mcbsp->max_tx_thres)
507 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56
EV		 508}
509EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
510
511/*
451fd82d
PU		 512 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
513 * The threshold parameter is 1 based, and it is converted (threshold - 1)
514 * for the THRSH1 register.
7aa9ff56
EV		 515 */
516void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
517{
518 struct omap_mcbsp *mcbsp;
7aa9ff56 519
7aa9ff56
EV		 520 if (!omap_mcbsp_check_valid_id(id)) {
521 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
522 return;
523 }
524 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 525 if (mcbsp->pdata->buffer_size == 0)
526 return;
7aa9ff56 527
451fd82d
PU		 528 if (threshold && threshold <= mcbsp->max_rx_thres)
529 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56
EV		 530}
531EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 532
533/*
534 * omap_mcbsp_get_max_tx_thres just return the current configured
535 * maximum threshold for transmission
536 */
537u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
538{
539 struct omap_mcbsp *mcbsp;
540
541 if (!omap_mcbsp_check_valid_id(id)) {
542 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
543 return -ENODEV;
544 }
545 mcbsp = id_to_mcbsp_ptr(id);
546
547 return mcbsp->max_tx_thres;
548}
549EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
550
551/*
552 * omap_mcbsp_get_max_rx_thres just return the current configured
553 * maximum threshold for reception
554 */
555u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
556{
557 struct omap_mcbsp *mcbsp;
558
559 if (!omap_mcbsp_check_valid_id(id)) {
560 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
561 return -ENODEV;
562 }
563 mcbsp = id_to_mcbsp_ptr(id);
564
565 return mcbsp->max_rx_thres;
566}
567EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 568
0acce82b
PU		 569u16 omap_mcbsp_get_fifo_size(unsigned int id)
570{
571 struct omap_mcbsp *mcbsp;
572
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
575 return -ENODEV;
576 }
577 mcbsp = id_to_mcbsp_ptr(id);
578
579 return mcbsp->pdata->buffer_size;
580}
581EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
582
7dc976ed
PU		 583/*
584 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
585 */
586u16 omap_mcbsp_get_tx_delay(unsigned int id)
587{
588 struct omap_mcbsp *mcbsp;
589 u16 buffstat;
590
591 if (!omap_mcbsp_check_valid_id(id)) {
592 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
593 return -ENODEV;
594 }
595 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 596 if (mcbsp->pdata->buffer_size == 0)
597 return 0;
7dc976ed
PU		 598
599 /* Returns the number of free locations in the buffer */
600 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
601
602 /* Number of slots are different in McBSP ports */
f10b8ad1 603 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed
PU		 604}
605EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
606
607/*
608 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
609 * to reach the threshold value (when the DMA will be triggered to read it)
610 */
611u16 omap_mcbsp_get_rx_delay(unsigned int id)
612{
613 struct omap_mcbsp *mcbsp;
614 u16 buffstat, threshold;
615
616 if (!omap_mcbsp_check_valid_id(id)) {
617 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
618 return -ENODEV;
619 }
620 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 621 if (mcbsp->pdata->buffer_size == 0)
622 return 0;
7dc976ed
PU		 623
624 /* Returns the number of used locations in the buffer */
625 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
626 /* RX threshold */
627 threshold = MCBSP_READ(mcbsp, THRSH1);
628
629 /* Return the number of location till we reach the threshold limit */
630 if (threshold <= buffstat)
631 return 0;
632 else
633 return threshold - buffstat;
634}
635EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
636
98cb20e8
PU		 637/*
638 * omap_mcbsp_get_dma_op_mode just return the current configured
639 * operating mode for the mcbsp channel
640 */
641int omap_mcbsp_get_dma_op_mode(unsigned int id)
642{
643 struct omap_mcbsp *mcbsp;
644 int dma_op_mode;
645
646 if (!omap_mcbsp_check_valid_id(id)) {
647 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
648 return -ENODEV;
649 }
650 mcbsp = id_to_mcbsp_ptr(id);
651
98cb20e8 652 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 653
654 return dma_op_mode;
655}
656EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6 657
5e1c5ff4
TL		 658int omap_mcbsp_request(unsigned int id)
659{
b4b58f58 660 struct omap_mcbsp *mcbsp;
c8c99699 661 void *reg_cache;
5e1c5ff4
TL		 662 int err;
663
bc5d0c89
EV		 664 if (!omap_mcbsp_check_valid_id(id)) {
665 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
666 return -ENODEV;
120db2cb 667 }
b4b58f58 668 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 669
ac6747ca 670 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
c8c99699
JK		 671 if (!reg_cache) {
672 return -ENOMEM;
673 }
674
b4b58f58
CS		 675 spin_lock(&mcbsp->lock);
676 if (!mcbsp->free) {
677 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
678 mcbsp->id);
c8c99699
JK		 679 err = -EBUSY;
680 goto err_kfree;
5e1c5ff4
TL		 681 }
682
6722a723 683 mcbsp->free = false;
c8c99699 684 mcbsp->reg_cache = reg_cache;
b4b58f58 685 spin_unlock(&mcbsp->lock);
5e1c5ff4 686
b820ce4e
RK		 687 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
688 mcbsp->pdata->ops->request(id);
689
e95496d4 690 pm_runtime_get_sync(mcbsp->dev);
b820ce4e 691
1a645884
JN		 692 /* Enable wakeup behavior */
693 if (mcbsp->pdata->has_wakeup)
694 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
2122fdc6 695
5a07055a
JN		 696 /*
697 * Make sure that transmitter, receiver and sample-rate generator are
698 * not running before activating IRQs.
699 */
8ea3200f
JK		 700 MCBSP_WRITE(mcbsp, SPCR1, 0);
701 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 702
bafe2721
JN		 703 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
704 0, "McBSP", (void *)mcbsp);
705 if (err != 0) {
706 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
707 "for McBSP%d\n", mcbsp->tx_irq,
708 mcbsp->id);
709 goto err_clk_disable;
710 }
711
712 if (mcbsp->rx_irq) {
713 err = request_irq(mcbsp->rx_irq,
714 omap_mcbsp_rx_irq_handler,
715 0, "McBSP", (void *)mcbsp);
120db2cb 716 if (err != 0) {
bafe2721
JN		 717 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
718 "for McBSP%d\n", mcbsp->rx_irq,
b4b58f58 719 mcbsp->id);
bafe2721 720 goto err_free_irq;
120db2cb 721 }
5e1c5ff4
TL		 722 }
723
5e1c5ff4 724 return 0;
c8c99699 725err_free_irq:
1866b545 726 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 727err_clk_disable:
1866b545 728 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 729 mcbsp->pdata->ops->free(id);
1866b545 730
1a645884
JN		 731 /* Disable wakeup behavior */
732 if (mcbsp->pdata->has_wakeup)
733 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 734
e95496d4 735 pm_runtime_put_sync(mcbsp->dev);
1866b545 736
c8c99699 737 spin_lock(&mcbsp->lock);
6722a723 738 mcbsp->free = true;
c8c99699
JK		 739 mcbsp->reg_cache = NULL;
740err_kfree:
741 spin_unlock(&mcbsp->lock);
742 kfree(reg_cache);
1866b545
JK		 743
744 return err;
5e1c5ff4 745}
fb78d808 746EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 747
748void omap_mcbsp_free(unsigned int id)
749{
b4b58f58 750 struct omap_mcbsp *mcbsp;
c8c99699 751 void *reg_cache;
b4b58f58 752
bc5d0c89
EV		 753 if (!omap_mcbsp_check_valid_id(id)) {
754 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 755 return;
120db2cb 756 }
b4b58f58 757 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 758
b4b58f58
CS		 759 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
760 mcbsp->pdata->ops->free(id);
bc5d0c89 761
1a645884
JN		 762 /* Disable wakeup behavior */
763 if (mcbsp->pdata->has_wakeup)
764 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 765
e95496d4 766 pm_runtime_put_sync(mcbsp->dev);
b820ce4e 767
bafe2721
JN		 768 if (mcbsp->rx_irq)
769 free_irq(mcbsp->rx_irq, (void *)mcbsp);
770 free_irq(mcbsp->tx_irq, (void *)mcbsp);
5e1c5ff4 771
c8c99699 772 reg_cache = mcbsp->reg_cache;
5e1c5ff4 773
c8c99699
JK		 774 spin_lock(&mcbsp->lock);
775 if (mcbsp->free)
776 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
777 else
6722a723 778 mcbsp->free = true;
c8c99699 779 mcbsp->reg_cache = NULL;
b4b58f58 780 spin_unlock(&mcbsp->lock);
c8c99699
JK		 781
782 if (reg_cache)
783 kfree(reg_cache);
5e1c5ff4 784}
fb78d808 785EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 786
787/*
c12abc01
JN		 788 * Here we start the McBSP, by enabling transmitter, receiver or both.
789 * If no transmitter or receiver is active prior calling, then sample-rate
790 * generator and frame sync are started.
5e1c5ff4 791 */
c12abc01 792void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 793{
b4b58f58 794 struct omap_mcbsp *mcbsp;
ce3f054b 795 int enable_srg = 0;
5e1c5ff4
TL		 796 u16 w;
797
bc5d0c89
EV		 798 if (!omap_mcbsp_check_valid_id(id)) {
799 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 800 return;
bc5d0c89 801 }
b4b58f58 802 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 803
f821eece 804 if (mcbsp->st_data)
d912fa92
EN		 805 omap_st_start(mcbsp);
806
ce3f054b
PU		 807 /* Only enable SRG, if McBSP is master */
808 w = MCBSP_READ_CACHE(mcbsp, PCR0);
809 if (w & (FSXM | FSRM | CLKXM | CLKRM))
810 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
811 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 812
ce3f054b 813 if (enable_srg) {
c12abc01 814 /* Start the sample generator */
96fbd745 815 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 816 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 817 }
5e1c5ff4
TL		 818
819 /* Enable transmitter and receiver */
d09a2afc 820 tx &= 1;
96fbd745 821 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 822 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 823
d09a2afc 824 rx &= 1;
96fbd745 825 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 826 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 827
44a6311c
EV		 828 /*
829 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
830 * REVISIT: 100us may give enough time for two CLKSRG, however
831 * due to some unknown PM related, clock gating etc. reason it
832 * is now at 500us.
833 */
834 udelay(500);
5e1c5ff4 835
ce3f054b 836 if (enable_srg) {
c12abc01 837 /* Start frame sync */
96fbd745 838 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 839 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 840 }
5e1c5ff4 841
88408230 842 if (mcbsp->pdata->has_ccr) {
d09a2afc 843 /* Release the transmitter and receiver */
96fbd745 844 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 845 w &= ~(tx ? XDISABLE : 0);
8ea3200f 846 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 847 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 848 w &= ~(rx ? RDISABLE : 0);
8ea3200f 849 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 850 }
851
5e1c5ff4
TL		 852 /* Dump McBSP Regs */
853 omap_mcbsp_dump_reg(id);
5e1c5ff4 854}
fb78d808 855EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 856
c12abc01 857void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 858{
b4b58f58 859 struct omap_mcbsp *mcbsp;
c12abc01 860 int idle;
5e1c5ff4
TL		 861 u16 w;
862
bc5d0c89
EV		 863 if (!omap_mcbsp_check_valid_id(id)) {
864 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 865 return;
bc5d0c89 866 }
5e1c5ff4 867
b4b58f58 868 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 869
fb78d808 870 /* Reset transmitter */
d09a2afc 871 tx &= 1;
88408230 872 if (mcbsp->pdata->has_ccr) {
96fbd745 873 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 874 w |= (tx ? XDISABLE : 0);
8ea3200f 875 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 876 }
96fbd745 877 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 878 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 879
880 /* Reset receiver */
d09a2afc 881 rx &= 1;
88408230 882 if (mcbsp->pdata->has_ccr) {
96fbd745 883 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 884 w |= (rx ? RDISABLE : 0);
8ea3200f 885 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 886 }
96fbd745 887 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 888 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 889
96fbd745
JK		 890 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
891 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 892
893 if (idle) {
894 /* Reset the sample rate generator */
96fbd745 895 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 896 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 897 }
d912fa92 898
f821eece 899 if (mcbsp->st_data)
d912fa92 900 omap_st_stop(mcbsp);
5e1c5ff4 901}
fb78d808 902EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 903
69d042d1
PW		 904int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
905{
09d28d2c
JN		 906 struct omap_mcbsp *mcbsp;
907 const char *src;
908
909 if (!omap_mcbsp_check_valid_id(id)) {
910 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
911 return -EINVAL;
912 }
913 mcbsp = id_to_mcbsp_ptr(id);
914
915 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
916 src = "clks_ext";
917 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
918 src = "clks_fclk";
919 else
920 return -EINVAL;
921
922 if (mcbsp->pdata->set_clk_src)
923 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
924 else
925 return -EINVAL;
69d042d1 926}
09d28d2c 927EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
69d042d1
PW		 928
929void omap2_mcbsp1_mux_clkr_src(u8 mux)
930{
7bc0c4ba
JN		 931 struct omap_mcbsp *mcbsp;
932 const char *src;
933
934 if (mux == CLKR_SRC_CLKR)
935 src = "clkr";
936 else if (mux == CLKR_SRC_CLKX)
937 src = "clkx";
938 else
939 return;
940
941 mcbsp = id_to_mcbsp_ptr(0);
942 if (mcbsp->pdata->mux_signal)
943 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
69d042d1 944}
7bc0c4ba 945EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
69d042d1
PW		 946
947void omap2_mcbsp1_mux_fsr_src(u8 mux)
948{
7bc0c4ba
JN		 949 struct omap_mcbsp *mcbsp;
950 const char *src;
951
952 if (mux == FSR_SRC_FSR)
953 src = "fsr";
954 else if (mux == FSR_SRC_FSX)
955 src = "fsx";
956 else
957 return;
958
959 mcbsp = id_to_mcbsp_ptr(0);
960 if (mcbsp->pdata->mux_signal)
961 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
69d042d1 962}
7bc0c4ba 963EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
69d042d1 964
a1a56f5f
EV		 965#define max_thres(m) (mcbsp->pdata->buffer_size)
966#define valid_threshold(m, val) ((val) <= max_thres(m))
967#define THRESHOLD_PROP_BUILDER(prop) \
968static ssize_t prop##_show(struct device *dev, \
969 struct device_attribute *attr, char *buf) \
970{ \
971 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
972 \
973 return sprintf(buf, "%u\n", mcbsp->prop); \
974} \
975 \
976static ssize_t prop##_store(struct device *dev, \
977 struct device_attribute *attr, \
978 const char *buf, size_t size) \
979{ \
980 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
981 unsigned long val; \
982 int status; \
983 \
984 status = strict_strtoul(buf, 0, &val); \
985 if (status) \
986 return status; \
987 \
988 if (!valid_threshold(mcbsp, val)) \
989 return -EDOM; \
990 \
991 mcbsp->prop = val; \
992 return size; \
993} \
994 \
995static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
996
997THRESHOLD_PROP_BUILDER(max_tx_thres);
998THRESHOLD_PROP_BUILDER(max_rx_thres);
999
9b300509
JN		 1000static const char *dma_op_modes[] = {
1001 "element", "threshold", "frame",
1002};
1003
98cb20e8
PU		 1004static ssize_t dma_op_mode_show(struct device *dev,
1005 struct device_attribute *attr, char *buf)
1006{
1007 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1008 int dma_op_mode, i = 0;
1009 ssize_t len = 0;
1010 const char * const *s;
98cb20e8 1011
98cb20e8 1012 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 1013
9b300509
JN		 1014 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1015 if (dma_op_mode == i)
1016 len += sprintf(buf + len, "[%s] ", *s);
1017 else
1018 len += sprintf(buf + len, "%s ", *s);
1019 }
1020 len += sprintf(buf + len, "\n");
1021
1022 return len;
98cb20e8
PU		 1023}
1024
1025static ssize_t dma_op_mode_store(struct device *dev,
1026 struct device_attribute *attr,
1027 const char *buf, size_t size)
1028{
1029 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1030 const char * const *s;
1031 int i = 0;
98cb20e8 1032
9b300509
JN		 1033 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1034 if (sysfs_streq(buf, *s))
1035 break;
98cb20e8 1036
9b300509
JN		 1037 if (i == ARRAY_SIZE(dma_op_modes))
1038 return -EINVAL;
98cb20e8 1039
9b300509 1040 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1041 if (!mcbsp->free) {
1042 size = -EBUSY;
1043 goto unlock;
1044 }
9b300509 1045 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1046
1047unlock:
1048 spin_unlock_irq(&mcbsp->lock);
1049
1050 return size;
1051}
1052
1053static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1054
7bba67ab
JN		 1055static const struct attribute *additional_attrs[] = {
1056 &dev_attr_max_tx_thres.attr,
1057 &dev_attr_max_rx_thres.attr,
1058 &dev_attr_dma_op_mode.attr,
1059 NULL,
1060};
1061
1062static const struct attribute_group additional_attr_group = {
1063 .attrs = (struct attribute **)additional_attrs,
1064};
1065
d912fa92
EN		 1066static ssize_t st_taps_show(struct device *dev,
1067 struct device_attribute *attr, char *buf)
1068{
1069 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1070 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1071 ssize_t status = 0;
1072 int i;
1073
1074 spin_lock_irq(&mcbsp->lock);
1075 for (i = 0; i < st_data->nr_taps; i++)
1076 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1077 st_data->taps[i]);
1078 if (i)
1079 status += sprintf(&buf[status], "\n");
1080 spin_unlock_irq(&mcbsp->lock);
1081
1082 return status;
1083}
1084
1085static ssize_t st_taps_store(struct device *dev,
1086 struct device_attribute *attr,
1087 const char *buf, size_t size)
1088{
1089 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1090 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1091 int val, tmp, status, i = 0;
1092
1093 spin_lock_irq(&mcbsp->lock);
1094 memset(st_data->taps, 0, sizeof(st_data->taps));
1095 st_data->nr_taps = 0;
1096
1097 do {
1098 status = sscanf(buf, "%d%n", &val, &tmp);
1099 if (status < 0 || status == 0) {
1100 size = -EINVAL;
1101 goto out;
1102 }
1103 if (val < -32768 || val > 32767) {
1104 size = -EINVAL;
1105 goto out;
1106 }
1107 st_data->taps[i++] = val;
1108 buf += tmp;
1109 if (*buf != ',')
1110 break;
1111 buf++;
1112 } while (1);
1113
1114 st_data->nr_taps = i;
1115
1116out:
1117 spin_unlock_irq(&mcbsp->lock);
1118
1119 return size;
1120}
1121
1122static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1123
d912fa92
EN		 1124static const struct attribute *sidetone_attrs[] = {
1125 &dev_attr_st_taps.attr,
1126 NULL,
1127};
1128
1129static const struct attribute_group sidetone_attr_group = {
1130 .attrs = (struct attribute **)sidetone_attrs,
1131};
1132
f821eece
JN		 1133static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1134 struct resource *res)
d912fa92 1135{
d912fa92
EN		 1136 struct omap_mcbsp_st_data *st_data;
1137 int err;
1138
1139 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1140 if (!st_data) {
1141 err = -ENOMEM;
1142 goto err1;
1143 }
1144
3cf32bba 1145 st_data->io_base_st = ioremap(res->start, resource_size(res));
d912fa92
EN		 1146 if (!st_data->io_base_st) {
1147 err = -ENOMEM;
1148 goto err2;
1149 }
1150
1151 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1152 if (err)
1153 goto err3;
1154
1155 mcbsp->st_data = st_data;
1156 return 0;
1157
1158err3:
1159 iounmap(st_data->io_base_st);
1160err2:
1161 kfree(st_data);
1162err1:
1163 return err;
1164
1165}
1166
1167static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1168{
1169 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1170
f821eece
JN		 1171 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1172 iounmap(st_data->io_base_st);
1173 kfree(st_data);
a1a56f5f 1174}
a1a56f5f 1175
5e1c5ff4
TL		 1176/*
1177 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1178 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1179 */
25cef225 1180static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1181{
1182 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1183 struct omap_mcbsp *mcbsp;
bc5d0c89 1184 int id = pdev->id - 1;
3cf32bba 1185 struct resource *res;
bc5d0c89 1186 int ret = 0;
5e1c5ff4 1187
bc5d0c89
EV		 1188 if (!pdata) {
1189 dev_err(&pdev->dev, "McBSP device initialized without"
1190 "platform data\n");
1191 ret = -EINVAL;
1192 goto exit;
1193 }
1194
1195 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1196
b4b58f58 1197 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1198 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1199 ret = -EINVAL;
1200 goto exit;
1201 }
1202
b4b58f58
CS		 1203 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1204 if (!mcbsp) {
1205 ret = -ENOMEM;
1206 goto exit;
1207 }
b4b58f58
CS		 1208
1209 spin_lock_init(&mcbsp->lock);
1210 mcbsp->id = id + 1;
6722a723 1211 mcbsp->free = true;
bc5d0c89 1212
3cf32bba
KVA		 1213 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1214 if (!res) {
1215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1216 if (!res) {
1217 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1218 "resource\n", __func__, pdev->id);
1219 ret = -ENOMEM;
1220 goto exit;
1221 }
1222 }
1223 mcbsp->phys_base = res->start;
ac6747ca 1224 mcbsp->reg_cache_size = resource_size(res);
3cf32bba 1225 mcbsp->io_base = ioremap(res->start, resource_size(res));
b4b58f58 1226 if (!mcbsp->io_base) {
d592dd1a
RK		 1227 ret = -ENOMEM;
1228 goto err_ioremap;
1229 }
1230
3cf32bba
KVA		 1231 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1232 if (!res)
1233 mcbsp->phys_dma_base = mcbsp->phys_base;
1234 else
1235 mcbsp->phys_dma_base = res->start;
1236
3cf32bba
KVA		 1237 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1238 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1239
cb7e9ded
KVA		 1240 /* From OMAP4 there will be a single irq line */
1241 if (mcbsp->tx_irq == -ENXIO)
1242 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1243
3cf32bba
KVA		 1244 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1245 if (!res) {
1246 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1247 __func__, pdev->id);
1248 ret = -ENODEV;
1249 goto err_res;
1250 }
1251 mcbsp->dma_rx_sync = res->start;
1252
1253 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1254 if (!res) {
1255 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1256 __func__, pdev->id);
1257 ret = -ENODEV;
1258 goto err_res;
1259 }
1260 mcbsp->dma_tx_sync = res->start;
bc5d0c89 1261
b820ce4e
RK		 1262 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1263 if (IS_ERR(mcbsp->fclk)) {
1264 ret = PTR_ERR(mcbsp->fclk);
1265 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
e95496d4 1266 goto err_res;
bc5d0c89
EV		 1267 }
1268
b4b58f58
CS		 1269 mcbsp->pdata = pdata;
1270 mcbsp->dev = &pdev->dev;
b820ce4e 1271 mcbsp_ptr[id] = mcbsp;
b4b58f58 1272 platform_set_drvdata(pdev, mcbsp);
e95496d4 1273 pm_runtime_enable(mcbsp->dev);
a1a56f5f 1274
7bba67ab
JN		 1275 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1276 if (mcbsp->pdata->buffer_size) {
1277 /*
1278 * Initially configure the maximum thresholds to a safe value.
1279 * The McBSP FIFO usage with these values should not go under
1280 * 16 locations.
1281 * If the whole FIFO without safety buffer is used, than there
1282 * is a possibility that the DMA will be not able to push the
1283 * new data on time, causing channel shifts in runtime.
1284 */
1285 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1286 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1287
1288 ret = sysfs_create_group(&mcbsp->dev->kobj,
1289 &additional_attr_group);
1290 if (ret) {
1291 dev_err(mcbsp->dev,
1292 "Unable to create additional controls\n");
1293 goto err_thres;
1294 }
1295 } else {
1296 mcbsp->max_tx_thres = -EINVAL;
1297 mcbsp->max_rx_thres = -EINVAL;
1298 }
1299
f821eece
JN		 1300 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1301 if (res) {
1302 ret = omap_st_add(mcbsp, res);
1303 if (ret) {
1304 dev_err(mcbsp->dev,
1305 "Unable to create sidetone controls\n");
1306 goto err_st;
1307 }
1308 }
a1a56f5f 1309
d592dd1a 1310 return 0;
bc5d0c89 1311
f821eece
JN		 1312err_st:
1313 if (mcbsp->pdata->buffer_size)
1314 sysfs_remove_group(&mcbsp->dev->kobj,
1315 &additional_attr_group);
7bba67ab
JN		 1316err_thres:
1317 clk_put(mcbsp->fclk);
3cf32bba 1318err_res:
b4b58f58 1319 iounmap(mcbsp->io_base);
d592dd1a 1320err_ioremap:
b820ce4e 1321 kfree(mcbsp);
bc5d0c89
EV		 1322exit:
1323 return ret;
1324}
120db2cb 1325
25cef225 1326static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1327{
bc5d0c89 1328 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1329
bc5d0c89
EV		 1330 platform_set_drvdata(pdev, NULL);
1331 if (mcbsp) {
5e1c5ff4 1332
bc5d0c89
EV		 1333 if (mcbsp->pdata && mcbsp->pdata->ops &&
1334 mcbsp->pdata->ops->free)
1335 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1336
7bba67ab
JN		 1337 if (mcbsp->pdata->buffer_size)
1338 sysfs_remove_group(&mcbsp->dev->kobj,
1339 &additional_attr_group);
1340
f821eece
JN		 1341 if (mcbsp->st_data)
1342 omap_st_remove(mcbsp);
a1a56f5f 1343
b820ce4e 1344 clk_put(mcbsp->fclk);
bc5d0c89 1345
d592dd1a 1346 iounmap(mcbsp->io_base);
5f3b7284 1347 kfree(mcbsp);
5e1c5ff4
TL		 1348 }
1349
1350 return 0;
1351}
1352
bc5d0c89
EV		 1353static struct platform_driver omap_mcbsp_driver = {
1354 .probe = omap_mcbsp_probe,
25cef225 1355 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1356 .driver = {
1357 .name = "omap-mcbsp",
1358 },
1359};
1360
0210dc4e
PU		 1361module_platform_driver(omap_mcbsp_driver);
1362
1363MODULE_AUTHOR("Samuel Ortiz <samuel.ortiz@nokia.com>");
1364MODULE_DESCRIPTION("OMAP McBSP core driver");
1365MODULE_LICENSE("GPL");
1366MODULE_ALIAS("platform:omap-mcbsp");
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