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Merge tag 'cleanup-fixes-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / sound / soc / omap / mcbsp.c
CommitLineData
5e1c5ff4 1/*
71e822e9 2 * sound/soc/omap/mcbsp.c
5e1c5ff4
TL		 3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
71e822e9
PU		 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
5e1c5ff4
TL		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
bc5d0c89 20#include <linux/platform_device.h>
5e1c5ff4
TL		 21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
5e1c5ff4 27
ce491cf8 28#include <plat/mcbsp.h>
5e1c5ff4 29
7d7e1eba
TL		 30#include <plat/cpu.h>
31
219f4316
PU		 32#include "mcbsp.h"
33
b0a330dc 34static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 35{
cdc71514
JN		 36 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
37
38 if (mcbsp->pdata->reg_size == 2) {
39 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
40 __raw_writew((u16)val, addr);
c8c99699 41 } else {
cdc71514
JN		 42 ((u32 *)mcbsp->reg_cache)[reg] = val;
43 __raw_writel(val, addr);
c8c99699 44 }
b4b58f58
CS		 45}
46
b0a330dc 47static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 48{
cdc71514
JN		 49 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
50
51 if (mcbsp->pdata->reg_size == 2) {
52 return !from_cache ? __raw_readw(addr) :
53 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 54 } else {
cdc71514
JN		 55 return !from_cache ? __raw_readl(addr) :
56 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 57 }
b4b58f58
CS		 58}
59
b0a330dc 60static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 61{
62 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
63}
64
b0a330dc 65static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 66{
67 return __raw_readl(mcbsp->st_data->io_base_st + reg);
68}
d912fa92 69
8ea3200f 70#define MCBSP_READ(mcbsp, reg) \
c8c99699 71 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 72#define MCBSP_WRITE(mcbsp, reg, val) \
73 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 74#define MCBSP_READ_CACHE(mcbsp, reg) \
75 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 76
d912fa92
EN		 77#define MCBSP_ST_READ(mcbsp, reg) \
78 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
79#define MCBSP_ST_WRITE(mcbsp, reg, val) \
80 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
81
45656b44 82static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
5e1c5ff4 83{
b4b58f58
CS		 84 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
85 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 86 MCBSP_READ(mcbsp, DRR2));
b4b58f58 87 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 88 MCBSP_READ(mcbsp, DRR1));
b4b58f58 89 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 90 MCBSP_READ(mcbsp, DXR2));
b4b58f58 91 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 92 MCBSP_READ(mcbsp, DXR1));
b4b58f58 93 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 94 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 95 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 96 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 97 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 98 MCBSP_READ(mcbsp, RCR2));
b4b58f58 99 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 100 MCBSP_READ(mcbsp, RCR1));
b4b58f58 101 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 102 MCBSP_READ(mcbsp, XCR2));
b4b58f58 103 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 104 MCBSP_READ(mcbsp, XCR1));
b4b58f58 105 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 106 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 107 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 108 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 109 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 110 MCBSP_READ(mcbsp, PCR0));
b4b58f58 111 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 112}
113
35d210fa
PU		 114static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
115{
116 struct omap_mcbsp *mcbsp = dev_id;
117 u16 irqst;
118
119 irqst = MCBSP_READ(mcbsp, IRQST);
120 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
121
122 if (irqst & RSYNCERREN)
123 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
124 if (irqst & RFSREN)
125 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
126 if (irqst & REOFEN)
127 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
128 if (irqst & RRDYEN)
129 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
130 if (irqst & RUNDFLEN)
131 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
132 if (irqst & ROVFLEN)
133 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
134
135 if (irqst & XSYNCERREN)
136 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
137 if (irqst & XFSXEN)
138 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
139 if (irqst & XEOFEN)
140 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
141 if (irqst & XRDYEN)
142 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
143 if (irqst & XUNDFLEN)
144 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
145 if (irqst & XOVFLEN)
146 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
147 if (irqst & XEMPTYEOFEN)
148 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
149
150 MCBSP_WRITE(mcbsp, IRQST, irqst);
151
152 return IRQ_HANDLED;
153}
154
0cd61b68 155static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 156{
e8f2af17 157 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 158 u16 irqst_spcr2;
5e1c5ff4 159
8ea3200f 160 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 161 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 162
d6d834b0
EN		 163 if (irqst_spcr2 & XSYNC_ERR) {
164 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
165 irqst_spcr2);
166 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 167 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 168 }
fb78d808 169
5e1c5ff4
TL		 170 return IRQ_HANDLED;
171}
172
0cd61b68 173static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 174{
e8f2af17 175 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 176 u16 irqst_spcr1;
177
8ea3200f 178 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 179 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
180
181 if (irqst_spcr1 & RSYNC_ERR) {
182 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
183 irqst_spcr1);
184 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 185 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 186 }
fb78d808 187
5e1c5ff4
TL		 188 return IRQ_HANDLED;
189}
190
5e1c5ff4
TL		 191/*
192 * omap_mcbsp_config simply write a config to the
193 * appropriate McBSP.
194 * You either call this function or set the McBSP registers
195 * by yourself before calling omap_mcbsp_start().
196 */
45656b44
PU		 197void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
198 const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 199{
b4b58f58
CS		 200 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
201 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 202
203 /* We write the given config */
8ea3200f
JK		 204 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
205 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
206 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
207 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
208 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
209 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
210 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
211 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
212 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
213 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
214 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 215 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 216 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
217 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 218 }
08905d8a
PU		 219 /* Enable wakeup behavior */
220 if (mcbsp->pdata->has_wakeup)
221 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
35d210fa
PU		 222
223 /* Enable TX/RX sync error interrupts by default */
224 if (mcbsp->irq)
225 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
5e1c5ff4 226}
5e1c5ff4 227
9504ba64
KVA		 228/**
229 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
230 * @id - mcbsp id
231 * @stream - indicates the direction of data flow (rx or tx)
232 *
233 * Returns the address of mcbsp data transmit register or data receive register
234 * to be used by DMA for transferring/receiving data based on the value of
235 * @stream for the requested mcbsp given by @id
236 */
b8fb4907
PU		 237static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
238 unsigned int stream)
9504ba64 239{
9504ba64
KVA		 240 int data_reg;
241
cdc71514 242 if (mcbsp->pdata->reg_size == 2) {
9504ba64 243 if (stream)
cdc71514 244 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 245 else
cdc71514 246 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 247 } else {
248 if (stream)
cdc71514 249 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 250 else
cdc71514 251 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 252 }
253
cdc71514 254 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64 255}
9504ba64 256
d912fa92
EN		 257static void omap_st_on(struct omap_mcbsp *mcbsp)
258{
259 unsigned int w;
260
1743d14f
JN		 261 if (mcbsp->pdata->enable_st_clock)
262 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
d912fa92
EN		 263
264 /* Enable McBSP Sidetone */
265 w = MCBSP_READ(mcbsp, SSELCR);
266 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
267
d912fa92
EN		 268 /* Enable Sidetone from Sidetone Core */
269 w = MCBSP_ST_READ(mcbsp, SSELCR);
270 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
271}
272
273static void omap_st_off(struct omap_mcbsp *mcbsp)
274{
275 unsigned int w;
276
277 w = MCBSP_ST_READ(mcbsp, SSELCR);
278 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
279
d912fa92
EN		 280 w = MCBSP_READ(mcbsp, SSELCR);
281 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
282
1743d14f
JN		 283 if (mcbsp->pdata->enable_st_clock)
284 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
d912fa92
EN		 285}
286
287static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
288{
289 u16 val, i;
d912fa92
EN		 290
291 val = MCBSP_ST_READ(mcbsp, SSELCR);
292
293 if (val & ST_COEFFWREN)
294 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
295
296 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
297
298 for (i = 0; i < 128; i++)
299 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
300
301 i = 0;
302
303 val = MCBSP_ST_READ(mcbsp, SSELCR);
304 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
305 val = MCBSP_ST_READ(mcbsp, SSELCR);
306
307 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
308
309 if (i == 1000)
310 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
311}
312
313static void omap_st_chgain(struct omap_mcbsp *mcbsp)
314{
315 u16 w;
316 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 317
318 w = MCBSP_ST_READ(mcbsp, SSELCR);
319
320 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
321 ST_CH1GAIN(st_data->ch1gain));
322}
323
45656b44 324int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
d912fa92 325{
e2002ab3 326 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 327 int ret = 0;
328
d912fa92
EN		 329 if (!st_data)
330 return -ENOENT;
331
332 spin_lock_irq(&mcbsp->lock);
333 if (channel == 0)
334 st_data->ch0gain = chgain;
335 else if (channel == 1)
336 st_data->ch1gain = chgain;
337 else
338 ret = -EINVAL;
339
340 if (st_data->enabled)
341 omap_st_chgain(mcbsp);
342 spin_unlock_irq(&mcbsp->lock);
343
344 return ret;
345}
d912fa92 346
45656b44 347int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
d912fa92 348{
e2002ab3 349 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 350 int ret = 0;
351
d912fa92
EN		 352 if (!st_data)
353 return -ENOENT;
354
355 spin_lock_irq(&mcbsp->lock);
356 if (channel == 0)
357 *chgain = st_data->ch0gain;
358 else if (channel == 1)
359 *chgain = st_data->ch1gain;
360 else
361 ret = -EINVAL;
362 spin_unlock_irq(&mcbsp->lock);
363
364 return ret;
365}
d912fa92
EN		 366
367static int omap_st_start(struct omap_mcbsp *mcbsp)
368{
369 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
370
58db1dcd 371 if (st_data->enabled && !st_data->running) {
d912fa92
EN		 372 omap_st_fir_write(mcbsp, st_data->taps);
373 omap_st_chgain(mcbsp);
374
375 if (!mcbsp->free) {
376 omap_st_on(mcbsp);
377 st_data->running = 1;
378 }
379 }
380
381 return 0;
382}
383
45656b44 384int omap_st_enable(struct omap_mcbsp *mcbsp)
d912fa92 385{
e2002ab3 386 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 387
388 if (!st_data)
389 return -ENODEV;
390
391 spin_lock_irq(&mcbsp->lock);
392 st_data->enabled = 1;
393 omap_st_start(mcbsp);
394 spin_unlock_irq(&mcbsp->lock);
395
396 return 0;
397}
d912fa92
EN		 398
399static int omap_st_stop(struct omap_mcbsp *mcbsp)
400{
401 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
402
58db1dcd 403 if (st_data->running) {
d912fa92
EN		 404 if (!mcbsp->free) {
405 omap_st_off(mcbsp);
406 st_data->running = 0;
407 }
408 }
409
410 return 0;
411}
412
45656b44 413int omap_st_disable(struct omap_mcbsp *mcbsp)
d912fa92 414{
e2002ab3 415 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 416 int ret = 0;
417
d912fa92
EN		 418 if (!st_data)
419 return -ENODEV;
420
421 spin_lock_irq(&mcbsp->lock);
422 omap_st_stop(mcbsp);
423 st_data->enabled = 0;
424 spin_unlock_irq(&mcbsp->lock);
425
426 return ret;
427}
d912fa92 428
45656b44 429int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
d912fa92 430{
e2002ab3 431 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 432
433 if (!st_data)
434 return -ENODEV;
435
d912fa92
EN		 436 return st_data->enabled;
437}
d912fa92 438
7aa9ff56 439/*
451fd82d
PU		 440 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
441 * The threshold parameter is 1 based, and it is converted (threshold - 1)
442 * for the THRSH2 register.
7aa9ff56 443 */
45656b44 444void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 445{
7bba67ab
JN		 446 if (mcbsp->pdata->buffer_size == 0)
447 return;
7aa9ff56 448
451fd82d
PU		 449 if (threshold && threshold <= mcbsp->max_tx_thres)
450 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56 451}
7aa9ff56
EV		 452
453/*
451fd82d
PU		 454 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
455 * The threshold parameter is 1 based, and it is converted (threshold - 1)
456 * for the THRSH1 register.
7aa9ff56 457 */
45656b44 458void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 459{
7bba67ab
JN		 460 if (mcbsp->pdata->buffer_size == 0)
461 return;
7aa9ff56 462
451fd82d
PU		 463 if (threshold && threshold <= mcbsp->max_rx_thres)
464 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56 465}
a1a56f5f 466
7dc976ed
PU		 467/*
468 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
469 */
45656b44 470u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 471{
7dc976ed
PU		 472 u16 buffstat;
473
7bba67ab
JN		 474 if (mcbsp->pdata->buffer_size == 0)
475 return 0;
7dc976ed
PU		 476
477 /* Returns the number of free locations in the buffer */
478 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
479
480 /* Number of slots are different in McBSP ports */
f10b8ad1 481 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed 482}
7dc976ed
PU		 483
484/*
485 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
486 * to reach the threshold value (when the DMA will be triggered to read it)
487 */
45656b44 488u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 489{
7dc976ed
PU		 490 u16 buffstat, threshold;
491
7bba67ab
JN		 492 if (mcbsp->pdata->buffer_size == 0)
493 return 0;
7dc976ed
PU		 494
495 /* Returns the number of used locations in the buffer */
496 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
497 /* RX threshold */
498 threshold = MCBSP_READ(mcbsp, THRSH1);
499
500 /* Return the number of location till we reach the threshold limit */
501 if (threshold <= buffstat)
502 return 0;
503 else
504 return threshold - buffstat;
505}
7dc976ed 506
45656b44 507int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
5e1c5ff4 508{
c8c99699 509 void *reg_cache;
5e1c5ff4
TL		 510 int err;
511
ac6747ca 512 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
c8c99699
JK		 513 if (!reg_cache) {
514 return -ENOMEM;
515 }
516
b4b58f58
CS		 517 spin_lock(&mcbsp->lock);
518 if (!mcbsp->free) {
519 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
520 mcbsp->id);
c8c99699
JK		 521 err = -EBUSY;
522 goto err_kfree;
5e1c5ff4
TL		 523 }
524
6722a723 525 mcbsp->free = false;
c8c99699 526 mcbsp->reg_cache = reg_cache;
b4b58f58 527 spin_unlock(&mcbsp->lock);
5e1c5ff4 528
b820ce4e 529 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
45656b44 530 mcbsp->pdata->ops->request(mcbsp->id - 1);
b820ce4e 531
5a07055a
JN		 532 /*
533 * Make sure that transmitter, receiver and sample-rate generator are
534 * not running before activating IRQs.
535 */
8ea3200f
JK		 536 MCBSP_WRITE(mcbsp, SPCR1, 0);
537 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 538
35d210fa
PU		 539 if (mcbsp->irq) {
540 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
541 "McBSP", (void *)mcbsp);
542 if (err != 0) {
543 dev_err(mcbsp->dev, "Unable to request IRQ\n");
544 goto err_clk_disable;
545 }
546 } else {
547 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
548 "McBSP TX", (void *)mcbsp);
549 if (err != 0) {
550 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
551 goto err_clk_disable;
552 }
bafe2721 553
35d210fa
PU		 554 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
555 "McBSP RX", (void *)mcbsp);
120db2cb 556 if (err != 0) {
35d210fa 557 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
bafe2721 558 goto err_free_irq;
120db2cb 559 }
5e1c5ff4
TL		 560 }
561
5e1c5ff4 562 return 0;
c8c99699 563err_free_irq:
1866b545 564 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 565err_clk_disable:
1866b545 566 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 567 mcbsp->pdata->ops->free(mcbsp->id - 1);
1866b545 568
1a645884
JN		 569 /* Disable wakeup behavior */
570 if (mcbsp->pdata->has_wakeup)
571 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 572
c8c99699 573 spin_lock(&mcbsp->lock);
6722a723 574 mcbsp->free = true;
c8c99699
JK		 575 mcbsp->reg_cache = NULL;
576err_kfree:
577 spin_unlock(&mcbsp->lock);
578 kfree(reg_cache);
1866b545
JK		 579
580 return err;
5e1c5ff4
TL		 581}
582
45656b44 583void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
5e1c5ff4 584{
c8c99699 585 void *reg_cache;
b4b58f58 586
b4b58f58 587 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 588 mcbsp->pdata->ops->free(mcbsp->id - 1);
bc5d0c89 589
1a645884
JN		 590 /* Disable wakeup behavior */
591 if (mcbsp->pdata->has_wakeup)
592 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 593
35d210fa
PU		 594 /* Disable interrupt requests */
595 if (mcbsp->irq)
596 MCBSP_WRITE(mcbsp, IRQEN, 0);
597
598 if (mcbsp->irq) {
599 free_irq(mcbsp->irq, (void *)mcbsp);
600 } else {
bafe2721 601 free_irq(mcbsp->rx_irq, (void *)mcbsp);
35d210fa
PU		 602 free_irq(mcbsp->tx_irq, (void *)mcbsp);
603 }
5e1c5ff4 604
c8c99699 605 reg_cache = mcbsp->reg_cache;
5e1c5ff4 606
e386615c
PU		 607 /*
608 * Select CLKS source from internal source unconditionally before
609 * marking the McBSP port as free.
610 * If the external clock source via MCBSP_CLKS pin has been selected the
611 * system will refuse to enter idle if the CLKS pin source is not reset
612 * back to internal source.
613 */
614 if (!cpu_class_is_omap1())
615 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
616
c8c99699
JK		 617 spin_lock(&mcbsp->lock);
618 if (mcbsp->free)
619 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
620 else
6722a723 621 mcbsp->free = true;
c8c99699 622 mcbsp->reg_cache = NULL;
b4b58f58 623 spin_unlock(&mcbsp->lock);
c8c99699
JK		 624
625 if (reg_cache)
626 kfree(reg_cache);
5e1c5ff4
TL		 627}
628
629/*
c12abc01
JN		 630 * Here we start the McBSP, by enabling transmitter, receiver or both.
631 * If no transmitter or receiver is active prior calling, then sample-rate
632 * generator and frame sync are started.
5e1c5ff4 633 */
45656b44 634void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 635{
ce3f054b 636 int enable_srg = 0;
5e1c5ff4
TL		 637 u16 w;
638
f821eece 639 if (mcbsp->st_data)
d912fa92
EN		 640 omap_st_start(mcbsp);
641
ce3f054b
PU		 642 /* Only enable SRG, if McBSP is master */
643 w = MCBSP_READ_CACHE(mcbsp, PCR0);
644 if (w & (FSXM | FSRM | CLKXM | CLKRM))
645 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
646 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 647
ce3f054b 648 if (enable_srg) {
c12abc01 649 /* Start the sample generator */
96fbd745 650 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 651 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 652 }
5e1c5ff4
TL		 653
654 /* Enable transmitter and receiver */
d09a2afc 655 tx &= 1;
96fbd745 656 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 657 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 658
d09a2afc 659 rx &= 1;
96fbd745 660 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 661 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 662
44a6311c
EV		 663 /*
664 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
665 * REVISIT: 100us may give enough time for two CLKSRG, however
666 * due to some unknown PM related, clock gating etc. reason it
667 * is now at 500us.
668 */
669 udelay(500);
5e1c5ff4 670
ce3f054b 671 if (enable_srg) {
c12abc01 672 /* Start frame sync */
96fbd745 673 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 674 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 675 }
5e1c5ff4 676
88408230 677 if (mcbsp->pdata->has_ccr) {
d09a2afc 678 /* Release the transmitter and receiver */
96fbd745 679 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 680 w &= ~(tx ? XDISABLE : 0);
8ea3200f 681 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 682 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 683 w &= ~(rx ? RDISABLE : 0);
8ea3200f 684 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 685 }
686
5e1c5ff4 687 /* Dump McBSP Regs */
45656b44 688 omap_mcbsp_dump_reg(mcbsp);
5e1c5ff4
TL		 689}
690
45656b44 691void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 692{
c12abc01 693 int idle;
5e1c5ff4
TL		 694 u16 w;
695
fb78d808 696 /* Reset transmitter */
d09a2afc 697 tx &= 1;
88408230 698 if (mcbsp->pdata->has_ccr) {
96fbd745 699 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 700 w |= (tx ? XDISABLE : 0);
8ea3200f 701 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 702 }
96fbd745 703 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 704 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 705
706 /* Reset receiver */
d09a2afc 707 rx &= 1;
88408230 708 if (mcbsp->pdata->has_ccr) {
96fbd745 709 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 710 w |= (rx ? RDISABLE : 0);
8ea3200f 711 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 712 }
96fbd745 713 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 714 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 715
96fbd745
JK		 716 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
717 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 718
719 if (idle) {
720 /* Reset the sample rate generator */
96fbd745 721 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 722 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 723 }
d912fa92 724
f821eece 725 if (mcbsp->st_data)
d912fa92 726 omap_st_stop(mcbsp);
5e1c5ff4 727}
5e1c5ff4 728
45656b44 729int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
69d042d1 730{
09d28d2c
JN		 731 const char *src;
732
09d28d2c
JN		 733 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
734 src = "clks_ext";
735 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
736 src = "clks_fclk";
737 else
738 return -EINVAL;
739
740 if (mcbsp->pdata->set_clk_src)
741 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
742 else
743 return -EINVAL;
69d042d1
PW		 744}
745
cd1f08c7 746int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
69d042d1 747{
cd1f08c7 748 const char *signal, *src;
5788c62e 749
d0db84e7 750 if (!mcbsp->pdata->mux_signal)
5788c62e 751 return -EINVAL;
45656b44 752
cd1f08c7
PU		 753 switch (mux) {
754 case CLKR_SRC_CLKR:
755 signal = "clkr";
7bc0c4ba 756 src = "clkr";
cd1f08c7
PU		 757 break;
758 case CLKR_SRC_CLKX:
759 signal = "clkr";
7bc0c4ba 760 src = "clkx";
cd1f08c7
PU		 761 break;
762 case FSR_SRC_FSR:
763 signal = "fsr";
7bc0c4ba 764 src = "fsr";
cd1f08c7
PU		 765 break;
766 case FSR_SRC_FSX:
767 signal = "fsr";
7bc0c4ba 768 src = "fsx";
cd1f08c7
PU		 769 break;
770 default:
771 return -EINVAL;
772 }
7bc0c4ba 773
5788c62e 774 return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
69d042d1 775}
69d042d1 776
a1a56f5f
EV		 777#define max_thres(m) (mcbsp->pdata->buffer_size)
778#define valid_threshold(m, val) ((val) <= max_thres(m))
779#define THRESHOLD_PROP_BUILDER(prop) \
780static ssize_t prop##_show(struct device *dev, \
781 struct device_attribute *attr, char *buf) \
782{ \
783 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
784 \
785 return sprintf(buf, "%u\n", mcbsp->prop); \
786} \
787 \
788static ssize_t prop##_store(struct device *dev, \
789 struct device_attribute *attr, \
790 const char *buf, size_t size) \
791{ \
792 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
793 unsigned long val; \
794 int status; \
795 \
796 status = strict_strtoul(buf, 0, &val); \
797 if (status) \
798 return status; \
799 \
800 if (!valid_threshold(mcbsp, val)) \
801 return -EDOM; \
802 \
803 mcbsp->prop = val; \
804 return size; \
805} \
806 \
807static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
808
809THRESHOLD_PROP_BUILDER(max_tx_thres);
810THRESHOLD_PROP_BUILDER(max_rx_thres);
811
9b300509 812static const char *dma_op_modes[] = {
09fa37ac 813 "element", "threshold",
9b300509
JN		 814};
815
98cb20e8
PU		 816static ssize_t dma_op_mode_show(struct device *dev,
817 struct device_attribute *attr, char *buf)
818{
819 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 820 int dma_op_mode, i = 0;
821 ssize_t len = 0;
822 const char * const *s;
98cb20e8 823
98cb20e8 824 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 825
9b300509
JN		 826 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
827 if (dma_op_mode == i)
828 len += sprintf(buf + len, "[%s] ", *s);
829 else
830 len += sprintf(buf + len, "%s ", *s);
831 }
832 len += sprintf(buf + len, "\n");
833
834 return len;
98cb20e8
PU		 835}
836
837static ssize_t dma_op_mode_store(struct device *dev,
838 struct device_attribute *attr,
839 const char *buf, size_t size)
840{
841 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 842 const char * const *s;
843 int i = 0;
98cb20e8 844
9b300509
JN		 845 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
846 if (sysfs_streq(buf, *s))
847 break;
98cb20e8 848
9b300509
JN		 849 if (i == ARRAY_SIZE(dma_op_modes))
850 return -EINVAL;
98cb20e8 851
9b300509 852 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 853 if (!mcbsp->free) {
854 size = -EBUSY;
855 goto unlock;
856 }
9b300509 857 mcbsp->dma_op_mode = i;
98cb20e8
PU		 858
859unlock:
860 spin_unlock_irq(&mcbsp->lock);
861
862 return size;
863}
864
865static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
866
7bba67ab
JN		 867static const struct attribute *additional_attrs[] = {
868 &dev_attr_max_tx_thres.attr,
869 &dev_attr_max_rx_thres.attr,
870 &dev_attr_dma_op_mode.attr,
871 NULL,
872};
873
874static const struct attribute_group additional_attr_group = {
875 .attrs = (struct attribute **)additional_attrs,
876};
877
d912fa92
EN		 878static ssize_t st_taps_show(struct device *dev,
879 struct device_attribute *attr, char *buf)
880{
881 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
882 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
883 ssize_t status = 0;
884 int i;
885
886 spin_lock_irq(&mcbsp->lock);
887 for (i = 0; i < st_data->nr_taps; i++)
888 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
889 st_data->taps[i]);
890 if (i)
891 status += sprintf(&buf[status], "\n");
892 spin_unlock_irq(&mcbsp->lock);
893
894 return status;
895}
896
897static ssize_t st_taps_store(struct device *dev,
898 struct device_attribute *attr,
899 const char *buf, size_t size)
900{
901 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
902 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
903 int val, tmp, status, i = 0;
904
905 spin_lock_irq(&mcbsp->lock);
906 memset(st_data->taps, 0, sizeof(st_data->taps));
907 st_data->nr_taps = 0;
908
909 do {
910 status = sscanf(buf, "%d%n", &val, &tmp);
911 if (status < 0 || status == 0) {
912 size = -EINVAL;
913 goto out;
914 }
915 if (val < -32768 || val > 32767) {
916 size = -EINVAL;
917 goto out;
918 }
919 st_data->taps[i++] = val;
920 buf += tmp;
921 if (*buf != ',')
922 break;
923 buf++;
924 } while (1);
925
926 st_data->nr_taps = i;
927
928out:
929 spin_unlock_irq(&mcbsp->lock);
930
931 return size;
932}
933
934static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
935
d912fa92
EN		 936static const struct attribute *sidetone_attrs[] = {
937 &dev_attr_st_taps.attr,
938 NULL,
939};
940
941static const struct attribute_group sidetone_attr_group = {
942 .attrs = (struct attribute **)sidetone_attrs,
943};
944
f821eece
JN		 945static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
946 struct resource *res)
d912fa92 947{
d912fa92
EN		 948 struct omap_mcbsp_st_data *st_data;
949 int err;
950
2ee65950
PU		 951 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
952 if (!st_data)
953 return -ENOMEM;
d912fa92 954
2ee65950
PU		 955 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
956 resource_size(res));
957 if (!st_data->io_base_st)
958 return -ENOMEM;
d912fa92
EN		 959
960 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
961 if (err)
2ee65950 962 return err;
d912fa92
EN		 963
964 mcbsp->st_data = st_data;
965 return 0;
a1a56f5f 966}
a1a56f5f 967
5e1c5ff4
TL		 968/*
969 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
970 * 730 has only 2 McBSP, and both of them are MPU peripherals.
971 */
2ee65950 972int __devinit omap_mcbsp_init(struct platform_device *pdev)
bc5d0c89 973{
2ee65950 974 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
3cf32bba 975 struct resource *res;
bc5d0c89 976 int ret = 0;
5e1c5ff4 977
b4b58f58 978 spin_lock_init(&mcbsp->lock);
6722a723 979 mcbsp->free = true;
bc5d0c89 980
3cf32bba
KVA		 981 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
982 if (!res) {
983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
984 if (!res) {
2ee65950
PU		 985 dev_err(mcbsp->dev, "invalid memory resource\n");
986 return -ENOMEM;
3cf32bba
KVA		 987 }
988 }
2ee65950
PU		 989 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
990 dev_name(&pdev->dev))) {
991 dev_err(mcbsp->dev, "memory region already claimed\n");
992 return -ENODEV;
993 }
994
3cf32bba 995 mcbsp->phys_base = res->start;
ac6747ca 996 mcbsp->reg_cache_size = resource_size(res);
2ee65950
PU		 997 mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
998 resource_size(res));
999 if (!mcbsp->io_base)
1000 return -ENOMEM;
d592dd1a 1001
3cf32bba
KVA		 1002 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1003 if (!res)
1004 mcbsp->phys_dma_base = mcbsp->phys_base;
1005 else
1006 mcbsp->phys_dma_base = res->start;
1007
35d210fa
PU		 1008 /*
1009 * OMAP1, 2 uses two interrupt lines: TX, RX
1010 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1011 * OMAP4 and newer SoC only have the combined IRQ line.
1012 * Use the combined IRQ if available since it gives better debugging
1013 * possibilities.
1014 */
1015 mcbsp->irq = platform_get_irq_byname(pdev, "common");
1016 if (mcbsp->irq == -ENXIO) {
1017 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1018
1019 if (mcbsp->tx_irq == -ENXIO) {
1020 mcbsp->irq = platform_get_irq(pdev, 0);
1021 mcbsp->tx_irq = 0;
1022 } else {
1023 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1024 mcbsp->irq = 0;
1025 }
73c9522e 1026 }
cb7e9ded 1027
3cf32bba
KVA		 1028 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1029 if (!res) {
2ee65950
PU		 1030 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1031 return -ENODEV;
3cf32bba 1032 }
b8fb4907
PU		 1033 /* RX DMA request number, and port address configuration */
1034 mcbsp->dma_data[1].name = "Audio Capture";
1035 mcbsp->dma_data[1].dma_req = res->start;
1036 mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
3cf32bba
KVA		 1037
1038 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1039 if (!res) {
2ee65950
PU		 1040 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1041 return -ENODEV;
3cf32bba 1042 }
b8fb4907
PU		 1043 /* TX DMA request number, and port address configuration */
1044 mcbsp->dma_data[0].name = "Audio Playback";
1045 mcbsp->dma_data[0].dma_req = res->start;
1046 mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
bc5d0c89 1047
b820ce4e
RK		 1048 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1049 if (IS_ERR(mcbsp->fclk)) {
1050 ret = PTR_ERR(mcbsp->fclk);
2ee65950
PU		 1051 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1052 return ret;
bc5d0c89
EV		 1053 }
1054
7bba67ab
JN		 1055 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1056 if (mcbsp->pdata->buffer_size) {
1057 /*
1058 * Initially configure the maximum thresholds to a safe value.
1059 * The McBSP FIFO usage with these values should not go under
1060 * 16 locations.
1061 * If the whole FIFO without safety buffer is used, than there
1062 * is a possibility that the DMA will be not able to push the
1063 * new data on time, causing channel shifts in runtime.
1064 */
1065 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1066 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1067
1068 ret = sysfs_create_group(&mcbsp->dev->kobj,
1069 &additional_attr_group);
1070 if (ret) {
1071 dev_err(mcbsp->dev,
1072 "Unable to create additional controls\n");
1073 goto err_thres;
1074 }
1075 } else {
1076 mcbsp->max_tx_thres = -EINVAL;
1077 mcbsp->max_rx_thres = -EINVAL;
1078 }
1079
f821eece
JN		 1080 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1081 if (res) {
1082 ret = omap_st_add(mcbsp, res);
1083 if (ret) {
1084 dev_err(mcbsp->dev,
1085 "Unable to create sidetone controls\n");
1086 goto err_st;
1087 }
1088 }
a1a56f5f 1089
d592dd1a 1090 return 0;
bc5d0c89 1091
f821eece
JN		 1092err_st:
1093 if (mcbsp->pdata->buffer_size)
2ee65950 1094 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
7bba67ab
JN		 1095err_thres:
1096 clk_put(mcbsp->fclk);
bc5d0c89
EV		 1097 return ret;
1098}
120db2cb 1099
2ee65950 1100void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
5e1c5ff4 1101{
2ee65950
PU		 1102 if (mcbsp->pdata->buffer_size)
1103 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
5e1c5ff4 1104
2ee65950
PU		 1105 if (mcbsp->st_data)
1106 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
5e1c5ff4 1107}
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