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2e74796a JN |
1 | /* |
2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
7ec41ee5 | 6 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> |
56a87429 | 7 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
2e74796a JN |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <sound/core.h> | |
29 | #include <sound/pcm.h> | |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/soc.h> | |
33 | ||
ce491cf8 TL |
34 | #include <plat/dma.h> |
35 | #include <plat/mcbsp.h> | |
219f4316 | 36 | #include "mcbsp.h" |
2e74796a JN |
37 | #include "omap-mcbsp.h" |
38 | #include "omap-pcm.h" | |
39 | ||
0b604856 | 40 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) |
2e74796a | 41 | |
83905c13 IK |
42 | #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ |
43 | xhandler_get, xhandler_put) \ | |
44 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
45 | .info = omap_mcbsp_st_info_volsw, \ | |
46 | .get = xhandler_get, .put = xhandler_put, \ | |
47 | .private_value = (unsigned long) &(struct soc_mixer_control) \ | |
48 | {.min = xmin, .max = xmax} } | |
49 | ||
219f4316 PU |
50 | enum { |
51 | OMAP_MCBSP_WORD_8 = 0, | |
52 | OMAP_MCBSP_WORD_12, | |
53 | OMAP_MCBSP_WORD_16, | |
54 | OMAP_MCBSP_WORD_20, | |
55 | OMAP_MCBSP_WORD_24, | |
56 | OMAP_MCBSP_WORD_32, | |
57 | }; | |
58 | ||
2e74796a JN |
59 | struct omap_mcbsp_data { |
60 | unsigned int bus_id; | |
61 | struct omap_mcbsp_reg_cfg regs; | |
ba9d0fd0 | 62 | unsigned int fmt; |
2e74796a JN |
63 | /* |
64 | * Flags indicating is the bus already activated and configured by | |
65 | * another substream | |
66 | */ | |
67 | int active; | |
68 | int configured; | |
5f63ef99 GG |
69 | unsigned int in_freq; |
70 | int clk_div; | |
3f024039 | 71 | int wlen; |
2e74796a JN |
72 | }; |
73 | ||
2e74796a JN |
74 | static struct omap_mcbsp_data mcbsp_data[NUM_LINKS]; |
75 | ||
76 | /* | |
77 | * Stream DMA parameters. DMA request line and port address are set runtime | |
78 | * since they are different between OMAP1 and later OMAPs | |
79 | */ | |
2e89713a | 80 | static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; |
2e74796a | 81 | |
caebc0cb EV |
82 | static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) |
83 | { | |
84 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad LG |
85 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
86 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); | |
cf80e158 | 87 | struct omap_pcm_dma_data *dma_data; |
a0a499c5 | 88 | int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id); |
3f024039 | 89 | int words; |
a0a499c5 | 90 | |
f0fba2ad | 91 | dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
cf80e158 | 92 | |
a0a499c5 EV |
93 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ |
94 | if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) | |
cf80e158 PU |
95 | /* |
96 | * Configure McBSP threshold based on either: | |
97 | * packet_size, when the sDMA is in packet mode, or | |
98 | * based on the period size. | |
99 | */ | |
100 | if (dma_data->packet_size) | |
101 | words = dma_data->packet_size; | |
102 | else | |
103 | words = snd_pcm_lib_period_bytes(substream) / | |
3f024039 | 104 | (mcbsp_data->wlen / 8); |
a0a499c5 | 105 | else |
3f024039 | 106 | words = 1; |
caebc0cb EV |
107 | |
108 | /* Configure McBSP internal buffer usage */ | |
109 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3f024039 | 110 | omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words); |
caebc0cb | 111 | else |
3f024039 | 112 | omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words); |
caebc0cb EV |
113 | } |
114 | ||
ddc29b01 PU |
115 | static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, |
116 | struct snd_pcm_hw_rule *rule) | |
117 | { | |
118 | struct snd_interval *buffer_size = hw_param_interval(params, | |
119 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE); | |
120 | struct snd_interval *channels = hw_param_interval(params, | |
121 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
122 | struct omap_mcbsp_data *mcbsp_data = rule->private; | |
123 | struct snd_interval frames; | |
124 | int size; | |
125 | ||
126 | snd_interval_any(&frames); | |
127 | size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id); | |
128 | ||
129 | frames.min = size / channels->min; | |
130 | frames.integer = 1; | |
131 | return snd_interval_refine(buffer_size, &frames); | |
132 | } | |
133 | ||
dee89c4d | 134 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 135 | struct snd_soc_dai *cpu_dai) |
2e74796a | 136 | { |
f0fba2ad | 137 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
caebc0cb | 138 | int bus_id = mcbsp_data->bus_id; |
2e74796a JN |
139 | int err = 0; |
140 | ||
caebc0cb EV |
141 | if (!cpu_dai->active) |
142 | err = omap_mcbsp_request(bus_id); | |
143 | ||
ddc29b01 PU |
144 | /* |
145 | * OMAP3 McBSP FIFO is word structured. | |
146 | * McBSP2 has 1024 + 256 = 1280 word long buffer, | |
147 | * McBSP1,3,4,5 has 128 word long buffer | |
148 | * This means that the size of the FIFO depends on the sample format. | |
149 | * For example on McBSP3: | |
150 | * 16bit samples: size is 128 * 2 = 256 bytes | |
151 | * 32bit samples: size is 128 * 4 = 512 bytes | |
152 | * It is simpler to place constraint for buffer and period based on | |
153 | * channels. | |
154 | * McBSP3 as example again (16 or 32 bit samples): | |
155 | * 1 channel (mono): size is 128 frames (128 words) | |
156 | * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) | |
157 | * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) | |
158 | */ | |
d4912977 | 159 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
6984992b | 160 | /* |
998a8a69 | 161 | * Rule for the buffer size. We should not allow |
ddc29b01 PU |
162 | * smaller buffer than the FIFO size to avoid underruns |
163 | */ | |
164 | snd_pcm_hw_rule_add(substream->runtime, 0, | |
165 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
166 | omap_mcbsp_hwrule_min_buffersize, | |
167 | mcbsp_data, | |
168 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1); | |
caebc0cb | 169 | |
998a8a69 PU |
170 | /* Make sure, that the period size is always even */ |
171 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
172 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
6984992b JN |
173 | } |
174 | ||
2e74796a JN |
175 | return err; |
176 | } | |
177 | ||
dee89c4d | 178 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 179 | struct snd_soc_dai *cpu_dai) |
2e74796a | 180 | { |
f0fba2ad | 181 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
182 | |
183 | if (!cpu_dai->active) { | |
184 | omap_mcbsp_free(mcbsp_data->bus_id); | |
185 | mcbsp_data->configured = 0; | |
186 | } | |
187 | } | |
188 | ||
dee89c4d | 189 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 190 | struct snd_soc_dai *cpu_dai) |
2e74796a | 191 | { |
f0fba2ad | 192 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
c12abc01 | 193 | int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
2e74796a JN |
194 | |
195 | switch (cmd) { | |
196 | case SNDRV_PCM_TRIGGER_START: | |
197 | case SNDRV_PCM_TRIGGER_RESUME: | |
198 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
c12abc01 JN |
199 | mcbsp_data->active++; |
200 | omap_mcbsp_start(mcbsp_data->bus_id, play, !play); | |
2e74796a JN |
201 | break; |
202 | ||
203 | case SNDRV_PCM_TRIGGER_STOP: | |
204 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
205 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
c12abc01 JN |
206 | omap_mcbsp_stop(mcbsp_data->bus_id, play, !play); |
207 | mcbsp_data->active--; | |
2e74796a JN |
208 | break; |
209 | default: | |
210 | err = -EINVAL; | |
211 | } | |
212 | ||
213 | return err; | |
214 | } | |
215 | ||
75581d24 PU |
216 | static snd_pcm_sframes_t omap_mcbsp_dai_delay( |
217 | struct snd_pcm_substream *substream, | |
218 | struct snd_soc_dai *dai) | |
219 | { | |
220 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad LG |
221 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
222 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); | |
75581d24 PU |
223 | u16 fifo_use; |
224 | snd_pcm_sframes_t delay; | |
225 | ||
226 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
227 | fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id); | |
228 | else | |
229 | fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id); | |
230 | ||
231 | /* | |
232 | * Divide the used locations with the channel count to get the | |
233 | * FIFO usage in samples (don't care about partial samples in the | |
234 | * buffer). | |
235 | */ | |
236 | delay = fifo_use / substream->runtime->channels; | |
237 | ||
238 | return delay; | |
239 | } | |
240 | ||
2e74796a | 241 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, |
dee89c4d | 242 | struct snd_pcm_hw_params *params, |
f0fba2ad | 243 | struct snd_soc_dai *cpu_dai) |
2e74796a | 244 | { |
f0fba2ad | 245 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a | 246 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
81ec027e PU |
247 | struct omap_pcm_dma_data *dma_data; |
248 | int dma, bus_id = mcbsp_data->bus_id; | |
caebc0cb | 249 | int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT; |
cf80e158 | 250 | int pkt_size = 0; |
2e74796a | 251 | unsigned long port; |
5f63ef99 | 252 | unsigned int format, div, framesize, master; |
2e74796a | 253 | |
81ec027e | 254 | dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream]; |
2686e07b KVA |
255 | |
256 | dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream); | |
257 | port = omap_mcbsp_dma_reg_params(bus_id, substream->stream); | |
258 | ||
d98508a1 SL |
259 | switch (params_format(params)) { |
260 | case SNDRV_PCM_FORMAT_S16_LE: | |
81ec027e | 261 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S16; |
cf80e158 | 262 | wlen = 16; |
d98508a1 SL |
263 | break; |
264 | case SNDRV_PCM_FORMAT_S32_LE: | |
81ec027e | 265 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S32; |
cf80e158 | 266 | wlen = 32; |
d98508a1 SL |
267 | break; |
268 | default: | |
269 | return -EINVAL; | |
270 | } | |
7243a4b1 | 271 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
15d01430 PU |
272 | dma_data->set_threshold = omap_mcbsp_set_threshold; |
273 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ | |
274 | if (omap_mcbsp_get_dma_op_mode(bus_id) == | |
cf80e158 PU |
275 | MCBSP_DMA_MODE_THRESHOLD) { |
276 | int period_words, max_thrsh; | |
277 | ||
278 | period_words = params_period_bytes(params) / (wlen / 8); | |
279 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
280 | max_thrsh = omap_mcbsp_get_max_tx_threshold( | |
281 | mcbsp_data->bus_id); | |
282 | else | |
283 | max_thrsh = omap_mcbsp_get_max_rx_threshold( | |
284 | mcbsp_data->bus_id); | |
285 | /* | |
286 | * If the period contains less or equal number of words, | |
287 | * we are using the original threshold mode setup: | |
288 | * McBSP threshold = sDMA frame size = period_size | |
289 | * Otherwise we switch to sDMA packet mode: | |
290 | * McBSP threshold = sDMA packet size | |
291 | * sDMA frame size = period size | |
292 | */ | |
293 | if (period_words > max_thrsh) { | |
294 | int divider = 0; | |
295 | ||
296 | /* | |
297 | * Look for the biggest threshold value, which | |
298 | * divides the period size evenly. | |
299 | */ | |
300 | divider = period_words / max_thrsh; | |
301 | if (period_words % max_thrsh) | |
302 | divider++; | |
303 | while (period_words % divider && | |
304 | divider < period_words) | |
305 | divider++; | |
306 | if (divider == period_words) | |
307 | return -EINVAL; | |
308 | ||
309 | pkt_size = period_words / divider; | |
310 | sync_mode = OMAP_DMA_SYNC_PACKET; | |
311 | } else { | |
312 | sync_mode = OMAP_DMA_SYNC_FRAME; | |
313 | } | |
314 | } | |
15d01430 PU |
315 | } |
316 | ||
317 | dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback"; | |
318 | dma_data->dma_req = dma; | |
319 | dma_data->port_addr = port; | |
320 | dma_data->sync_mode = sync_mode; | |
cf80e158 | 321 | dma_data->packet_size = pkt_size; |
fd23b7de | 322 | |
81ec027e | 323 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); |
2e74796a JN |
324 | |
325 | if (mcbsp_data->configured) { | |
326 | /* McBSP already configured by another stream */ | |
327 | return 0; | |
328 | } | |
329 | ||
4dd04172 JN |
330 | regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); |
331 | regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); | |
332 | regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); | |
333 | regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); | |
c29b206f PU |
334 | format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
335 | wpf = channels = params_channels(params); | |
299a151f PU |
336 | if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || |
337 | format == SND_SOC_DAIFMT_LEFT_J)) { | |
5f63ef99 GG |
338 | /* Use dual-phase frames */ |
339 | regs->rcr2 |= RPHASE; | |
340 | regs->xcr2 |= XPHASE; | |
341 | /* Set 1 word per (McBSP) frame for phase1 and phase2 */ | |
342 | wpf--; | |
343 | regs->rcr2 |= RFRLEN2(wpf - 1); | |
344 | regs->xcr2 |= XFRLEN2(wpf - 1); | |
2e74796a JN |
345 | } |
346 | ||
5f63ef99 GG |
347 | regs->rcr1 |= RFRLEN1(wpf - 1); |
348 | regs->xcr1 |= XFRLEN1(wpf - 1); | |
349 | ||
2e74796a JN |
350 | switch (params_format(params)) { |
351 | case SNDRV_PCM_FORMAT_S16_LE: | |
352 | /* Set word lengths */ | |
353 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); | |
354 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); | |
355 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); | |
356 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); | |
2e74796a | 357 | break; |
d98508a1 SL |
358 | case SNDRV_PCM_FORMAT_S32_LE: |
359 | /* Set word lengths */ | |
d98508a1 SL |
360 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); |
361 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); | |
362 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); | |
363 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); | |
364 | break; | |
2e74796a JN |
365 | default: |
366 | /* Unsupported PCM format */ | |
367 | return -EINVAL; | |
368 | } | |
369 | ||
5f63ef99 GG |
370 | /* In McBSP master modes, FRAME (i.e. sample rate) is generated |
371 | * by _counting_ BCLKs. Calculate frame size in BCLKs */ | |
372 | master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK; | |
373 | if (master == SND_SOC_DAIFMT_CBS_CFS) { | |
374 | div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1; | |
375 | framesize = (mcbsp_data->in_freq / div) / params_rate(params); | |
376 | ||
377 | if (framesize < wlen * channels) { | |
378 | printk(KERN_ERR "%s: not enough bandwidth for desired rate and " | |
379 | "channels\n", __func__); | |
380 | return -EINVAL; | |
381 | } | |
382 | } else | |
383 | framesize = wlen * channels; | |
384 | ||
ba9d0fd0 | 385 | /* Set FS period and length in terms of bit clock periods */ |
4dd04172 JN |
386 | regs->srgr2 &= ~FPER(0xfff); |
387 | regs->srgr1 &= ~FWID(0xff); | |
c29b206f | 388 | switch (format) { |
ba9d0fd0 | 389 | case SND_SOC_DAIFMT_I2S: |
299a151f | 390 | case SND_SOC_DAIFMT_LEFT_J: |
5f63ef99 GG |
391 | regs->srgr2 |= FPER(framesize - 1); |
392 | regs->srgr1 |= FWID((framesize >> 1) - 1); | |
ba9d0fd0 | 393 | break; |
3ba191ce | 394 | case SND_SOC_DAIFMT_DSP_A: |
bd25867a | 395 | case SND_SOC_DAIFMT_DSP_B: |
5f63ef99 | 396 | regs->srgr2 |= FPER(framesize - 1); |
36ce8582 | 397 | regs->srgr1 |= FWID(0); |
ba9d0fd0 JN |
398 | break; |
399 | } | |
400 | ||
2e74796a | 401 | omap_mcbsp_config(bus_id, &mcbsp_data->regs); |
3f024039 | 402 | mcbsp_data->wlen = wlen; |
2e74796a JN |
403 | mcbsp_data->configured = 1; |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | /* | |
409 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register | |
410 | * cache is initialized here | |
411 | */ | |
8687eb8b | 412 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
413 | unsigned int fmt) |
414 | { | |
f0fba2ad | 415 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a | 416 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
91a18ae8 | 417 | bool inv_fs = false; |
2e74796a JN |
418 | |
419 | if (mcbsp_data->configured) | |
420 | return 0; | |
421 | ||
ba9d0fd0 | 422 | mcbsp_data->fmt = fmt; |
2e74796a JN |
423 | memset(regs, 0, sizeof(*regs)); |
424 | /* Generic McBSP register settings */ | |
425 | regs->spcr2 |= XINTM(3) | FREE; | |
426 | regs->spcr1 |= RINTM(3); | |
c721bbda | 427 | /* RFIG and XFIG are not defined in 34xx */ |
d4686c65 | 428 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) { |
c721bbda EN |
429 | regs->rcr2 |= RFIG; |
430 | regs->xcr2 |= XFIG; | |
431 | } | |
d4686c65 | 432 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
32080af7 JN |
433 | regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; |
434 | regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; | |
ef390c0b | 435 | } |
2e74796a JN |
436 | |
437 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
438 | case SND_SOC_DAIFMT_I2S: | |
439 | /* 1-bit data delay */ | |
440 | regs->rcr2 |= RDATDLY(1); | |
441 | regs->xcr2 |= XDATDLY(1); | |
442 | break; | |
299a151f PU |
443 | case SND_SOC_DAIFMT_LEFT_J: |
444 | /* 0-bit data delay */ | |
445 | regs->rcr2 |= RDATDLY(0); | |
446 | regs->xcr2 |= XDATDLY(0); | |
447 | regs->spcr1 |= RJUST(2); | |
448 | /* Invert FS polarity configuration */ | |
91a18ae8 | 449 | inv_fs = true; |
299a151f | 450 | break; |
3ba191ce PU |
451 | case SND_SOC_DAIFMT_DSP_A: |
452 | /* 1-bit data delay */ | |
453 | regs->rcr2 |= RDATDLY(1); | |
454 | regs->xcr2 |= XDATDLY(1); | |
455 | /* Invert FS polarity configuration */ | |
91a18ae8 | 456 | inv_fs = true; |
3ba191ce | 457 | break; |
bd25867a | 458 | case SND_SOC_DAIFMT_DSP_B: |
3336c5b5 AK |
459 | /* 0-bit data delay */ |
460 | regs->rcr2 |= RDATDLY(0); | |
461 | regs->xcr2 |= XDATDLY(0); | |
36ce8582 | 462 | /* Invert FS polarity configuration */ |
91a18ae8 | 463 | inv_fs = true; |
3336c5b5 | 464 | break; |
2e74796a JN |
465 | default: |
466 | /* Unsupported data format */ | |
467 | return -EINVAL; | |
468 | } | |
469 | ||
470 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
471 | case SND_SOC_DAIFMT_CBS_CFS: | |
472 | /* McBSP master. Set FS and bit clocks as outputs */ | |
473 | regs->pcr0 |= FSXM | FSRM | | |
474 | CLKXM | CLKRM; | |
475 | /* Sample rate generator drives the FS */ | |
476 | regs->srgr2 |= FSGM; | |
477 | break; | |
478 | case SND_SOC_DAIFMT_CBM_CFM: | |
479 | /* McBSP slave */ | |
480 | break; | |
481 | default: | |
482 | /* Unsupported master/slave configuration */ | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | /* Set bit clock (CLKX/CLKR) and FS polarities */ | |
91a18ae8 | 487 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2e74796a JN |
488 | case SND_SOC_DAIFMT_NB_NF: |
489 | /* | |
490 | * Normal BCLK + FS. | |
491 | * FS active low. TX data driven on falling edge of bit clock | |
492 | * and RX data sampled on rising edge of bit clock. | |
493 | */ | |
494 | regs->pcr0 |= FSXP | FSRP | | |
495 | CLKXP | CLKRP; | |
496 | break; | |
497 | case SND_SOC_DAIFMT_NB_IF: | |
498 | regs->pcr0 |= CLKXP | CLKRP; | |
499 | break; | |
500 | case SND_SOC_DAIFMT_IB_NF: | |
501 | regs->pcr0 |= FSXP | FSRP; | |
502 | break; | |
503 | case SND_SOC_DAIFMT_IB_IF: | |
504 | break; | |
505 | default: | |
506 | return -EINVAL; | |
507 | } | |
91a18ae8 JN |
508 | if (inv_fs == true) |
509 | regs->pcr0 ^= FSXP | FSRP; | |
2e74796a JN |
510 | |
511 | return 0; | |
512 | } | |
513 | ||
8687eb8b | 514 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
515 | int div_id, int div) |
516 | { | |
f0fba2ad | 517 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
518 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
519 | ||
520 | if (div_id != OMAP_MCBSP_CLKGDV) | |
521 | return -ENODEV; | |
522 | ||
5f63ef99 | 523 | mcbsp_data->clk_div = div; |
4dd04172 | 524 | regs->srgr1 &= ~CLKGDV(0xff); |
2e74796a JN |
525 | regs->srgr1 |= CLKGDV(div - 1); |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
8687eb8b | 530 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
531 | int clk_id, unsigned int freq, |
532 | int dir) | |
533 | { | |
f0fba2ad | 534 | struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
535 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
536 | int err = 0; | |
537 | ||
141947e6 | 538 | if (mcbsp_data->active) { |
34c86985 JN |
539 | if (freq == mcbsp_data->in_freq) |
540 | return 0; | |
541 | else | |
542 | return -EBUSY; | |
141947e6 | 543 | } |
34c86985 | 544 | |
cf4c87ab PW |
545 | /* The McBSP signal muxing functions are only available on McBSP1 */ |
546 | if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR || | |
547 | clk_id == OMAP_MCBSP_CLKR_SRC_CLKX || | |
548 | clk_id == OMAP_MCBSP_FSR_SRC_FSR || | |
549 | clk_id == OMAP_MCBSP_FSR_SRC_FSX) | |
550 | if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0) | |
551 | return -EINVAL; | |
552 | ||
5f63ef99 | 553 | mcbsp_data->in_freq = freq; |
4dd04172 JN |
554 | regs->srgr2 &= ~CLKSM; |
555 | regs->pcr0 &= ~SCLKME; | |
5f63ef99 | 556 | |
2e74796a JN |
557 | switch (clk_id) { |
558 | case OMAP_MCBSP_SYSCLK_CLK: | |
559 | regs->srgr2 |= CLKSM; | |
560 | break; | |
561 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: | |
d1358657 PW |
562 | if (cpu_class_is_omap1()) { |
563 | err = -EINVAL; | |
564 | break; | |
565 | } | |
566 | err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, | |
567 | MCBSP_CLKS_PRCM_SRC); | |
568 | break; | |
2e74796a | 569 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: |
d1358657 PW |
570 | if (cpu_class_is_omap1()) { |
571 | err = 0; | |
572 | break; | |
573 | } | |
574 | err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, | |
575 | MCBSP_CLKS_PAD_SRC); | |
2e74796a JN |
576 | break; |
577 | ||
578 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: | |
579 | regs->srgr2 |= CLKSM; | |
580 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: | |
581 | regs->pcr0 |= SCLKME; | |
582 | break; | |
d2c0bdaa | 583 | |
cf4c87ab | 584 | |
d2c0bdaa | 585 | case OMAP_MCBSP_CLKR_SRC_CLKR: |
23353850 JK |
586 | if (cpu_class_is_omap1()) |
587 | break; | |
cf4c87ab PW |
588 | omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR); |
589 | break; | |
d2c0bdaa | 590 | case OMAP_MCBSP_CLKR_SRC_CLKX: |
23353850 JK |
591 | if (cpu_class_is_omap1()) |
592 | break; | |
cf4c87ab PW |
593 | omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX); |
594 | break; | |
d2c0bdaa | 595 | case OMAP_MCBSP_FSR_SRC_FSR: |
23353850 JK |
596 | if (cpu_class_is_omap1()) |
597 | break; | |
cf4c87ab PW |
598 | omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR); |
599 | break; | |
d2c0bdaa | 600 | case OMAP_MCBSP_FSR_SRC_FSX: |
23353850 JK |
601 | if (cpu_class_is_omap1()) |
602 | break; | |
cf4c87ab | 603 | omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX); |
d2c0bdaa | 604 | break; |
2e74796a JN |
605 | default: |
606 | err = -ENODEV; | |
607 | } | |
608 | ||
609 | return err; | |
610 | } | |
611 | ||
85e7652d | 612 | static const struct snd_soc_dai_ops mcbsp_dai_ops = { |
6335d055 EM |
613 | .startup = omap_mcbsp_dai_startup, |
614 | .shutdown = omap_mcbsp_dai_shutdown, | |
615 | .trigger = omap_mcbsp_dai_trigger, | |
75581d24 | 616 | .delay = omap_mcbsp_dai_delay, |
6335d055 EM |
617 | .hw_params = omap_mcbsp_dai_hw_params, |
618 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, | |
619 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, | |
620 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, | |
621 | }; | |
622 | ||
f0fba2ad LG |
623 | static int mcbsp_dai_probe(struct snd_soc_dai *dai) |
624 | { | |
625 | mcbsp_data[dai->id].bus_id = dai->id; | |
626 | snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id); | |
627 | return 0; | |
8def464d JN |
628 | } |
629 | ||
6179b772 | 630 | static struct snd_soc_dai_driver omap_mcbsp_dai = { |
f0fba2ad LG |
631 | .probe = mcbsp_dai_probe, |
632 | .playback = { | |
633 | .channels_min = 1, | |
634 | .channels_max = 16, | |
635 | .rates = OMAP_MCBSP_RATES, | |
636 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
637 | }, | |
638 | .capture = { | |
639 | .channels_min = 1, | |
640 | .channels_max = 16, | |
641 | .rates = OMAP_MCBSP_RATES, | |
642 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
643 | }, | |
644 | .ops = &mcbsp_dai_ops, | |
2e74796a | 645 | }; |
8def464d | 646 | |
3484457f | 647 | static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, |
83905c13 IK |
648 | struct snd_ctl_elem_info *uinfo) |
649 | { | |
650 | struct soc_mixer_control *mc = | |
651 | (struct soc_mixer_control *)kcontrol->private_value; | |
652 | int max = mc->max; | |
653 | int min = mc->min; | |
654 | ||
655 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
656 | uinfo->count = 1; | |
657 | uinfo->value.integer.min = min; | |
658 | uinfo->value.integer.max = max; | |
659 | return 0; | |
660 | } | |
661 | ||
662 | #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \ | |
663 | static int \ | |
664 | omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ | |
665 | struct snd_ctl_elem_value *uc) \ | |
666 | { \ | |
667 | struct soc_mixer_control *mc = \ | |
668 | (struct soc_mixer_control *)kc->private_value; \ | |
669 | int max = mc->max; \ | |
670 | int min = mc->min; \ | |
671 | int val = uc->value.integer.value[0]; \ | |
672 | \ | |
673 | if (val < min || val > max) \ | |
674 | return -EINVAL; \ | |
675 | \ | |
676 | /* OMAP McBSP implementation uses index values 0..4 */ \ | |
677 | return omap_st_set_chgain((id)-1, channel, val); \ | |
678 | } | |
679 | ||
680 | #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \ | |
681 | static int \ | |
682 | omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ | |
683 | struct snd_ctl_elem_value *uc) \ | |
684 | { \ | |
685 | s16 chgain; \ | |
686 | \ | |
687 | if (omap_st_get_chgain((id)-1, channel, &chgain)) \ | |
688 | return -EAGAIN; \ | |
689 | \ | |
690 | uc->value.integer.value[0] = chgain; \ | |
691 | return 0; \ | |
692 | } | |
693 | ||
694 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0) | |
695 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1) | |
696 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0) | |
697 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1) | |
698 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0) | |
699 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1) | |
700 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0) | |
701 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1) | |
702 | ||
703 | static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, | |
704 | struct snd_ctl_elem_value *ucontrol) | |
705 | { | |
706 | struct soc_mixer_control *mc = | |
707 | (struct soc_mixer_control *)kcontrol->private_value; | |
708 | u8 value = ucontrol->value.integer.value[0]; | |
709 | ||
710 | if (value == omap_st_is_enabled(mc->reg)) | |
711 | return 0; | |
712 | ||
713 | if (value) | |
714 | omap_st_enable(mc->reg); | |
715 | else | |
716 | omap_st_disable(mc->reg); | |
717 | ||
718 | return 1; | |
719 | } | |
720 | ||
721 | static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, | |
722 | struct snd_ctl_elem_value *ucontrol) | |
723 | { | |
724 | struct soc_mixer_control *mc = | |
725 | (struct soc_mixer_control *)kcontrol->private_value; | |
726 | ||
727 | ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg); | |
728 | return 0; | |
729 | } | |
730 | ||
731 | static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = { | |
732 | SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0, | |
733 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
734 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume", | |
735 | -32768, 32767, | |
736 | omap_mcbsp2_get_st_ch0_volume, | |
737 | omap_mcbsp2_set_st_ch0_volume), | |
738 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume", | |
739 | -32768, 32767, | |
740 | omap_mcbsp2_get_st_ch1_volume, | |
741 | omap_mcbsp2_set_st_ch1_volume), | |
742 | }; | |
743 | ||
744 | static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = { | |
745 | SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0, | |
746 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
747 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume", | |
748 | -32768, 32767, | |
749 | omap_mcbsp3_get_st_ch0_volume, | |
750 | omap_mcbsp3_set_st_ch0_volume), | |
751 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume", | |
752 | -32768, 32767, | |
753 | omap_mcbsp3_get_st_ch1_volume, | |
754 | omap_mcbsp3_set_st_ch1_volume), | |
755 | }; | |
756 | ||
022658be | 757 | int omap_mcbsp_st_add_controls(struct snd_soc_dai *dai) |
83905c13 IK |
758 | { |
759 | if (!cpu_is_omap34xx()) | |
760 | return -ENODEV; | |
761 | ||
022658be | 762 | switch (dai->id) { |
83905c13 | 763 | case 1: /* McBSP 2 */ |
022658be | 764 | return snd_soc_add_dai_controls(dai, omap_mcbsp2_st_controls, |
83905c13 IK |
765 | ARRAY_SIZE(omap_mcbsp2_st_controls)); |
766 | case 2: /* McBSP 3 */ | |
022658be | 767 | return snd_soc_add_dai_controls(dai, omap_mcbsp3_st_controls, |
83905c13 IK |
768 | ARRAY_SIZE(omap_mcbsp3_st_controls)); |
769 | default: | |
770 | break; | |
771 | } | |
772 | ||
773 | return -EINVAL; | |
774 | } | |
775 | EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); | |
776 | ||
f0fba2ad LG |
777 | static __devinit int asoc_mcbsp_probe(struct platform_device *pdev) |
778 | { | |
779 | return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai); | |
780 | } | |
781 | ||
782 | static int __devexit asoc_mcbsp_remove(struct platform_device *pdev) | |
783 | { | |
784 | snd_soc_unregister_dai(&pdev->dev); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static struct platform_driver asoc_mcbsp_driver = { | |
789 | .driver = { | |
790 | .name = "omap-mcbsp-dai", | |
791 | .owner = THIS_MODULE, | |
792 | }, | |
793 | ||
794 | .probe = asoc_mcbsp_probe, | |
795 | .remove = __devexit_p(asoc_mcbsp_remove), | |
796 | }; | |
797 | ||
beda5bf5 | 798 | module_platform_driver(asoc_mcbsp_driver); |
3f4b783c | 799 | |
7ec41ee5 | 800 | MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); |
2e74796a JN |
801 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); |
802 | MODULE_LICENSE("GPL"); |