[mirror_ubuntu-bionic-kernel.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include <sound/omap-pcm.h>

#include "omap-mcpdm.h"

struct mcpdm_link_config {
	u32 link_mask; /* channel mask for the direction */
	u32 threshold; /* FIFO threshold */
};

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* Playback/Capture configuration */
	struct mcpdm_link_config config[2];

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;

	/* McPDM needs to be restarted due to runtime reconfiguration */
	bool restart;

	/* pm state for suspend/resume handling */
	int pm_active_count;

	struct snd_dmaengine_dai_dma_data dma_data[2];
};

/*
 * Stream DMA parameters
 */

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	writel_relaxed(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return readl_relaxed(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= link_mask;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(link_mask);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);

	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
			 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
			 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active)
		omap_mcpdm_open_streams(mcpdm);

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
			mcpdm->config[0].link_mask = 0;
			mcpdm->config[1].link_mask = 0;
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 threshold;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	threshold = mcpdm->config[stream].threshold;
	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		link_mask <<= 3;

		/* If capture is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = 0x3;

		dma_data->maxburst =
				(MCPDM_DN_THRES_MAX - threshold) * channels;
	} else {
		/* If playback is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = (0x3 << 3);

		dma_data->maxburst = threshold * channels;
	}

	/* Check if we need to restart McPDM with this stream */
	if (mcpdm->config[stream].link_mask &&
	    mcpdm->config[stream].link_mask != link_mask)
		mcpdm->restart = true;

	mcpdm->config[stream].link_mask = link_mask;

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	} else if (mcpdm->restart) {
		omap_mcpdm_stop(mcpdm);
		omap_mcpdm_start(mcpdm);
		mcpdm->restart = false;
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
			  (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
							MCPDM_UP_THRES_MAX - 3;

	snd_soc_dai_init_dma_data(dai,
				  &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
				  &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);

	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int omap_mcpdm_suspend(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (dai->active) {
		omap_mcpdm_stop(mcpdm);
		omap_mcpdm_close_streams(mcpdm);
	}

	mcpdm->pm_active_count = 0;
	while (pm_runtime_active(mcpdm->dev)) {
		pm_runtime_put_sync(mcpdm->dev);
		mcpdm->pm_active_count++;
	}

	return 0;
}

static int omap_mcpdm_resume(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (mcpdm->pm_active_count) {
		while (mcpdm->pm_active_count--)
			pm_runtime_get_sync(mcpdm->dev);

		if (dai->active) {
			omap_mcpdm_open_streams(mcpdm);
			omap_mcpdm_start(mcpdm);
		}
	}


	return 0;
}
#else
#define omap_mcpdm_suspend NULL
#define omap_mcpdm_resume NULL
#endif

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.suspend = omap_mcpdm_suspend,
	.resume = omap_mcpdm_resume,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

static const struct snd_soc_component_driver omap_mcpdm_component = {
	.name		= "omap-mcpdm",
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;
	int ret;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;

	mcpdm->dma_data[0].filter_data = "dn_link";
	mcpdm->dma_data[1].filter_data = "up_link";

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mcpdm->io_base))
		return PTR_ERR(mcpdm->io_base);

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	ret =  devm_snd_soc_register_component(&pdev->dev,
					       &omap_mcpdm_component,
					       &omap_mcpdm_dai, 1);
	if (ret)
		return ret;

	return omap_pcm_platform_register(&pdev->dev);
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8	41	#include <sound/soc.h>
09ae3aaf	42	#include <sound/dmaengine_pcm.h>
87c19364	43	#include <sound/omap-pcm.h>
db72c2f8	44
f5f9d7bf	45	#include "omap-mcpdm.h"
db72c2f8	46
62376631 PU	47	struct mcpdm_link_config {
	48	u32 link_mask; /* channel mask for the direction */
	49	u32 threshold; /* FIFO threshold */
	50	};
dbc04161	51
f5f9d7bf MLC	52	struct omap_mcpdm {
	53	struct device *dev;
	54	unsigned long phys_base;
	55	void __iomem *io_base;
	56	int irq;
db72c2f8	57
f5f9d7bf MLC	58	struct mutex mutex;
f5f9d7bf MLC	59
62376631 PU	60	/* Playback/Capture configuration */
62376631 PU	61	struct mcpdm_link_config config[2];
89b0d550 PU	62
	63	/* McPDM dn offsets for rx1, and 2 channels */
	64	u32 dn_rx_offset;
81054b22 PU	65
	66	/* McPDM needs to be restarted due to runtime reconfiguration */
	67	bool restart;
09ae3aaf	68
4a5c8374 PU	69	/* pm state for suspend/resume handling */
	70	int pm_active_count;
	71
09ae3aaf	72	struct snd_dmaengine_dai_dma_data dma_data[2];
db72c2f8 MLC	73	};
	74
	75	/*
	76	* Stream DMA parameters
	77	*/
db72c2f8	78
f5f9d7bf	79	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	80	{
1b488a48	81	writel_relaxed(val, mcpdm->io_base + reg);
f5f9d7bf	82	}
db72c2f8	83
f5f9d7bf MLC	84	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
f5f9d7bf MLC	85	{
1b488a48	86	return readl_relaxed(mcpdm->io_base + reg);
f5f9d7bf	87	}
db72c2f8	88
f5f9d7bf MLC	89	#ifdef DEBUG
	90	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	91	{
	92	dev_dbg(mcpdm->dev, "***********************\n");
	93	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	94	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	95	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	96	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	97	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	98	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	99	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	100	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	101	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	102	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	103	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	104	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	105	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	106	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	107	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	108	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	109	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	110	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	111	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	112	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	113	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	114	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	115	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	116	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	117	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	118	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	119	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	120	}
f5f9d7bf MLC	121	#else
	122	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	123	#endif
db72c2f8	124
f5f9d7bf MLC	125	/*
	126	* Enables the transfer through the PDM interface to/from the Phoenix
	127	* codec by enabling the corresponding UP or DN channels.
	128	*/
	129	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	130	{
	131	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
62376631	132	u32 link_mask = mcpdm->config[0].link_mask \| mcpdm->config[1].link_mask;
f5f9d7bf MLC	133
	134	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	135	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	136
62376631	137	ctrl \|= link_mask;
f5f9d7bf MLC	138	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	139
	140	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	141	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	142	}
	143
	144	/*
	145	* Disables the transfer through the PDM interface to/from the Phoenix
	146	* codec by disabling the corresponding UP or DN channels.
	147	*/
	148	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	149	{
	150	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
81054b22	151	u32 link_mask = MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK;
f5f9d7bf MLC	152
	153	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	154	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	155
62376631	156	ctrl &= ~(link_mask);
f5f9d7bf MLC	157	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	158
	159	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	160	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	161
	162	}
	163
	164	/*
	165	* Is the physical McPDM interface active.
	166	*/
	167	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	168	{
	169	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	170	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	171	}
	172
	173	/*
	174	* Configures McPDM uplink, and downlink for audio.
	175	* This function should be called before omap_mcpdm_start.
	176	*/
	177	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	178	{
0efecc08 PU	179	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	180
	181	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl \| MCPDM_WD_EN);
	182
f5f9d7bf MLC	183	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	184	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	185	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	186
89b0d550 PU	187	/* Enable DN RX1/2 offset cancellation feature, if configured */
	188	if (mcpdm->dn_rx_offset) {
	189	u32 dn_offset = mcpdm->dn_rx_offset;
	190
	191	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	192	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	193	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	194	}
	195
62376631 PU	196	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
	197	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	198	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
	199	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
f5f9d7bf MLC	200
	201	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	202	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	203	}
	204
	205	/*
	206	* Cleans McPDM uplink, and downlink configuration.
	207	* This function should be called when the stream is closed.
	208	*/
	209	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	210	{
f5f9d7bf MLC	211	/* Disable irq request generation for downlink */
	212	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	213	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	214
	215	/* Disable DMA request generation for downlink */
	216	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	217
	218	/* Disable irq request generation for uplink */
	219	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	220	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	221
	222	/* Disable DMA request generation for uplink */
	223	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	224
	225	/* Disable RX1/2 offset cancellation */
	226	if (mcpdm->dn_rx_offset)
	227	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	228	}
	229
	230	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	231	{
	232	struct omap_mcpdm *mcpdm = dev_id;
	233	int irq_status;
	234
	235	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	236
	237	/* Acknowledge irq event */
	238	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	239
	240	if (irq_status & MCPDM_DN_IRQ_FULL)
	241	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	242
	243	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	244	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	245
	246	if (irq_status & MCPDM_DN_IRQ)
	247	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	248
	249	if (irq_status & MCPDM_UP_IRQ_FULL)
	250	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	251
	252	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	253	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	254
	255	if (irq_status & MCPDM_UP_IRQ)
	256	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	257
	258	return IRQ_HANDLED;
db72c2f8 MLC	259	}
db72c2f8 MLC	260
f5f9d7bf	261	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	262	struct snd_soc_dai *dai)
db72c2f8 MLC	263	{
f5f9d7bf	264	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	265
f5f9d7bf MLC	266	mutex_lock(&mcpdm->mutex);
f5f9d7bf MLC	267
0efecc08	268	if (!dai->active)
f5f9d7bf	269	omap_mcpdm_open_streams(mcpdm);
0efecc08	270
f5f9d7bf MLC	271	mutex_unlock(&mcpdm->mutex);
	272
	273	return 0;
	274	}
	275
	276	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	277	struct snd_soc_dai *dai)
	278	{
	279	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	280
	281	mutex_lock(&mcpdm->mutex);
	282
	283	if (!dai->active) {
	284	if (omap_mcpdm_active(mcpdm)) {
	285	omap_mcpdm_stop(mcpdm);
	286	omap_mcpdm_close_streams(mcpdm);
81054b22 PU	287	mcpdm->config[0].link_mask = 0;
81054b22 PU	288	mcpdm->config[1].link_mask = 0;
f5f9d7bf	289	}
f5f9d7bf MLC	290	}
	291
	292	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	293	}
	294
	295	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	296	struct snd_pcm_hw_params *params,
	297	struct snd_soc_dai *dai)
	298	{
f5f9d7bf	299	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	300	int stream = substream->stream;
09ae3aaf	301	struct snd_dmaengine_dai_dma_data *dma_data;
62376631	302	u32 threshold;
f5f9d7bf MLC	303	int channels;
f5f9d7bf MLC	304	int link_mask = 0;
db72c2f8	305
db72c2f8 MLC	306	channels = params_channels(params);
db72c2f8 MLC	307	switch (channels) {
3b5b516f PU	308	case 5:
	309	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	310	/* up to 3 channels for capture */
	311	return -EINVAL;
	312	link_mask \|= 1 << 4;
db72c2f8 MLC	313	case 4:
db72c2f8 MLC	314	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	315	/* up to 3 channels for capture */
db72c2f8 MLC	316	return -EINVAL;
	317	link_mask \|= 1 << 3;
	318	case 3:
db72c2f8 MLC	319	link_mask \|= 1 << 2;
	320	case 2:
	321	link_mask \|= 1 << 1;
	322	case 1:
	323	link_mask \|= 1 << 0;
	324	break;
	325	default:
	326	/* unsupported number of channels */
	327	return -EINVAL;
	328	}
	329
bcd6da7b	330	dma_data = snd_soc_dai_get_dma_data(dai, substream);
b199adfd	331
62376631	332	threshold = mcpdm->config[stream].threshold;
f5f9d7bf	333	/* Configure McPDM channels, and DMA packet size */
db72c2f8	334	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
62376631	335	link_mask <<= 3;
81054b22 PU	336
	337	/* If capture is not running assume a stereo stream to come */
	338	if (!mcpdm->config[!stream].link_mask)
	339	mcpdm->config[!stream].link_mask = 0x3;
	340
09ae3aaf	341	dma_data->maxburst =
62376631	342	(MCPDM_DN_THRES_MAX - threshold) * channels;
db72c2f8	343	} else {
81054b22 PU	344	/* If playback is not running assume a stereo stream to come */
	345	if (!mcpdm->config[!stream].link_mask)
	346	mcpdm->config[!stream].link_mask = (0x3 << 3);
	347
09ae3aaf	348	dma_data->maxburst = threshold * channels;
db72c2f8 MLC	349	}
db72c2f8 MLC	350
81054b22 PU	351	/* Check if we need to restart McPDM with this stream */
	352	if (mcpdm->config[stream].link_mask &&
	353	mcpdm->config[stream].link_mask != link_mask)
	354	mcpdm->restart = true;
	355
62376631	356	mcpdm->config[stream].link_mask = link_mask;
db72c2f8	357
f5f9d7bf	358	return 0;
db72c2f8 MLC	359	}
db72c2f8 MLC	360
f5f9d7bf	361	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	362	struct snd_soc_dai *dai)
db72c2f8 MLC	363	{
f5f9d7bf	364	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	365
f5f9d7bf MLC	366	if (!omap_mcpdm_active(mcpdm)) {
	367	omap_mcpdm_start(mcpdm);
	368	omap_mcpdm_reg_dump(mcpdm);
81054b22 PU	369	} else if (mcpdm->restart) {
	370	omap_mcpdm_stop(mcpdm);
	371	omap_mcpdm_start(mcpdm);
	372	mcpdm->restart = false;
	373	omap_mcpdm_reg_dump(mcpdm);
f5f9d7bf	374	}
db72c2f8	375
f5f9d7bf	376	return 0;
db72c2f8 MLC	377	}
db72c2f8 MLC	378
85e7652d	379	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	380	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	381	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	382	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	383	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	384	};
db72c2f8 MLC	385
f5f9d7bf MLC	386	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	387	{
	388	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	389	int ret;
	390
	391	pm_runtime_enable(mcpdm->dev);
	392
	393	/* Disable lines while request is ongoing */
	394	pm_runtime_get_sync(mcpdm->dev);
	395	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	396
a8719670 PU	397	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
a8719670 PU	398	(void *)mcpdm);
db72c2f8	399
f5f9d7bf MLC	400	pm_runtime_put_sync(mcpdm->dev);
	401
	402	if (ret) {
	403	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	404	pm_runtime_disable(mcpdm->dev);
	405	}
	406
	407	/* Configure McPDM threshold values */
62376631 PU	408	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	409	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
	410	MCPDM_UP_THRES_MAX - 3;
f6563b31 PU	411
	412	snd_soc_dai_init_dma_data(dai,
	413	&mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
	414	&mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
	415
f5f9d7bf MLC	416	return ret;
	417	}
	418
	419	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	420	{
f5f9d7bf MLC	421	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
f5f9d7bf MLC	422
a8719670	423	free_irq(mcpdm->irq, (void *)mcpdm);
f5f9d7bf MLC	424	pm_runtime_disable(mcpdm->dev);
f5f9d7bf MLC	425
f0fba2ad LG	426	return 0;
	427	}
	428
4a5c8374 PU	429	#ifdef CONFIG_PM_SLEEP
	430	static int omap_mcpdm_suspend(struct snd_soc_dai *dai)
	431	{
	432	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	433
	434	if (dai->active) {
	435	omap_mcpdm_stop(mcpdm);
	436	omap_mcpdm_close_streams(mcpdm);
	437	}
	438
	439	mcpdm->pm_active_count = 0;
	440	while (pm_runtime_active(mcpdm->dev)) {
	441	pm_runtime_put_sync(mcpdm->dev);
	442	mcpdm->pm_active_count++;
	443	}
	444
	445	return 0;
	446	}
	447
	448	static int omap_mcpdm_resume(struct snd_soc_dai *dai)
	449	{
	450	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	451
	452	if (mcpdm->pm_active_count) {
	453	while (mcpdm->pm_active_count--)
	454	pm_runtime_get_sync(mcpdm->dev);
	455
	456	if (dai->active) {
	457	omap_mcpdm_open_streams(mcpdm);
	458	omap_mcpdm_start(mcpdm);
	459	}
	460	}
	461
	462
	463	return 0;
	464	}
	465	#else
	466	#define omap_mcpdm_suspend NULL
	467	#define omap_mcpdm_resume NULL
	468	#endif
	469
f5f9d7bf MLC	470	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	471	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	472
f0fba2ad	473	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	474	.probe = omap_mcpdm_probe,
f5f9d7bf MLC	475	.remove = omap_mcpdm_remove,
4a5c8374 PU	476	.suspend = omap_mcpdm_suspend,
4a5c8374 PU	477	.resume = omap_mcpdm_resume,
f5f9d7bf MLC	478	.probe_order = SND_SOC_COMP_ORDER_LATE,
f5f9d7bf MLC	479	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	480	.playback = {
db72c2f8 MLC	481	.channels_min = 1,
3b5b516f	482	.channels_max = 5,
db72c2f8 MLC	483	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	484	.formats = OMAP_MCPDM_FORMATS,
b4badd49	485	.sig_bits = 24,
db72c2f8 MLC	486	},
	487	.capture = {
	488	.channels_min = 1,
3b5b516f	489	.channels_max = 3,
db72c2f8 MLC	490	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	491	.formats = OMAP_MCPDM_FORMATS,
b4badd49	492	.sig_bits = 24,
db72c2f8 MLC	493	},
db72c2f8 MLC	494	.ops = &omap_mcpdm_dai_ops,
db72c2f8	495	};
f0fba2ad	496
58709a32 KM	497	static const struct snd_soc_component_driver omap_mcpdm_component = {
	498	.name = "omap-mcpdm",
	499	};
	500
89b0d550 PU	501	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	502	u8 rx1, u8 rx2)
	503	{
	504	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	505
	506	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	507	}
	508	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	509
7ff60006	510	static int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad	511	{
f5f9d7bf MLC	512	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	513	struct resource *res;
335b0651	514	int ret;
f5f9d7bf	515
d77ae332	516	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	517	if (!mcpdm)
	518	return -ENOMEM;
	519
	520	platform_set_drvdata(pdev, mcpdm);
	521
	522	mutex_init(&mcpdm->mutex);
	523
5a40c57a PU	524	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	525	if (res == NULL)
	526	return -ENOMEM;
	527
09ae3aaf LPC	528	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
09ae3aaf LPC	529	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
5a40c57a	530
a8035f07 PU	531	mcpdm->dma_data[0].filter_data = "dn_link";
a8035f07 PU	532	mcpdm->dma_data[1].filter_data = "up_link";
5a40c57a PU	533
5a40c57a PU	534	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
77c641d3 SMP	535	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	536	if (IS_ERR(mcpdm->io_base))
	537	return PTR_ERR(mcpdm->io_base);
f5f9d7bf MLC	538
f5f9d7bf MLC	539	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	540	if (mcpdm->irq < 0)
d77ae332 PU	541	return mcpdm->irq;
f5f9d7bf MLC	542
f5f9d7bf MLC	543	mcpdm->dev = &pdev->dev;
f0fba2ad	544
335b0651	545	ret = devm_snd_soc_register_component(&pdev->dev,
6c3cc302 SK	546	&omap_mcpdm_component,
6c3cc302 SK	547	&omap_mcpdm_dai, 1);
335b0651 PU	548	if (ret)
	549	return ret;
	550
	551	return omap_pcm_platform_register(&pdev->dev);
f0fba2ad LG	552	}
f0fba2ad LG	553
7cb8a1b5 PU	554	static const struct of_device_id omap_mcpdm_of_match[] = {
	555	{ .compatible = "ti,omap4-mcpdm", },
	556	{ }
	557	};
	558	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	559
f0fba2ad LG	560	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	561	.driver = {
f5f9d7bf	562	.name = "omap-mcpdm",
7cb8a1b5	563	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	564	},
f0fba2ad LG	565
f5f9d7bf	566	.probe = asoc_mcpdm_probe,
f0fba2ad	567	};
db72c2f8	568
beda5bf5	569	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	570
d66a547c	571	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	572	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	573	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	574	MODULE_LICENSE("GPL");