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Merge branch 'topic/asoc' into for-linus
[mirror_ubuntu-bionic-kernel.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
49 struct ssp_state state;
50#endif
51};
52
1b340bd7
MB		 53static void dump_registers(struct ssp_device *ssp)
54{
55 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
57 ssp_read_reg(ssp, SSTO));
58
59 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
61 ssp_read_reg(ssp, SSACD));
62}
63
2d7e71fa
EM		 64struct pxa2xx_pcm_dma_data {
65 struct pxa2xx_pcm_dma_params params;
66 char name[20];
1b340bd7
MB		 67};
68
2d7e71fa 69static struct pxa2xx_pcm_dma_params *
8eb9feab 70ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 71{
72 struct pxa2xx_pcm_dma_data *dma;
73
74 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
75 if (dma == NULL)
76 return NULL;
77
78 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 79 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 80
81 dma->params.name = dma->name;
82 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
83 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
84 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 85 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 86 dma->params.dev_addr = ssp->phys_base + SSDR;
87
88 return &dma->params;
89}
90
dee89c4d
MB		 91static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *dai)
1b340bd7
MB		 93{
94 struct snd_soc_pcm_runtime *rtd = substream->private_data;
95 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
96 struct ssp_priv *priv = cpu_dai->private_data;
97 int ret = 0;
98
99 if (!cpu_dai->active) {
0664678a
PZ		 100 priv->dev.port = cpu_dai->id + 1;
101 priv->dev.irq = NO_IRQ;
102 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 103 ssp_disable(&priv->dev);
104 }
2d7e71fa
EM		 105
106 if (cpu_dai->dma_data) {
107 kfree(cpu_dai->dma_data);
108 cpu_dai->dma_data = NULL;
109 }
1b340bd7
MB		 110 return ret;
111}
112
dee89c4d
MB		 113static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
114 struct snd_soc_dai *dai)
1b340bd7
MB		 115{
116 struct snd_soc_pcm_runtime *rtd = substream->private_data;
117 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
118 struct ssp_priv *priv = cpu_dai->private_data;
119
120 if (!cpu_dai->active) {
121 ssp_disable(&priv->dev);
0664678a 122 clk_disable(priv->dev.ssp->clk);
1b340bd7 123 }
2d7e71fa
EM		 124
125 if (cpu_dai->dma_data) {
126 kfree(cpu_dai->dma_data);
127 cpu_dai->dma_data = NULL;
128 }
1b340bd7
MB		 129}
130
131#ifdef CONFIG_PM
132
dc7d7b83 133static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 134{
135 struct ssp_priv *priv = cpu_dai->private_data;
136
137 if (!cpu_dai->active)
026384d6 138 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 139
140 ssp_save_state(&priv->dev, &priv->state);
141 clk_disable(priv->dev.ssp->clk);
026384d6 142
1b340bd7
MB		 143 return 0;
144}
145
dc7d7b83 146static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 147{
148 struct ssp_priv *priv = cpu_dai->private_data;
149
1b340bd7
MB		 150 clk_enable(priv->dev.ssp->clk);
151 ssp_restore_state(&priv->dev, &priv->state);
026384d6
DM		 152
153 if (cpu_dai->active)
154 ssp_enable(&priv->dev);
155 else
156 clk_disable(priv->dev.ssp->clk);
1b340bd7
MB		 157
158 return 0;
159}
160
161#else
162#define pxa_ssp_suspend NULL
163#define pxa_ssp_resume NULL
164#endif
165
166/**
167 * ssp_set_clkdiv - set SSP clock divider
168 * @div: serial clock rate divider
169 */
1a297286 170static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 171{
1a297286
PZ		 172 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
173
174 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
175 sscr0 &= ~0x0000ff00;
176 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
177 } else {
178 sscr0 &= ~0x000fff00;
179 sscr0 |= (div - 1) << 8; /* 1..4096 */
180 }
181 ssp_write_reg(ssp, SSCR0, sscr0);
182}
183
184/**
185 * ssp_get_clkdiv - get SSP clock divider
186 */
187static u32 ssp_get_scr(struct ssp_device *ssp)
188{
189 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
190 u32 div;
1b340bd7 191
1a297286
PZ		 192 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
193 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
194 else
195 div = ((sscr0 >> 8) & 0xfff) + 1;
196 return div;
1b340bd7
MB		 197}
198
199/*
200 * Set the SSP ports SYSCLK.
201 */
202static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
203 int clk_id, unsigned int freq, int dir)
204{
205 struct ssp_priv *priv = cpu_dai->private_data;
206 struct ssp_device *ssp = priv->dev.ssp;
207 int val;
208
209 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 210 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 211
212 dev_dbg(&ssp->pdev->dev,
449bd54d 213 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 214 cpu_dai->id, clk_id, freq);
215
216 switch (clk_id) {
217 case PXA_SSP_CLK_NET_PLL:
218 sscr0 |= SSCR0_MOD;
219 break;
220 case PXA_SSP_CLK_PLL:
221 /* Internal PLL is fixed */
222 if (cpu_is_pxa25x())
223 priv->sysclk = 1843200;
224 else
225 priv->sysclk = 13000000;
226 break;
227 case PXA_SSP_CLK_EXT:
228 priv->sysclk = freq;
229 sscr0 |= SSCR0_ECS;
230 break;
231 case PXA_SSP_CLK_NET:
232 priv->sysclk = freq;
233 sscr0 |= SSCR0_NCS | SSCR0_MOD;
234 break;
235 case PXA_SSP_CLK_AUDIO:
236 priv->sysclk = 0;
1a297286 237 ssp_set_scr(ssp, 1);
20a41eac 238 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 239 break;
240 default:
241 return -ENODEV;
242 }
243
244 /* The SSP clock must be disabled when changing SSP clock mode
245 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
246 if (!cpu_is_pxa3xx())
247 clk_disable(priv->dev.ssp->clk);
248 val = ssp_read_reg(ssp, SSCR0) | sscr0;
249 ssp_write_reg(ssp, SSCR0, val);
250 if (!cpu_is_pxa3xx())
251 clk_enable(priv->dev.ssp->clk);
252
253 return 0;
254}
255
256/*
257 * Set the SSP clock dividers.
258 */
259static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
260 int div_id, int div)
261{
262 struct ssp_priv *priv = cpu_dai->private_data;
263 struct ssp_device *ssp = priv->dev.ssp;
264 int val;
265
266 switch (div_id) {
267 case PXA_SSP_AUDIO_DIV_ACDS:
268 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
269 ssp_write_reg(ssp, SSACD, val);
270 break;
271 case PXA_SSP_AUDIO_DIV_SCDB:
272 val = ssp_read_reg(ssp, SSACD);
273 val &= ~SSACD_SCDB;
274#if defined(CONFIG_PXA3xx)
275 if (cpu_is_pxa3xx())
276 val &= ~SSACD_SCDX8;
277#endif
278 switch (div) {
279 case PXA_SSP_CLK_SCDB_1:
280 val |= SSACD_SCDB;
281 break;
282 case PXA_SSP_CLK_SCDB_4:
283 break;
284#if defined(CONFIG_PXA3xx)
285 case PXA_SSP_CLK_SCDB_8:
286 if (cpu_is_pxa3xx())
287 val |= SSACD_SCDX8;
288 else
289 return -EINVAL;
290 break;
291#endif
292 default:
293 return -EINVAL;
294 }
295 ssp_write_reg(ssp, SSACD, val);
296 break;
297 case PXA_SSP_DIV_SCR:
1a297286 298 ssp_set_scr(ssp, div);
1b340bd7
MB		 299 break;
300 default:
301 return -ENODEV;
302 }
303
304 return 0;
305}
306
307/*
308 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
309 */
85488037
MB		 310static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
311 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7
MB		 312{
313 struct ssp_priv *priv = cpu_dai->private_data;
314 struct ssp_device *ssp = priv->dev.ssp;
315 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
316
317#if defined(CONFIG_PXA3xx)
318 if (cpu_is_pxa3xx())
319 ssp_write_reg(ssp, SSACDD, 0);
320#endif
321
322 switch (freq_out) {
323 case 5622000:
324 break;
325 case 11345000:
326 ssacd |= (0x1 << 4);
327 break;
328 case 12235000:
329 ssacd |= (0x2 << 4);
330 break;
331 case 14857000:
332 ssacd |= (0x3 << 4);
333 break;
334 case 32842000:
335 ssacd |= (0x4 << 4);
336 break;
337 case 48000000:
338 ssacd |= (0x5 << 4);
339 break;
340 case 0:
341 /* Disable */
342 break;
343
344 default:
345#ifdef CONFIG_PXA3xx
346 /* PXA3xx has a clock ditherer which can be used to generate
347 * a wider range of frequencies - calculate a value for it.
348 */
349 if (cpu_is_pxa3xx()) {
350 u32 val;
351 u64 tmp = 19968;
352 tmp *= 1000000;
353 do_div(tmp, freq_out);
354 val = tmp;
355
a419aef8 356 val = (val << 16) | 64;
1b340bd7
MB		 357 ssp_write_reg(ssp, SSACDD, val);
358
359 ssacd |= (0x6 << 4);
360
361 dev_dbg(&ssp->pdev->dev,
449bd54d 362 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 363 val, freq_out);
364 break;
365 }
366#endif
367
368 return -EINVAL;
369 }
370
371 ssp_write_reg(ssp, SSACD, ssacd);
372
373 return 0;
374}
375
376/*
377 * Set the active slots in TDM/Network mode
378 */
379static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 380 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7
MB		 381{
382 struct ssp_priv *priv = cpu_dai->private_data;
383 struct ssp_device *ssp = priv->dev.ssp;
384 u32 sscr0;
385
a5479e38
DR		 386 sscr0 = ssp_read_reg(ssp, SSCR0);
387 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 388
a5479e38
DR		 389 /* set slot width */
390 if (slot_width > 16)
391 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
392 else
393 sscr0 |= SSCR0_DataSize(slot_width);
394
395 if (slots > 1) {
396 /* enable network mode */
397 sscr0 |= SSCR0_MOD;
398
399 /* set number of active slots */
400 sscr0 |= SSCR0_SlotsPerFrm(slots);
401
402 /* set active slot mask */
403 ssp_write_reg(ssp, SSTSA, tx_mask);
404 ssp_write_reg(ssp, SSRSA, rx_mask);
405 }
1b340bd7
MB		 406 ssp_write_reg(ssp, SSCR0, sscr0);
407
1b340bd7
MB		 408 return 0;
409}
410
411/*
412 * Tristate the SSP DAI lines
413 */
414static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
415 int tristate)
416{
417 struct ssp_priv *priv = cpu_dai->private_data;
418 struct ssp_device *ssp = priv->dev.ssp;
419 u32 sscr1;
420
421 sscr1 = ssp_read_reg(ssp, SSCR1);
422 if (tristate)
423 sscr1 &= ~SSCR1_TTE;
424 else
425 sscr1 |= SSCR1_TTE;
426 ssp_write_reg(ssp, SSCR1, sscr1);
427
428 return 0;
429}
430
431/*
432 * Set up the SSP DAI format.
433 * The SSP Port must be inactive before calling this function as the
434 * physical interface format is changed.
435 */
436static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
437 unsigned int fmt)
438{
439 struct ssp_priv *priv = cpu_dai->private_data;
440 struct ssp_device *ssp = priv->dev.ssp;
441 u32 sscr0;
442 u32 sscr1;
443 u32 sspsp;
444
cbf1146d
DM		 445 /* check if we need to change anything at all */
446 if (priv->dai_fmt == fmt)
447 return 0;
448
449 /* we can only change the settings if the port is not in use */
450 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
451 dev_err(&ssp->pdev->dev,
452 "can't change hardware dai format: stream is in use");
453 return -EINVAL;
454 }
455
1b340bd7
MB		 456 /* reset port settings */
457 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 458 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 459 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
460 sspsp = 0;
461
462 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
463 case SND_SOC_DAIFMT_CBM_CFM:
464 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
465 break;
466 case SND_SOC_DAIFMT_CBM_CFS:
467 sscr1 |= SSCR1_SCLKDIR;
468 break;
469 case SND_SOC_DAIFMT_CBS_CFS:
470 break;
471 default:
472 return -EINVAL;
473 }
474
fa44c077
DR		 475 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
476 case SND_SOC_DAIFMT_NB_NF:
477 sspsp |= SSPSP_SFRMP;
478 break;
479 case SND_SOC_DAIFMT_NB_IF:
480 break;
481 case SND_SOC_DAIFMT_IB_IF:
482 sspsp |= SSPSP_SCMODE(2);
483 break;
484 case SND_SOC_DAIFMT_IB_NF:
485 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
486 break;
487 default:
488 return -EINVAL;
489 }
1b340bd7
MB		 490
491 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
492 case SND_SOC_DAIFMT_I2S:
72d74664 493 sscr0 |= SSCR0_PSP;
1b340bd7 494 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 495 /* See hw_params() */
1b340bd7
MB		 496 break;
497
498 case SND_SOC_DAIFMT_DSP_A:
499 sspsp |= SSPSP_FSRT;
500 case SND_SOC_DAIFMT_DSP_B:
501 sscr0 |= SSCR0_MOD | SSCR0_PSP;
502 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 503 break;
504
505 default:
506 return -EINVAL;
507 }
508
509 ssp_write_reg(ssp, SSCR0, sscr0);
510 ssp_write_reg(ssp, SSCR1, sscr1);
511 ssp_write_reg(ssp, SSPSP, sspsp);
512
513 dump_registers(ssp);
514
515 /* Since we are configuring the timings for the format by hand
516 * we have to defer some things until hw_params() where we
517 * know parameters like the sample size.
518 */
519 priv->dai_fmt = fmt;
520
521 return 0;
522}
523
524/*
525 * Set the SSP audio DMA parameters and sample size.
526 * Can be called multiple times by oss emulation.
527 */
528static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 529 struct snd_pcm_hw_params *params,
530 struct snd_soc_dai *dai)
1b340bd7
MB		 531{
532 struct snd_soc_pcm_runtime *rtd = substream->private_data;
533 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
534 struct ssp_priv *priv = cpu_dai->private_data;
535 struct ssp_device *ssp = priv->dev.ssp;
2d7e71fa 536 int chn = params_channels(params);
1b340bd7
MB		 537 u32 sscr0;
538 u32 sspsp;
539 int width = snd_pcm_format_physical_width(params_format(params));
92429069 540 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7 541
2d7e71fa
EM		 542 /* generate correct DMA params */
543 if (cpu_dai->dma_data)
544 kfree(cpu_dai->dma_data);
545
92429069
PZ		 546 /* Network mode with one active slot (ttsa == 1) can be used
547 * to force 16-bit frame width on the wire (for S16_LE), even
548 * with two channels. Use 16-bit DMA transfers for this case.
549 */
2d7e71fa
EM		 550 cpu_dai->dma_data = ssp_get_dma_params(ssp,
551 ((chn == 2) && (ttsa != 1)) || (width == 32),
552 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7
MB		 553
554 /* we can only change the settings if the port is not in use */
555 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
556 return 0;
557
558 /* clear selected SSP bits */
559 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
560 ssp_write_reg(ssp, SSCR0, sscr0);
561
562 /* bit size */
563 sscr0 = ssp_read_reg(ssp, SSCR0);
564 switch (params_format(params)) {
565 case SNDRV_PCM_FORMAT_S16_LE:
566#ifdef CONFIG_PXA3xx
567 if (cpu_is_pxa3xx())
568 sscr0 |= SSCR0_FPCKE;
569#endif
570 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 571 break;
572 case SNDRV_PCM_FORMAT_S24_LE:
573 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 574 break;
575 case SNDRV_PCM_FORMAT_S32_LE:
576 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 577 break;
578 }
579 ssp_write_reg(ssp, SSCR0, sscr0);
580
581 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
582 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 583 sspsp = ssp_read_reg(ssp, SSPSP);
584
1a297286 585 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 586 /* This is a special case where the bitclk is 64fs
587 * and we're not dealing with 2*32 bits of audio
588 * samples.
589 *
590 * The SSP values used for that are all found out by
591 * trying and failing a lot; some of the registers
592 * needed for that mode are only available on PXA3xx.
593 */
594
595#ifdef CONFIG_PXA3xx
596 if (!cpu_is_pxa3xx())
597 return -EINVAL;
598
599 sspsp |= SSPSP_SFRMWDTH(width * 2);
600 sspsp |= SSPSP_SFRMDLY(width * 4);
601 sspsp |= SSPSP_EDMYSTOP(3);
602 sspsp |= SSPSP_DMYSTOP(3);
603 sspsp |= SSPSP_DMYSTRT(1);
604#else
605 return -EINVAL;
606#endif
0ce36c5f
MB		 607 } else {
608 /* The frame width is the width the LRCLK is
609 * asserted for; the delay is expressed in
610 * half cycle units. We need the extra cycle
611 * because the data starts clocking out one BCLK
612 * after LRCLK changes polarity.
613 */
614 sspsp |= SSPSP_SFRMWDTH(width + 1);
615 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
616 sspsp |= SSPSP_DMYSTRT(1);
617 }
72d74664 618
1b340bd7
MB		 619 ssp_write_reg(ssp, SSPSP, sspsp);
620 break;
621 default:
622 break;
623 }
624
72d74664 625 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 626 * - complain loudly and fail if they've not been set up yet.
627 */
92429069 628 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 629 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
630 return -EINVAL;
631 }
632
633 dump_registers(ssp);
634
635 return 0;
636}
637
dee89c4d
MB		 638static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
639 struct snd_soc_dai *dai)
1b340bd7
MB		 640{
641 struct snd_soc_pcm_runtime *rtd = substream->private_data;
642 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
643 int ret = 0;
644 struct ssp_priv *priv = cpu_dai->private_data;
645 struct ssp_device *ssp = priv->dev.ssp;
646 int val;
647
648 switch (cmd) {
649 case SNDRV_PCM_TRIGGER_RESUME:
650 ssp_enable(&priv->dev);
651 break;
652 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
653 val = ssp_read_reg(ssp, SSCR1);
654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
655 val |= SSCR1_TSRE;
656 else
657 val |= SSCR1_RSRE;
658 ssp_write_reg(ssp, SSCR1, val);
659 val = ssp_read_reg(ssp, SSSR);
660 ssp_write_reg(ssp, SSSR, val);
661 break;
662 case SNDRV_PCM_TRIGGER_START:
663 val = ssp_read_reg(ssp, SSCR1);
664 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
665 val |= SSCR1_TSRE;
666 else
667 val |= SSCR1_RSRE;
668 ssp_write_reg(ssp, SSCR1, val);
669 ssp_enable(&priv->dev);
670 break;
671 case SNDRV_PCM_TRIGGER_STOP:
672 val = ssp_read_reg(ssp, SSCR1);
673 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
674 val &= ~SSCR1_TSRE;
675 else
676 val &= ~SSCR1_RSRE;
677 ssp_write_reg(ssp, SSCR1, val);
678 break;
679 case SNDRV_PCM_TRIGGER_SUSPEND:
680 ssp_disable(&priv->dev);
681 break;
682 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
683 val = ssp_read_reg(ssp, SSCR1);
684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
685 val &= ~SSCR1_TSRE;
686 else
687 val &= ~SSCR1_RSRE;
688 ssp_write_reg(ssp, SSCR1, val);
689 break;
690
691 default:
692 ret = -EINVAL;
693 }
694
695 dump_registers(ssp);
696
697 return ret;
698}
699
700static int pxa_ssp_probe(struct platform_device *pdev,
701 struct snd_soc_dai *dai)
702{
703 struct ssp_priv *priv;
704 int ret;
705
706 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
707 if (!priv)
708 return -ENOMEM;
709
0664678a 710 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 711 if (priv->dev.ssp == NULL) {
712 ret = -ENODEV;
713 goto err_priv;
714 }
715
a5735b7e 716 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 717 dai->private_data = priv;
718
719 return 0;
720
721err_priv:
722 kfree(priv);
723 return ret;
724}
725
726static void pxa_ssp_remove(struct platform_device *pdev,
727 struct snd_soc_dai *dai)
728{
729 struct ssp_priv *priv = dai->private_data;
730 ssp_free(priv->dev.ssp);
731}
732
733#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
734 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
735 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
736 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
737
738#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
739 SNDRV_PCM_FMTBIT_S24_LE | \
740 SNDRV_PCM_FMTBIT_S32_LE)
741
6335d055
EM		 742static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
743 .startup = pxa_ssp_startup,
744 .shutdown = pxa_ssp_shutdown,
745 .trigger = pxa_ssp_trigger,
746 .hw_params = pxa_ssp_hw_params,
747 .set_sysclk = pxa_ssp_set_dai_sysclk,
748 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
749 .set_pll = pxa_ssp_set_dai_pll,
750 .set_fmt = pxa_ssp_set_dai_fmt,
751 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
752 .set_tristate = pxa_ssp_set_dai_tristate,
753};
754
1b340bd7
MB		 755struct snd_soc_dai pxa_ssp_dai[] = {
756 {
757 .name = "pxa2xx-ssp1",
758 .id = 0,
1b340bd7
MB		 759 .probe = pxa_ssp_probe,
760 .remove = pxa_ssp_remove,
761 .suspend = pxa_ssp_suspend,
762 .resume = pxa_ssp_resume,
763 .playback = {
764 .channels_min = 1,
f34762b6 765 .channels_max = 8,
1b340bd7
MB		 766 .rates = PXA_SSP_RATES,
767 .formats = PXA_SSP_FORMATS,
768 },
769 .capture = {
770 .channels_min = 1,
f34762b6 771 .channels_max = 8,
1b340bd7
MB		 772 .rates = PXA_SSP_RATES,
773 .formats = PXA_SSP_FORMATS,
774 },
6335d055 775 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 776 },
777 { .name = "pxa2xx-ssp2",
778 .id = 1,
1b340bd7
MB		 779 .probe = pxa_ssp_probe,
780 .remove = pxa_ssp_remove,
781 .suspend = pxa_ssp_suspend,
782 .resume = pxa_ssp_resume,
783 .playback = {
784 .channels_min = 1,
f34762b6 785 .channels_max = 8,
1b340bd7
MB		 786 .rates = PXA_SSP_RATES,
787 .formats = PXA_SSP_FORMATS,
788 },
789 .capture = {
790 .channels_min = 1,
f34762b6 791 .channels_max = 8,
1b340bd7
MB		 792 .rates = PXA_SSP_RATES,
793 .formats = PXA_SSP_FORMATS,
794 },
6335d055 795 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 796 },
797 {
798 .name = "pxa2xx-ssp3",
799 .id = 2,
1b340bd7
MB		 800 .probe = pxa_ssp_probe,
801 .remove = pxa_ssp_remove,
802 .suspend = pxa_ssp_suspend,
803 .resume = pxa_ssp_resume,
804 .playback = {
805 .channels_min = 1,
f34762b6 806 .channels_max = 8,
1b340bd7
MB		 807 .rates = PXA_SSP_RATES,
808 .formats = PXA_SSP_FORMATS,
809 },
810 .capture = {
811 .channels_min = 1,
f34762b6 812 .channels_max = 8,
1b340bd7
MB		 813 .rates = PXA_SSP_RATES,
814 .formats = PXA_SSP_FORMATS,
815 },
6335d055 816 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 817 },
818 {
819 .name = "pxa2xx-ssp4",
820 .id = 3,
1b340bd7
MB		 821 .probe = pxa_ssp_probe,
822 .remove = pxa_ssp_remove,
823 .suspend = pxa_ssp_suspend,
824 .resume = pxa_ssp_resume,
825 .playback = {
826 .channels_min = 1,
f34762b6 827 .channels_max = 8,
1b340bd7
MB		 828 .rates = PXA_SSP_RATES,
829 .formats = PXA_SSP_FORMATS,
830 },
831 .capture = {
832 .channels_min = 1,
f34762b6 833 .channels_max = 8,
1b340bd7
MB		 834 .rates = PXA_SSP_RATES,
835 .formats = PXA_SSP_FORMATS,
836 },
6335d055 837 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 838 },
839};
840EXPORT_SYMBOL_GPL(pxa_ssp_dai);
841
c9b3a40f 842static int __init pxa_ssp_init(void)
3f4b783c
MB		 843{
844 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
845}
846module_init(pxa_ssp_init);
847
848static void __exit pxa_ssp_exit(void)
849{
850 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
851}
852module_exit(pxa_ssp_exit);
853
1b340bd7
MB		 854/* Module information */
855MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
856MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
857MODULE_LICENSE("GPL");
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