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75b41027 LG |
1 | /* |
2 | * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Dec 02, 2004 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/wait.h> | |
18 | #include <linux/delay.h> | |
19 | ||
20 | #include <sound/driver.h> | |
21 | #include <sound/core.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/ac97_codec.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | ||
27 | #include <asm/irq.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <asm/hardware.h> | |
30 | #include <asm/arch/pxa-regs.h> | |
31 | #include <asm/arch/audio.h> | |
32 | ||
33 | #include "pxa2xx-pcm.h" | |
596ce32b | 34 | #include "pxa2xx-ac97.h" |
75b41027 LG |
35 | |
36 | static DEFINE_MUTEX(car_mutex); | |
37 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); | |
38 | static volatile long gsr_bits; | |
39 | ||
75b41027 LG |
40 | /* |
41 | * Beware PXA27x bugs: | |
42 | * | |
43 | * o Slot 12 read from modem space will hang controller. | |
44 | * o CDONE, SDONE interrupt fails after any slot 12 IO. | |
45 | * | |
46 | * We therefore have an hybrid approach for waiting on SDONE (interrupt or | |
47 | * 1 jiffy timeout if interrupt never comes). | |
48 | */ | |
49 | ||
50 | static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, | |
51 | unsigned short reg) | |
52 | { | |
53 | unsigned short val = -1; | |
54 | volatile u32 *reg_addr; | |
55 | ||
56 | mutex_lock(&car_mutex); | |
57 | ||
58 | /* set up primary or secondary codec/modem space */ | |
59 | #ifdef CONFIG_PXA27x | |
60 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
61 | #else | |
62 | if (reg == AC97_GPIO_STATUS) | |
63 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; | |
64 | else | |
65 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
66 | #endif | |
67 | reg_addr += (reg >> 1); | |
68 | ||
69 | #ifndef CONFIG_PXA27x | |
70 | if (reg == AC97_GPIO_STATUS) { | |
71 | /* read from controller cache */ | |
72 | val = *reg_addr; | |
73 | goto out; | |
74 | } | |
75 | #endif | |
76 | ||
77 | /* start read access across the ac97 link */ | |
78 | GSR = GSR_CDONE | GSR_SDONE; | |
79 | gsr_bits = 0; | |
80 | val = *reg_addr; | |
81 | ||
82 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); | |
83 | if (!((GSR | gsr_bits) & GSR_SDONE)) { | |
84 | printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", | |
85 | __FUNCTION__, reg, GSR | gsr_bits); | |
86 | val = -1; | |
87 | goto out; | |
88 | } | |
89 | ||
90 | /* valid data now */ | |
91 | GSR = GSR_CDONE | GSR_SDONE; | |
92 | gsr_bits = 0; | |
93 | val = *reg_addr; | |
94 | /* but we've just started another cycle... */ | |
95 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); | |
96 | ||
97 | out: mutex_unlock(&car_mutex); | |
98 | return val; | |
99 | } | |
100 | ||
101 | static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |
102 | unsigned short val) | |
103 | { | |
104 | volatile u32 *reg_addr; | |
105 | ||
106 | mutex_lock(&car_mutex); | |
107 | ||
108 | /* set up primary or secondary codec/modem space */ | |
109 | #ifdef CONFIG_PXA27x | |
110 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
111 | #else | |
112 | if (reg == AC97_GPIO_STATUS) | |
113 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; | |
114 | else | |
115 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
116 | #endif | |
117 | reg_addr += (reg >> 1); | |
118 | ||
119 | GSR = GSR_CDONE | GSR_SDONE; | |
120 | gsr_bits = 0; | |
121 | *reg_addr = val; | |
122 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); | |
123 | if (!((GSR | gsr_bits) & GSR_CDONE)) | |
124 | printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", | |
125 | __FUNCTION__, reg, GSR | gsr_bits); | |
126 | ||
127 | mutex_unlock(&car_mutex); | |
128 | } | |
129 | ||
130 | static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) | |
131 | { | |
132 | gsr_bits = 0; | |
133 | ||
134 | #ifdef CONFIG_PXA27x | |
135 | /* warm reset broken on Bulverde, | |
136 | so manually keep AC97 reset high */ | |
137 | pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); | |
138 | udelay(10); | |
139 | GCR |= GCR_WARM_RST; | |
140 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
141 | udelay(500); | |
142 | #else | |
143 | GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; | |
144 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
145 | #endif | |
146 | ||
147 | if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) | |
148 | printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", | |
149 | __FUNCTION__, gsr_bits); | |
150 | ||
151 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
152 | GCR |= GCR_SDONE_IE|GCR_CDONE_IE; | |
153 | } | |
154 | ||
155 | static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) | |
156 | { | |
157 | GCR &= GCR_COLD_RST; /* clear everything but nCRST */ | |
158 | GCR &= ~GCR_COLD_RST; /* then assert nCRST */ | |
159 | ||
160 | gsr_bits = 0; | |
161 | #ifdef CONFIG_PXA27x | |
162 | /* PXA27x Developers Manual section 13.5.2.2.1 */ | |
03d14a55 | 163 | pxa_set_cken(CKEN_AC97CONF, 1); |
75b41027 | 164 | udelay(5); |
03d14a55 | 165 | pxa_set_cken(CKEN_AC97CONF, 0); |
75b41027 LG |
166 | GCR = GCR_COLD_RST; |
167 | udelay(50); | |
168 | #else | |
169 | GCR = GCR_COLD_RST; | |
170 | GCR |= GCR_CDONE_IE|GCR_SDONE_IE; | |
171 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
172 | #endif | |
173 | ||
174 | if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) | |
175 | printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", | |
176 | __FUNCTION__, gsr_bits); | |
177 | ||
178 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
179 | GCR |= GCR_SDONE_IE|GCR_CDONE_IE; | |
180 | } | |
181 | ||
182 | static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) | |
183 | { | |
184 | long status; | |
185 | ||
186 | status = GSR; | |
187 | if (status) { | |
188 | GSR = status; | |
189 | gsr_bits |= status; | |
190 | wake_up(&gsr_wq); | |
191 | ||
192 | #ifdef CONFIG_PXA27x | |
193 | /* Although we don't use those we still need to clear them | |
194 | since they tend to spuriously trigger when MMC is used | |
195 | (hardware bug? go figure)... */ | |
196 | MISR = MISR_EOC; | |
197 | PISR = PISR_EOC; | |
198 | MCSR = MCSR_EOC; | |
199 | #endif | |
200 | ||
201 | return IRQ_HANDLED; | |
202 | } | |
203 | ||
204 | return IRQ_NONE; | |
205 | } | |
206 | ||
207 | struct snd_ac97_bus_ops soc_ac97_ops = { | |
208 | .read = pxa2xx_ac97_read, | |
209 | .write = pxa2xx_ac97_write, | |
210 | .warm_reset = pxa2xx_ac97_warm_reset, | |
211 | .reset = pxa2xx_ac97_cold_reset, | |
212 | }; | |
213 | ||
214 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { | |
215 | .name = "AC97 PCM Stereo out", | |
216 | .dev_addr = __PREG(PCDR), | |
217 | .drcmr = &DRCMRTXPCDR, | |
218 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
219 | DCMD_BURST32 | DCMD_WIDTH4, | |
220 | }; | |
221 | ||
222 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { | |
223 | .name = "AC97 PCM Stereo in", | |
224 | .dev_addr = __PREG(PCDR), | |
225 | .drcmr = &DRCMRRXPCDR, | |
226 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
227 | DCMD_BURST32 | DCMD_WIDTH4, | |
228 | }; | |
229 | ||
230 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { | |
231 | .name = "AC97 Aux PCM (Slot 5) Mono out", | |
232 | .dev_addr = __PREG(MODR), | |
233 | .drcmr = &DRCMRTXMODR, | |
234 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
235 | DCMD_BURST16 | DCMD_WIDTH2, | |
236 | }; | |
237 | ||
238 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { | |
239 | .name = "AC97 Aux PCM (Slot 5) Mono in", | |
240 | .dev_addr = __PREG(MODR), | |
241 | .drcmr = &DRCMRRXMODR, | |
242 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
243 | DCMD_BURST16 | DCMD_WIDTH2, | |
244 | }; | |
245 | ||
246 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { | |
247 | .name = "AC97 Mic PCM (Slot 6) Mono in", | |
248 | .dev_addr = __PREG(MCDR), | |
249 | .drcmr = &DRCMRRXMCDR, | |
250 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
251 | DCMD_BURST16 | DCMD_WIDTH2, | |
252 | }; | |
253 | ||
254 | #ifdef CONFIG_PM | |
255 | static int pxa2xx_ac97_suspend(struct platform_device *pdev, | |
256 | struct snd_soc_cpu_dai *dai) | |
257 | { | |
258 | GCR |= GCR_ACLINK_OFF; | |
7053acbd | 259 | pxa_set_cken(CKEN_AC97, 0); |
75b41027 LG |
260 | return 0; |
261 | } | |
262 | ||
263 | static int pxa2xx_ac97_resume(struct platform_device *pdev, | |
264 | struct snd_soc_cpu_dai *dai) | |
265 | { | |
266 | pxa_gpio_mode(GPIO31_SYNC_AC97_MD); | |
267 | pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); | |
268 | pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); | |
269 | pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); | |
270 | #ifdef CONFIG_PXA27x | |
271 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | |
272 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
273 | #endif | |
7053acbd | 274 | pxa_set_cken(CKEN_AC97, 1); |
75b41027 LG |
275 | return 0; |
276 | } | |
277 | ||
278 | #else | |
279 | #define pxa2xx_ac97_suspend NULL | |
280 | #define pxa2xx_ac97_resume NULL | |
281 | #endif | |
282 | ||
283 | static int pxa2xx_ac97_probe(struct platform_device *pdev) | |
284 | { | |
285 | int ret; | |
286 | ||
287 | ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); | |
288 | if (ret < 0) | |
289 | goto err; | |
290 | ||
291 | pxa_gpio_mode(GPIO31_SYNC_AC97_MD); | |
292 | pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); | |
293 | pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); | |
294 | pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); | |
295 | #ifdef CONFIG_PXA27x | |
296 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | |
297 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
298 | #endif | |
7053acbd | 299 | pxa_set_cken(CKEN_AC97, 1); |
75b41027 LG |
300 | return 0; |
301 | ||
302 | err: | |
1f750a78 | 303 | if (CKEN & (1 << CKEN_AC97)) { |
75b41027 LG |
304 | GCR |= GCR_ACLINK_OFF; |
305 | free_irq(IRQ_AC97, NULL); | |
7053acbd | 306 | pxa_set_cken(CKEN_AC97, 0); |
75b41027 LG |
307 | } |
308 | return ret; | |
309 | } | |
310 | ||
311 | static void pxa2xx_ac97_remove(struct platform_device *pdev) | |
312 | { | |
313 | GCR |= GCR_ACLINK_OFF; | |
314 | free_irq(IRQ_AC97, NULL); | |
7053acbd | 315 | pxa_set_cken(CKEN_AC97, 0); |
75b41027 LG |
316 | } |
317 | ||
318 | static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, | |
319 | struct snd_pcm_hw_params *params) | |
320 | { | |
321 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 322 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
323 | |
324 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
596ce32b | 325 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; |
75b41027 | 326 | else |
596ce32b | 327 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; |
75b41027 LG |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
332 | static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, | |
333 | struct snd_pcm_hw_params *params) | |
334 | { | |
335 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 336 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
337 | |
338 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
596ce32b | 339 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; |
75b41027 | 340 | else |
596ce32b | 341 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; |
75b41027 LG |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
346 | static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, | |
347 | struct snd_pcm_hw_params *params) | |
348 | { | |
349 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 350 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
351 | |
352 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
353 | return -ENODEV; | |
354 | else | |
596ce32b | 355 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; |
75b41027 LG |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
596ce32b LG |
360 | #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
361 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ | |
362 | SNDRV_PCM_RATE_48000) | |
363 | ||
75b41027 LG |
364 | /* |
365 | * There is only 1 physical AC97 interface for pxa2xx, but it | |
366 | * has extra fifo's that can be used for aux DACs and ADCs. | |
367 | */ | |
368 | struct snd_soc_cpu_dai pxa_ac97_dai[] = { | |
369 | { | |
370 | .name = "pxa2xx-ac97", | |
371 | .id = 0, | |
372 | .type = SND_SOC_DAI_AC97, | |
373 | .probe = pxa2xx_ac97_probe, | |
374 | .remove = pxa2xx_ac97_remove, | |
375 | .suspend = pxa2xx_ac97_suspend, | |
376 | .resume = pxa2xx_ac97_resume, | |
377 | .playback = { | |
378 | .stream_name = "AC97 Playback", | |
379 | .channels_min = 2, | |
596ce32b LG |
380 | .channels_max = 2, |
381 | .rates = PXA2XX_AC97_RATES, | |
382 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
383 | .capture = { |
384 | .stream_name = "AC97 Capture", | |
385 | .channels_min = 2, | |
596ce32b LG |
386 | .channels_max = 2, |
387 | .rates = PXA2XX_AC97_RATES, | |
388 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
389 | .ops = { |
390 | .hw_params = pxa2xx_ac97_hw_params,}, | |
75b41027 LG |
391 | }, |
392 | { | |
393 | .name = "pxa2xx-ac97-aux", | |
394 | .id = 1, | |
395 | .type = SND_SOC_DAI_AC97, | |
396 | .playback = { | |
397 | .stream_name = "AC97 Aux Playback", | |
398 | .channels_min = 1, | |
596ce32b LG |
399 | .channels_max = 1, |
400 | .rates = PXA2XX_AC97_RATES, | |
401 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
402 | .capture = { |
403 | .stream_name = "AC97 Aux Capture", | |
404 | .channels_min = 1, | |
596ce32b LG |
405 | .channels_max = 1, |
406 | .rates = PXA2XX_AC97_RATES, | |
407 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
408 | .ops = { |
409 | .hw_params = pxa2xx_ac97_hw_aux_params,}, | |
75b41027 LG |
410 | }, |
411 | { | |
412 | .name = "pxa2xx-ac97-mic", | |
413 | .id = 2, | |
414 | .type = SND_SOC_DAI_AC97, | |
415 | .capture = { | |
416 | .stream_name = "AC97 Mic Capture", | |
417 | .channels_min = 1, | |
596ce32b LG |
418 | .channels_max = 1, |
419 | .rates = PXA2XX_AC97_RATES, | |
420 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
421 | .ops = { |
422 | .hw_params = pxa2xx_ac97_hw_mic_params,}, | |
596ce32b | 423 | }, |
75b41027 LG |
424 | }; |
425 | ||
426 | EXPORT_SYMBOL_GPL(pxa_ac97_dai); | |
427 | EXPORT_SYMBOL_GPL(soc_ac97_ops); | |
428 | ||
429 | MODULE_AUTHOR("Nicolas Pitre"); | |
430 | MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); | |
431 | MODULE_LICENSE("GPL"); |