projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| cd59f138 KW |
1 | /* |
| 2 | * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 and | |
| 6 | * only version 2 as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | * | |
| 13 | * lpass-lpaif-ipq806x.h -- Definitions for the QTi LPAIF in the ipq806x LPASS | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef __LPASS_LPAIF_H__ | |
| 17 | #define __LPASS_LPAIF_H__ | |
| 18 | ||
| 19 | #define LPAIF_BANK_OFFSET 0x1000 | |
| 20 | ||
| 21 | /* LPAIF I2S */ | |
| 22 | ||
| 23 | #define LPAIF_I2SCTL_REG_BASE 0x0010 | |
| 24 | #define LPAIF_I2SCTL_REG_STRIDE 0x4 | |
| 25 | #define LPAIF_I2SCTL_REG_ADDR(addr, port) \ | |
| 26 | (LPAIF_I2SCTL_REG_BASE + (addr) + (LPAIF_I2SCTL_REG_STRIDE * (port))) | |
| 27 | ||
| 28 | enum lpaif_i2s_ports { | |
| 29 | LPAIF_I2S_PORT_MIN = 0, | |
| 30 | ||
| 31 | LPAIF_I2S_PORT_CODEC_SPK = 0, | |
| 32 | LPAIF_I2S_PORT_CODEC_MIC = 1, | |
| 33 | LPAIF_I2S_PORT_SEC_SPK = 2, | |
| 34 | LPAIF_I2S_PORT_SEC_MIC = 3, | |
| 35 | LPAIF_I2S_PORT_MI2S = 4, | |
| 36 | ||
| 37 | LPAIF_I2S_PORT_MAX = 4, | |
| 38 | LPAIF_I2S_PORT_NUM = 5, | |
| 39 | }; | |
| 40 | ||
| 41 | #define LPAIF_I2SCTL_REG(port) LPAIF_I2SCTL_REG_ADDR(0x0, (port)) | |
| 42 | ||
| 43 | #define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000 | |
| 44 | #define LPAIF_I2SCTL_LOOPBACK_SHIFT 15 | |
| 45 | #define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT) | |
| 46 | #define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT) | |
| 47 | ||
| 48 | #define LPAIF_I2SCTL_SPKEN_MASK 0x4000 | |
| 49 | #define LPAIF_I2SCTL_SPKEN_SHIFT 14 | |
| 50 | #define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT) | |
| 51 | #define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT) | |
| 52 | ||
| 53 | #define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00 | |
| 54 | #define LPAIF_I2SCTL_SPKMODE_SHIFT 10 | |
| 55 | #define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 56 | #define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 57 | #define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 58 | #define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 59 | #define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 60 | #define LPAIF_I2SCTL_SPKMODE_QUAD01 (5 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 61 | #define LPAIF_I2SCTL_SPKMODE_QUAD23 (6 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 62 | #define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 63 | #define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 64 | ||
| 65 | #define LPAIF_I2SCTL_SPKMONO_MASK 0x0200 | |
| 66 | #define LPAIF_I2SCTL_SPKMONO_SHIFT 9 | |
| 67 | #define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT) | |
| 68 | #define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT) | |
| 69 | ||
| 70 | #define LPAIF_I2SCTL_WSSRC_MASK 0x0004 | |
| 71 | #define LPAIF_I2SCTL_WSSRC_SHIFT 2 | |
| 72 | #define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT) | |
| 73 | #define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT) | |
| 74 | ||
| 75 | #define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003 | |
| 76 | #define LPAIF_I2SCTL_BITWIDTH_SHIFT 0 | |
| 77 | #define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 78 | #define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 79 | #define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 80 | ||
| 81 | /* LPAIF IRQ */ | |
| 82 | ||
| 83 | #define LPAIF_IRQ_REG_BASE 0x3000 | |
| 84 | #define LPAIF_IRQ_REG_STRIDE 0x1000 | |
| 85 | #define LPAIF_IRQ_REG_ADDR(addr, port) \ | |
| 86 | (LPAIF_IRQ_REG_BASE + (addr) + (LPAIF_IRQ_REG_STRIDE * (port))) | |
| 87 | ||
| 88 | enum lpaif_irq_ports { | |
| 89 | LPAIF_IRQ_PORT_MIN = 0, | |
| 90 | ||
| 91 | LPAIF_IRQ_PORT_HOST = 0, | |
| 92 | LPAIF_IRQ_PORT_ADSP = 1, | |
| 93 | ||
| 94 | LPAIF_IRQ_PORT_MAX = 2, | |
| 95 | LPAIF_IRQ_PORT_NUM = 3, | |
| 96 | }; | |
| 97 | ||
| 98 | #define LPAIF_IRQEN_REG(port) LPAIF_IRQ_REG_ADDR(0x0, (port)) | |
| 99 | #define LPAIF_IRQSTAT_REG(port) LPAIF_IRQ_REG_ADDR(0x4, (port)) | |
| 100 | #define LPAIF_IRQCLEAR_REG(port) LPAIF_IRQ_REG_ADDR(0xC, (port)) | |
| 101 | ||
| 102 | #define LPAIF_IRQ_BITSTRIDE 3 | |
| 103 | #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 104 | #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 105 | #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 106 | #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 107 | ||
| 108 | /* LPAIF DMA */ | |
| 109 | ||
| 110 | #define LPAIF_RDMA_REG_BASE 0x6000 | |
| 111 | #define LPAIF_RDMA_REG_STRIDE 0x1000 | |
| 112 | #define LPAIF_RDMA_REG_ADDR(addr, chan) \ | |
| 113 | (LPAIF_RDMA_REG_BASE + (addr) + (LPAIF_RDMA_REG_STRIDE * (chan))) | |
| 114 | ||
| 115 | enum lpaif_dma_channels { | |
| 116 | LPAIF_RDMA_CHAN_MIN = 0, | |
| 117 | ||
| 118 | LPAIF_RDMA_CHAN_MI2S = 0, | |
| 119 | LPAIF_RDMA_CHAN_PCM0 = 1, | |
| 120 | LPAIF_RDMA_CHAN_PCM1 = 2, | |
| 121 | ||
| 122 | LPAIF_RDMA_CHAN_MAX = 4, | |
| 123 | LPAIF_RDMA_CHAN_NUM = 5, | |
| 124 | }; | |
| 125 | ||
| 126 | #define LPAIF_RDMACTL_REG(chan) LPAIF_RDMA_REG_ADDR(0x00, (chan)) | |
| 127 | #define LPAIF_RDMABASE_REG(chan) LPAIF_RDMA_REG_ADDR(0x04, (chan)) | |
| 128 | #define LPAIF_RDMABUFF_REG(chan) LPAIF_RDMA_REG_ADDR(0x08, (chan)) | |
| 129 | #define LPAIF_RDMACURR_REG(chan) LPAIF_RDMA_REG_ADDR(0x0C, (chan)) | |
| 130 | #define LPAIF_RDMAPER_REG(chan) LPAIF_RDMA_REG_ADDR(0x10, (chan)) | |
| 131 | ||
| 132 | #define LPAIF_RDMACTL_BURSTEN_MASK 0x800 | |
| 133 | #define LPAIF_RDMACTL_BURSTEN_SHIFT 11 | |
| 134 | #define LPAIF_RDMACTL_BURSTEN_SINGLE (0 << LPAIF_RDMACTL_BURSTEN_SHIFT) | |
| 135 | #define LPAIF_RDMACTL_BURSTEN_INCR4 (1 << LPAIF_RDMACTL_BURSTEN_SHIFT) | |
| 136 | ||
| 137 | #define LPAIF_RDMACTL_WPSCNT_MASK 0x700 | |
| 138 | #define LPAIF_RDMACTL_WPSCNT_SHIFT 8 | |
| 139 | #define LPAIF_RDMACTL_WPSCNT_ONE (0 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 140 | #define LPAIF_RDMACTL_WPSCNT_TWO (1 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 141 | #define LPAIF_RDMACTL_WPSCNT_THREE (2 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 142 | #define LPAIF_RDMACTL_WPSCNT_FOUR (3 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 143 | #define LPAIF_RDMACTL_WPSCNT_SIX (5 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 144 | #define LPAIF_RDMACTL_WPSCNT_EIGHT (7 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 145 | ||
| 146 | #define LPAIF_RDMACTL_AUDINTF_MASK 0x0F0 | |
| 147 | #define LPAIF_RDMACTL_AUDINTF_SHIFT 4 | |
| 148 | #define LPAIF_RDMACTL_AUDINTF_NONE (0 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 149 | #define LPAIF_RDMACTL_AUDINTF_CODEC (1 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 150 | #define LPAIF_RDMACTL_AUDINTF_PCM (2 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 151 | #define LPAIF_RDMACTL_AUDINTF_SEC_I2S (3 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 152 | #define LPAIF_RDMACTL_AUDINTF_MI2S (4 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 153 | #define LPAIF_RDMACTL_AUDINTF_HDMI (5 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 154 | #define LPAIF_RDMACTL_AUDINTF_SEC_PCM (7 << LPAIF_RDMACTL_AUDINTF_SHIFT) | |
| 155 | ||
| 156 | #define LPAIF_RDMACTL_FIFOWM_MASK 0x00E | |
| 157 | #define LPAIF_RDMACTL_FIFOWM_SHIFT 1 | |
| 158 | #define LPAIF_RDMACTL_FIFOWM_1 (0 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 159 | #define LPAIF_RDMACTL_FIFOWM_2 (1 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 160 | #define LPAIF_RDMACTL_FIFOWM_3 (2 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 161 | #define LPAIF_RDMACTL_FIFOWM_4 (3 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 162 | #define LPAIF_RDMACTL_FIFOWM_5 (4 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 163 | #define LPAIF_RDMACTL_FIFOWM_6 (5 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 164 | #define LPAIF_RDMACTL_FIFOWM_7 (6 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 165 | #define LPAIF_RDMACTL_FIFOWM_8 (7 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 166 | ||
| 167 | #define LPAIF_RDMACTL_ENABLE_MASK 0x1 | |
| 168 | #define LPAIF_RDMACTL_ENABLE_SHIFT 0 | |
| 169 | #define LPAIF_RDMACTL_ENABLE_OFF (0 << LPAIF_RDMACTL_ENABLE_SHIFT) | |
| 170 | #define LPAIF_RDMACTL_ENABLE_ON (1 << LPAIF_RDMACTL_ENABLE_SHIFT) | |
| 171 | ||
| 172 | #endif /* __LPASS_LPAIF_H__ */ |