[mirror_ubuntu-zesty-kernel.git] / sound / soc / rockchip / rockchip_i2s.c

/* sound/soc/rockchip/rockchip_i2s.c
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>

#include "rockchip_i2s.h"

#define DRV_NAME "rockchip-i2s"

struct rk_i2s_dev {
	struct device *dev;

	struct clk *hclk;
	struct clk *mclk;

	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;

	struct regmap *regmap;

/*
 * Used to indicate the tx/rx status.
 * I2S controller hopes to start the tx and rx together,
 * also to stop them when they are both try to stop.
*/
	bool tx_start;
	bool rx_start;
	bool is_master_mode;
};

static int i2s_runtime_suspend(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->mclk);

	return 0;
}

static int i2s_runtime_resume(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->mclk);
	if (ret) {
		dev_err(i2s->dev, "clock enable failed %d\n", ret);
		return ret;
	}

	return 0;
}

static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
	return snd_soc_dai_get_drvdata(dai);
}

static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->tx_start = true;
	} else {
		i2s->tx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);

		if (!i2s->rx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->rx_start = true;
	} else {
		i2s->rx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);

		if (!i2s->tx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
				unsigned int fmt)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	unsigned int mask = 0, val = 0;

	mask = I2S_CKR_MSS_MASK;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Set source clock in Master mode */
		val = I2S_CKR_MSS_MASTER;
		i2s->is_master_mode = true;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val = I2S_CKR_MSS_SLAVE;
		i2s->is_master_mode = false;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_TXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_TXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_TXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_TXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);

	mask = I2S_RXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_RXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_RXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_RXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);

	return 0;
}

static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	unsigned int val = 0;
	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;

	if (i2s->is_master_mode) {
		mclk_rate = clk_get_rate(i2s->mclk);
		bclk_rate = 2 * 32 * params_rate(params);
		if (bclk_rate && mclk_rate % bclk_rate)
			return -EINVAL;

		div_bclk = mclk_rate / bclk_rate;
		div_lrck = bclk_rate / params_rate(params);
		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_MDIV_MASK,
				   I2S_CKR_MDIV(div_bclk));

		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_TSD_MASK |
				   I2S_CKR_RSD_MASK,
				   I2S_CKR_TSD(div_lrck) |
				   I2S_CKR_RSD(div_lrck));
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		val |= I2S_TXCR_VDW(8);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		val |= I2S_TXCR_VDW(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		val |= I2S_TXCR_VDW(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val |= I2S_TXCR_VDW(24);
		break;
	default:
		return -EINVAL;
	}

	switch (params_channels(params)) {
	case 8:
		val |= I2S_CHN_8;
		break;
	case 6:
		val |= I2S_CHN_6;
		break;
	case 4:
		val |= I2S_CHN_4;
		break;
	case 2:
		val |= I2S_CHN_2;
		break;
	default:
		dev_err(i2s->dev, "invalid channel: %d\n",
			params_channels(params));
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		regmap_update_bits(i2s->regmap, I2S_RXCR,
				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
				   val);
	else
		regmap_update_bits(i2s->regmap, I2S_TXCR,
				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
				   val);

	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
			   I2S_DMACR_TDL(16));
	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
			   I2S_DMACR_RDL(16));

	val = I2S_CKR_TRCM_TXRX;
	if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
		val = I2S_CKR_TRCM_TXSHARE;

	regmap_update_bits(i2s->regmap, I2S_CKR,
			   I2S_CKR_TRCM_MASK,
			   val);
	return 0;
}

static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 1);
		else
			rockchip_snd_txctrl(i2s, 1);
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 0);
		else
			rockchip_snd_txctrl(i2s, 0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				   unsigned int freq, int dir)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	int ret;

	ret = clk_set_rate(i2s->mclk, freq);
	if (ret)
		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);

	return ret;
}

static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	.hw_params = rockchip_i2s_hw_params,
	.set_sysclk = rockchip_i2s_set_sysclk,
	.set_fmt = rockchip_i2s_set_fmt,
	.trigger = rockchip_i2s_trigger,
};

static struct snd_soc_dai_driver rockchip_i2s_dai = {
	.probe = rockchip_i2s_dai_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 8,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE),
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE),
	},
	.ops = &rockchip_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver rockchip_i2s_component = {
	.name = DRV_NAME,
};

static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_RXDR:
	case I2S_FIFOLR:
	case I2S_INTSR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_INTSR:
	case I2S_CLR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	default:
		return false;
	}
}

static const struct regmap_config rockchip_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = I2S_RXDR,
	.writeable_reg = rockchip_i2s_wr_reg,
	.readable_reg = rockchip_i2s_rd_reg,
	.volatile_reg = rockchip_i2s_volatile_reg,
	.precious_reg = rockchip_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int rockchip_i2s_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct rk_i2s_dev *i2s;
	struct resource *res;
	void __iomem *regs;
	int ret;
	int val;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
		return -ENOMEM;
	}

	/* try to prepare related clocks */
	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	if (IS_ERR(i2s->hclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
		return PTR_ERR(i2s->hclk);
	}
	ret = clk_prepare_enable(i2s->hclk);
	if (ret) {
		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
		return ret;
	}

	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	if (IS_ERR(i2s->mclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
		return PTR_ERR(i2s->mclk);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &rockchip_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev,
			"Failed to initialise managed register map\n");
		return PTR_ERR(i2s->regmap);
	}

	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	i2s->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, i2s);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	/* refine capture channels */
	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
		if (val >= 2 && val <= 8)
			rockchip_i2s_dai.capture.channels_max = val;
		else
			rockchip_i2s_dai.capture.channels_max = 2;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &rockchip_i2s_component,
					      &rockchip_i2s_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI\n");
		goto err_suspend;
	}

	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM\n");
		return ret;
	}

	return 0;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int rockchip_i2s_remove(struct platform_device *pdev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);

	clk_disable_unprepare(i2s->mclk);
	clk_disable_unprepare(i2s->hclk);

	return 0;
}

static const struct of_device_id rockchip_i2s_match[] = {
	{ .compatible = "rockchip,rk3066-i2s", },
	{},
};

static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
			   NULL)
};

static struct platform_driver rockchip_i2s_driver = {
	.probe = rockchip_i2s_probe,
	.remove = rockchip_i2s_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(rockchip_i2s_match),
		.pm = &rockchip_i2s_pm_ops,
	},
};
module_platform_driver(rockchip_i2s_driver);

MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Commit	Line	Data
4495c89f JX	1	/* sound/soc/rockchip/rockchip_i2s.c
	2	*
	3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
	4	*
	5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
	6	* Author: Jianqun <jay.xu@rock-chips.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
1b21572f	13	#include <linux/module.h>
4495c89f JX	14	#include <linux/delay.h>
	15	#include <linux/of_gpio.h>
	16	#include <linux/clk.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/regmap.h>
	19	#include <sound/pcm_params.h>
	20	#include <sound/dmaengine_pcm.h>
	21
	22	#include "rockchip_i2s.h"
	23
	24	#define DRV_NAME "rockchip-i2s"
	25
	26	struct rk_i2s_dev {
	27	struct device *dev;
	28
	29	struct clk *hclk;
	30	struct clk *mclk;
	31
	32	struct snd_dmaengine_dai_dma_data capture_dma_data;
	33	struct snd_dmaengine_dai_dma_data playback_dma_data;
	34
	35	struct regmap *regmap;
	36
	37	/*
	38	* Used to indicate the tx/rx status.
	39	* I2S controller hopes to start the tx and rx together,
	40	* also to stop them when they are both try to stop.
	41	*/
	42	bool tx_start;
	43	bool rx_start;
2458c377	44	bool is_master_mode;
4495c89f JX	45	};
	46
	47	static int i2s_runtime_suspend(struct device *dev)
	48	{
	49	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	50
	51	clk_disable_unprepare(i2s->mclk);
	52
	53	return 0;
	54	}
	55
	56	static int i2s_runtime_resume(struct device *dev)
	57	{
	58	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	59	int ret;
	60
	61	ret = clk_prepare_enable(i2s->mclk);
	62	if (ret) {
	63	dev_err(i2s->dev, "clock enable failed %d\n", ret);
	64	return ret;
	65	}
	66
	67	return 0;
	68	}
	69
	70	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
	71	{
	72	return snd_soc_dai_get_drvdata(dai);
	73	}
	74
	75	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
	76	{
	77	unsigned int val = 0;
	78	int retry = 10;
	79
	80	if (on) {
	81	regmap_update_bits(i2s->regmap, I2S_DMACR,
	82	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	83
	84	regmap_update_bits(i2s->regmap, I2S_XFER,
	85	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
	86	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
	87
	88	i2s->tx_start = true;
	89	} else {
	90	i2s->tx_start = false;
	91
	92	regmap_update_bits(i2s->regmap, I2S_DMACR,
4c5258ac	93	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
4495c89f JX	94
	95	if (!i2s->rx_start) {
	96	regmap_update_bits(i2s->regmap, I2S_XFER,
	97	I2S_XFER_TXS_START \|
	98	I2S_XFER_RXS_START,
	99	I2S_XFER_TXS_STOP \|
	100	I2S_XFER_RXS_STOP);
	101
	102	regmap_update_bits(i2s->regmap, I2S_CLR,
4c5258ac	103	I2S_CLR_TXC \| I2S_CLR_RXC,
4c5258ac	104	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f JX	105
	106	regmap_read(i2s->regmap, I2S_CLR, &val);
	107
	108	/* Should wait for clear operation to finish */
	109	while (val) {
	110	regmap_read(i2s->regmap, I2S_CLR, &val);
	111	retry--;
528a82b4	112	if (!retry) {
4495c89f	113	dev_warn(i2s->dev, "fail to clear\n");
528a82b4 SR	114	break;
528a82b4 SR	115	}
4495c89f JX	116	}
	117	}
	118	}
	119	}
	120
	121	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
	122	{
	123	unsigned int val = 0;
	124	int retry = 10;
	125
	126	if (on) {
	127	regmap_update_bits(i2s->regmap, I2S_DMACR,
	128	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
	129
	130	regmap_update_bits(i2s->regmap, I2S_XFER,
	131	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
	132	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
	133
	134	i2s->rx_start = true;
	135	} else {
	136	i2s->rx_start = false;
	137
	138	regmap_update_bits(i2s->regmap, I2S_DMACR,
	139	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
	140
	141	if (!i2s->tx_start) {
	142	regmap_update_bits(i2s->regmap, I2S_XFER,
	143	I2S_XFER_TXS_START \|
	144	I2S_XFER_RXS_START,
	145	I2S_XFER_TXS_STOP \|
	146	I2S_XFER_RXS_STOP);
	147
	148	regmap_update_bits(i2s->regmap, I2S_CLR,
4c5258ac	149	I2S_CLR_TXC \| I2S_CLR_RXC,
4c5258ac	150	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f JX	151
	152	regmap_read(i2s->regmap, I2S_CLR, &val);
	153
	154	/* Should wait for clear operation to finish */
	155	while (val) {
	156	regmap_read(i2s->regmap, I2S_CLR, &val);
	157	retry--;
29f95bd7	158	if (!retry) {
4495c89f	159	dev_warn(i2s->dev, "fail to clear\n");
29f95bd7 J	160	break;
29f95bd7 J	161	}
4495c89f JX	162	}
	163	}
	164	}
	165	}
	166
	167	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	168	unsigned int fmt)
	169	{
	170	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	171	unsigned int mask = 0, val = 0;
	172
07833d88	173	mask = I2S_CKR_MSS_MASK;
4495c89f JX	174	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4495c89f JX	175	case SND_SOC_DAIFMT_CBS_CFS:
07833d88 J	176	/* Set source clock in Master mode */
07833d88 J	177	val = I2S_CKR_MSS_MASTER;
2458c377	178	i2s->is_master_mode = true;
4495c89f JX	179	break;
4495c89f JX	180	case SND_SOC_DAIFMT_CBM_CFM:
07833d88	181	val = I2S_CKR_MSS_SLAVE;
2458c377	182	i2s->is_master_mode = false;
4495c89f JX	183	break;
	184	default:
	185	return -EINVAL;
	186	}
	187
	188	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	189
	190	mask = I2S_TXCR_IBM_MASK;
	191	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	192	case SND_SOC_DAIFMT_RIGHT_J:
	193	val = I2S_TXCR_IBM_RSJM;
	194	break;
	195	case SND_SOC_DAIFMT_LEFT_J:
	196	val = I2S_TXCR_IBM_LSJM;
	197	break;
	198	case SND_SOC_DAIFMT_I2S:
	199	val = I2S_TXCR_IBM_NORMAL;
	200	break;
	201	default:
	202	return -EINVAL;
	203	}
	204
	205	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
	206
	207	mask = I2S_RXCR_IBM_MASK;
	208	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	209	case SND_SOC_DAIFMT_RIGHT_J:
	210	val = I2S_RXCR_IBM_RSJM;
	211	break;
	212	case SND_SOC_DAIFMT_LEFT_J:
	213	val = I2S_RXCR_IBM_LSJM;
	214	break;
	215	case SND_SOC_DAIFMT_I2S:
	216	val = I2S_RXCR_IBM_NORMAL;
	217	break;
	218	default:
	219	return -EINVAL;
	220	}
	221
	222	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
	223
	224	return 0;
	225	}
	226
	227	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
	228	struct snd_pcm_hw_params *params,
	229	struct snd_soc_dai *dai)
	230	{
	231	struct rk_i2s_dev *i2s = to_info(dai);
b3f2dcdd	232	struct snd_soc_pcm_runtime *rtd = substream->private_data;
4495c89f	233	unsigned int val = 0;
2458c377 CW	234	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
	235
	236	if (i2s->is_master_mode) {
	237	mclk_rate = clk_get_rate(i2s->mclk);
	238	bclk_rate = 2 * 32 * params_rate(params);
	239	if (bclk_rate && mclk_rate % bclk_rate)
	240	return -EINVAL;
	241
	242	div_bclk = mclk_rate / bclk_rate;
	243	div_lrck = bclk_rate / params_rate(params);
	244	regmap_update_bits(i2s->regmap, I2S_CKR,
	245	I2S_CKR_MDIV_MASK,
	246	I2S_CKR_MDIV(div_bclk));
	247
	248	regmap_update_bits(i2s->regmap, I2S_CKR,
	249	I2S_CKR_TSD_MASK \|
	250	I2S_CKR_RSD_MASK,
	251	I2S_CKR_TSD(div_lrck) \|
	252	I2S_CKR_RSD(div_lrck));
	253	}
4495c89f JX	254
	255	switch (params_format(params)) {
	256	case SNDRV_PCM_FORMAT_S8:
	257	val \|= I2S_TXCR_VDW(8);
	258	break;
	259	case SNDRV_PCM_FORMAT_S16_LE:
	260	val \|= I2S_TXCR_VDW(16);
	261	break;
	262	case SNDRV_PCM_FORMAT_S20_3LE:
	263	val \|= I2S_TXCR_VDW(20);
	264	break;
	265	case SNDRV_PCM_FORMAT_S24_LE:
	266	val \|= I2S_TXCR_VDW(24);
	267	break;
	268	default:
	269	return -EINVAL;
	270	}
	271
4c9c018b SZ	272	switch (params_channels(params)) {
	273	case 8:
	274	val \|= I2S_CHN_8;
	275	break;
	276	case 6:
	277	val \|= I2S_CHN_6;
	278	break;
	279	case 4:
	280	val \|= I2S_CHN_4;
	281	break;
	282	case 2:
	283	val \|= I2S_CHN_2;
	284	break;
	285	default:
	286	dev_err(i2s->dev, "invalid channel: %d\n",
	287	params_channels(params));
	288	return -EINVAL;
	289	}
	290
	291	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	292	regmap_update_bits(i2s->regmap, I2S_RXCR,
	293	I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	294	val);
	295	else
	296	regmap_update_bits(i2s->regmap, I2S_TXCR,
	297	I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	298	val);
	299
bba14312 JX	300	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
	301	I2S_DMACR_TDL(16));
	302	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
	303	I2S_DMACR_RDL(16));
4495c89f	304
b3f2dcdd SZ	305	val = I2S_CKR_TRCM_TXRX;
	306	if (dai->driver->symmetric_rates \|\| rtd->dai_link->symmetric_rates)
	307	val = I2S_CKR_TRCM_TXSHARE;
	308
	309	regmap_update_bits(i2s->regmap, I2S_CKR,
	310	I2S_CKR_TRCM_MASK,
	311	val);
4495c89f JX	312	return 0;
	313	}
	314
	315	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
	316	int cmd, struct snd_soc_dai *dai)
	317	{
	318	struct rk_i2s_dev *i2s = to_info(dai);
	319	int ret = 0;
	320
	321	switch (cmd) {
	322	case SNDRV_PCM_TRIGGER_START:
	323	case SNDRV_PCM_TRIGGER_RESUME:
	324	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	325	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	326	rockchip_snd_rxctrl(i2s, 1);
	327	else
	328	rockchip_snd_txctrl(i2s, 1);
	329	break;
	330	case SNDRV_PCM_TRIGGER_SUSPEND:
	331	case SNDRV_PCM_TRIGGER_STOP:
	332	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	333	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	334	rockchip_snd_rxctrl(i2s, 0);
	335	else
	336	rockchip_snd_txctrl(i2s, 0);
	337	break;
	338	default:
	339	ret = -EINVAL;
	340	break;
	341	}
	342
	343	return ret;
	344	}
	345
	346	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	347	unsigned int freq, int dir)
	348	{
	349	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	350	int ret;
	351
	352	ret = clk_set_rate(i2s->mclk, freq);
	353	if (ret)
	354	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
	355
	356	return ret;
	357	}
	358
3b40a802 J	359	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
	360	{
	361	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
	362
	363	dai->capture_dma_data = &i2s->capture_dma_data;
	364	dai->playback_dma_data = &i2s->playback_dma_data;
	365
	366	return 0;
	367	}
	368
4495c89f JX	369	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	370	.hw_params = rockchip_i2s_hw_params,
	371	.set_sysclk = rockchip_i2s_set_sysclk,
	372	.set_fmt = rockchip_i2s_set_fmt,
	373	.trigger = rockchip_i2s_trigger,
	374	};
	375
	376	static struct snd_soc_dai_driver rockchip_i2s_dai = {
3b40a802	377	.probe = rockchip_i2s_dai_probe,
4495c89f	378	.playback = {
3b40a802	379	.stream_name = "Playback",
4495c89f JX	380	.channels_min = 2,
	381	.channels_max = 8,
	382	.rates = SNDRV_PCM_RATE_8000_192000,
	383	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	384	SNDRV_PCM_FMTBIT_S16_LE \|
	385	SNDRV_PCM_FMTBIT_S20_3LE \|
	386	SNDRV_PCM_FMTBIT_S24_LE),
	387	},
	388	.capture = {
3b40a802	389	.stream_name = "Capture",
4495c89f JX	390	.channels_min = 2,
	391	.channels_max = 2,
	392	.rates = SNDRV_PCM_RATE_8000_192000,
	393	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	394	SNDRV_PCM_FMTBIT_S16_LE \|
	395	SNDRV_PCM_FMTBIT_S20_3LE \|
	396	SNDRV_PCM_FMTBIT_S24_LE),
	397	},
	398	.ops = &rockchip_i2s_dai_ops,
a12d159d	399	.symmetric_rates = 1,
4495c89f JX	400	};
	401
	402	static const struct snd_soc_component_driver rockchip_i2s_component = {
	403	.name = DRV_NAME,
	404	};
	405
	406	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
	407	{
	408	switch (reg) {
	409	case I2S_TXCR:
	410	case I2S_RXCR:
	411	case I2S_CKR:
	412	case I2S_DMACR:
	413	case I2S_INTCR:
	414	case I2S_XFER:
	415	case I2S_CLR:
	416	case I2S_TXDR:
	417	return true;
	418	default:
	419	return false;
	420	}
	421	}
	422
	423	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
	424	{
	425	switch (reg) {
	426	case I2S_TXCR:
	427	case I2S_RXCR:
	428	case I2S_CKR:
	429	case I2S_DMACR:
	430	case I2S_INTCR:
	431	case I2S_XFER:
	432	case I2S_CLR:
	433	case I2S_RXDR:
2f1e93f8 J	434	case I2S_FIFOLR:
2f1e93f8 J	435	case I2S_INTSR:
4495c89f JX	436	return true;
	437	default:
	438	return false;
	439	}
	440	}
	441
	442	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
	443	{
	444	switch (reg) {
4495c89f	445	case I2S_INTSR:
2f1e93f8	446	case I2S_CLR:
4495c89f JX	447	return true;
	448	default:
	449	return false;
	450	}
	451	}
	452
	453	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
	454	{
	455	switch (reg) {
4495c89f JX	456	default:
	457	return false;
	458	}
	459	}
	460
	461	static const struct regmap_config rockchip_i2s_regmap_config = {
	462	.reg_bits = 32,
	463	.reg_stride = 4,
	464	.val_bits = 32,
	465	.max_register = I2S_RXDR,
	466	.writeable_reg = rockchip_i2s_wr_reg,
	467	.readable_reg = rockchip_i2s_rd_reg,
	468	.volatile_reg = rockchip_i2s_volatile_reg,
	469	.precious_reg = rockchip_i2s_precious_reg,
	470	.cache_type = REGCACHE_FLAT,
	471	};
	472
	473	static int rockchip_i2s_probe(struct platform_device *pdev)
	474	{
4c9c018b	475	struct device_node *node = pdev->dev.of_node;
4495c89f JX	476	struct rk_i2s_dev *i2s;
	477	struct resource *res;
	478	void __iomem *regs;
	479	int ret;
4c9c018b	480	int val;
4495c89f JX	481
	482	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	483	if (!i2s) {
	484	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
	485	return -ENOMEM;
	486	}
	487
	488	/* try to prepare related clocks */
	489	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	490	if (IS_ERR(i2s->hclk)) {
	491	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
	492	return PTR_ERR(i2s->hclk);
	493	}
01605ad1 J	494	ret = clk_prepare_enable(i2s->hclk);
	495	if (ret) {
	496	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
	497	return ret;
	498	}
4495c89f JX	499
	500	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	501	if (IS_ERR(i2s->mclk)) {
	502	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
	503	return PTR_ERR(i2s->mclk);
	504	}
	505
	506	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	507	regs = devm_ioremap_resource(&pdev->dev, res);
55b21944	508	if (IS_ERR(regs))
4495c89f	509	return PTR_ERR(regs);
4495c89f JX	510
	511	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	512	&rockchip_i2s_regmap_config);
	513	if (IS_ERR(i2s->regmap)) {
	514	dev_err(&pdev->dev,
	515	"Failed to initialise managed register map\n");
	516	return PTR_ERR(i2s->regmap);
	517	}
	518
	519	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	520	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	521	i2s->playback_dma_data.maxburst = 4;
4495c89f JX	522
	523	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	524	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	525	i2s->capture_dma_data.maxburst = 4;
4495c89f JX	526
	527	i2s->dev = &pdev->dev;
	528	dev_set_drvdata(&pdev->dev, i2s);
	529
	530	pm_runtime_enable(&pdev->dev);
	531	if (!pm_runtime_enabled(&pdev->dev)) {
	532	ret = i2s_runtime_resume(&pdev->dev);
	533	if (ret)
	534	goto err_pm_disable;
	535	}
	536
4c9c018b SZ	537	/* refine capture channels */
	538	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
	539	if (val >= 2 && val <= 8)
	540	rockchip_i2s_dai.capture.channels_max = val;
	541	else
	542	rockchip_i2s_dai.capture.channels_max = 2;
	543	}
	544
4495c89f JX	545	ret = devm_snd_soc_register_component(&pdev->dev,
	546	&rockchip_i2s_component,
	547	&rockchip_i2s_dai, 1);
	548	if (ret) {
	549	dev_err(&pdev->dev, "Could not register DAI\n");
	550	goto err_suspend;
	551	}
	552
ebb75c0b	553	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
4495c89f JX	554	if (ret) {
4495c89f JX	555	dev_err(&pdev->dev, "Could not register PCM\n");
ebb75c0b	556	return ret;
4495c89f JX	557	}
	558
	559	return 0;
	560
4495c89f JX	561	err_suspend:
	562	if (!pm_runtime_status_suspended(&pdev->dev))
	563	i2s_runtime_suspend(&pdev->dev);
	564	err_pm_disable:
	565	pm_runtime_disable(&pdev->dev);
	566
	567	return ret;
	568	}
	569
	570	static int rockchip_i2s_remove(struct platform_device *pdev)
	571	{
	572	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
	573
	574	pm_runtime_disable(&pdev->dev);
	575	if (!pm_runtime_status_suspended(&pdev->dev))
	576	i2s_runtime_suspend(&pdev->dev);
	577
	578	clk_disable_unprepare(i2s->mclk);
	579	clk_disable_unprepare(i2s->hclk);
4495c89f JX	580
	581	return 0;
	582	}
	583
	584	static const struct of_device_id rockchip_i2s_match[] = {
	585	{ .compatible = "rockchip,rk3066-i2s", },
	586	{},
	587	};
	588
	589	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	590	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
	591	NULL)
	592	};
	593
	594	static struct platform_driver rockchip_i2s_driver = {
	595	.probe = rockchip_i2s_probe,
	596	.remove = rockchip_i2s_remove,
	597	.driver = {
	598	.name = DRV_NAME,
4495c89f JX	599	.of_match_table = of_match_ptr(rockchip_i2s_match),
	600	.pm = &rockchip_i2s_pm_ops,
	601	},
	602	};
	603	module_platform_driver(rockchip_i2s_driver);
	604
	605	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
	606	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
	607	MODULE_LICENSE("GPL v2");
	608	MODULE_ALIAS("platform:" DRV_NAME);
	609	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);