]>
Commit | Line | Data |
---|---|---|
49646dfa BD |
1 | /* sound/soc/s3c24xx/s3c2412-i2s.c |
2 | * | |
3 | * ALSA Soc Audio Layer - S3C2412 I2S driver | |
4 | * | |
5 | * Copyright (c) 2006 Wolfson Microelectronics PLC. | |
6 | * Graeme Gregory graeme.gregory@wolfsonmicro.com | |
7 | * linux@wolfsonmicro.com | |
8 | * | |
9 | * Copyright (c) 2007, 2004-2005 Simtec Electronics | |
10 | * http://armlinux.simtec.co.uk/ | |
11 | * Ben Dooks <ben@simtec.co.uk> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/kernel.h> | |
8150bc88 | 25 | #include <linux/io.h> |
49646dfa BD |
26 | |
27 | #include <sound/core.h> | |
28 | #include <sound/pcm.h> | |
29 | #include <sound/pcm_params.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/soc.h> | |
a09e64fb | 32 | #include <mach/hardware.h> |
49646dfa | 33 | |
8150bc88 | 34 | #include <plat/regs-s3c2412-iis.h> |
49646dfa | 35 | |
dc85447b | 36 | #include <plat/regs-gpio.h> |
899e6cf5 | 37 | #include <plat/audio.h> |
a09e64fb | 38 | #include <mach/dma.h> |
49646dfa BD |
39 | |
40 | #include "s3c24xx-pcm.h" | |
41 | #include "s3c2412-i2s.h" | |
42 | ||
43 | #define S3C2412_I2S_DEBUG 0 | |
49646dfa BD |
44 | |
45 | #if S3C2412_I2S_DEBUG | |
46 | #define DBG(x...) printk(KERN_INFO x) | |
47 | #else | |
48 | #define DBG(x...) do { } while (0) | |
49 | #endif | |
50 | ||
51 | static struct s3c2410_dma_client s3c2412_dma_client_out = { | |
52 | .name = "I2S PCM Stereo out" | |
53 | }; | |
54 | ||
55 | static struct s3c2410_dma_client s3c2412_dma_client_in = { | |
56 | .name = "I2S PCM Stereo in" | |
57 | }; | |
58 | ||
59 | static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_out = { | |
60 | .client = &s3c2412_dma_client_out, | |
61 | .channel = DMACH_I2S_OUT, | |
62 | .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD, | |
63 | .dma_size = 4, | |
64 | }; | |
65 | ||
66 | static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_in = { | |
67 | .client = &s3c2412_dma_client_in, | |
68 | .channel = DMACH_I2S_IN, | |
69 | .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD, | |
70 | .dma_size = 4, | |
71 | }; | |
72 | ||
dc85447b | 73 | static struct s3c_i2sv2_info s3c2412_i2s; |
49646dfa BD |
74 | |
75 | /* | |
76 | * Set S3C2412 Clock source | |
77 | */ | |
1992a6fb | 78 | static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, |
49646dfa BD |
79 | int clk_id, unsigned int freq, int dir) |
80 | { | |
81 | u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD); | |
82 | ||
83 | DBG("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id, | |
84 | freq, dir); | |
85 | ||
86 | switch (clk_id) { | |
87 | case S3C2412_CLKSRC_PCLK: | |
dc85447b | 88 | s3c2412_i2s.master = 1; |
49646dfa BD |
89 | iismod &= ~S3C2412_IISMOD_MASTER_MASK; |
90 | iismod |= S3C2412_IISMOD_MASTER_INTERNAL; | |
91 | break; | |
92 | case S3C2412_CLKSRC_I2SCLK: | |
dc85447b | 93 | s3c2412_i2s.master = 0; |
49646dfa BD |
94 | iismod &= ~S3C2412_IISMOD_MASTER_MASK; |
95 | iismod |= S3C2412_IISMOD_MASTER_EXTERNAL; | |
96 | break; | |
97 | default: | |
98 | return -EINVAL; | |
99 | } | |
100 | ||
101 | writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD); | |
102 | return 0; | |
103 | } | |
104 | ||
49646dfa BD |
105 | |
106 | struct clk *s3c2412_get_iisclk(void) | |
107 | { | |
108 | return s3c2412_i2s.iis_clk; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(s3c2412_get_iisclk); | |
111 | ||
112 | ||
bdb92876 | 113 | static int s3c2412_i2s_probe(struct platform_device *pdev, |
1992a6fb | 114 | struct snd_soc_dai *dai) |
49646dfa | 115 | { |
dc85447b | 116 | int ret; |
49646dfa | 117 | |
dc85447b | 118 | DBG("Entered %s\n", __func__); |
49646dfa | 119 | |
dc85447b BD |
120 | ret = s3c_i2sv2_probe(pdev, dai, &s3c2412_i2s, S3C2410_PA_IIS); |
121 | if (ret) | |
122 | return ret; | |
49646dfa | 123 | |
dc85447b BD |
124 | s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in; |
125 | s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out; | |
49646dfa BD |
126 | |
127 | s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk"); | |
128 | if (s3c2412_i2s.iis_cclk == NULL) { | |
129 | DBG("failed to get i2sclk clock\n"); | |
130 | iounmap(s3c2412_i2s.regs); | |
131 | return -ENODEV; | |
132 | } | |
133 | ||
dc85447b | 134 | /* Set MPLL as the source for IIS CLK */ |
49646dfa | 135 | |
dc85447b | 136 | clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll")); |
49646dfa BD |
137 | clk_enable(s3c2412_i2s.iis_cclk); |
138 | ||
dc85447b | 139 | s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk; |
49646dfa BD |
140 | |
141 | /* Configure the I2S pins in correct mode */ | |
142 | s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK); | |
143 | s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK); | |
144 | s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK); | |
145 | s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI); | |
146 | s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO); | |
147 | ||
6cab2d3d BD |
148 | return 0; |
149 | } | |
150 | ||
49646dfa BD |
151 | #define S3C2412_I2S_RATES \ |
152 | (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ | |
153 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ | |
154 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) | |
155 | ||
1992a6fb | 156 | struct snd_soc_dai s3c2412_i2s_dai = { |
dc85447b BD |
157 | .name = "s3c2412-i2s", |
158 | .id = 0, | |
159 | .probe = s3c2412_i2s_probe, | |
49646dfa BD |
160 | .playback = { |
161 | .channels_min = 2, | |
162 | .channels_max = 2, | |
163 | .rates = S3C2412_I2S_RATES, | |
164 | .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE, | |
165 | }, | |
166 | .capture = { | |
167 | .channels_min = 2, | |
168 | .channels_max = 2, | |
169 | .rates = S3C2412_I2S_RATES, | |
170 | .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE, | |
171 | }, | |
172 | .ops = { | |
49646dfa BD |
173 | .set_sysclk = s3c2412_i2s_set_sysclk, |
174 | }, | |
175 | }; | |
176 | EXPORT_SYMBOL_GPL(s3c2412_i2s_dai); | |
177 | ||
c9b3a40f | 178 | static int __init s3c2412_i2s_init(void) |
3f4b783c | 179 | { |
dc85447b | 180 | return s3c_i2sv2_register_dai(&s3c2412_i2s_dai); |
3f4b783c MB |
181 | } |
182 | module_init(s3c2412_i2s_init); | |
183 | ||
184 | static void __exit s3c2412_i2s_exit(void) | |
185 | { | |
186 | snd_soc_unregister_dai(&s3c2412_i2s_dai); | |
187 | } | |
188 | module_exit(s3c2412_i2s_exit); | |
189 | ||
49646dfa BD |
190 | /* Module information */ |
191 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
192 | MODULE_DESCRIPTION("S3C2412 I2S SoC Interface"); | |
193 | MODULE_LICENSE("GPL"); |