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ASoC: samsung: i2s: Ensure the RCLK rate is properly determined
[mirror_ubuntu-bionic-kernel.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
074b89bb 13#include <dt-bindings/sound/samsung-i2s.h>
1c7ac018
JB		 14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
074b89bb 17#include <linux/clk-provider.h>
1c7ac018 18#include <linux/io.h>
da155d5b 19#include <linux/module.h>
40476f61 20#include <linux/of.h>
2f7b5d14 21#include <linux/of_device.h>
40476f61 22#include <linux/of_gpio.h>
c5cf4dbc 23#include <linux/pm_runtime.h>
1c7ac018 24
1c7ac018 25#include <sound/soc.h>
0378b6ac 26#include <sound/pcm_params.h>
1c7ac018 27
436d42c6 28#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 29
30#include "dma.h"
61100f40 31#include "idma.h"
1c7ac018 32#include "i2s.h"
172a453d 33#include "i2s-regs.h"
1c7ac018
JB		 34
35#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
36
a5a56871
PV		 37struct samsung_i2s_variant_regs {
38 unsigned int bfs_off;
39 unsigned int rfs_off;
40 unsigned int sdf_off;
41 unsigned int txr_off;
42 unsigned int rclksrc_off;
43 unsigned int mss_off;
44 unsigned int cdclkcon_off;
45 unsigned int lrp_off;
46 unsigned int bfs_mask;
47 unsigned int rfs_mask;
48 unsigned int ftx0cnt_off;
49};
50
40476f61 51struct samsung_i2s_dai_data {
7da493e9 52 u32 quirks;
4720c2fe 53 unsigned int pcm_rates;
a5a56871 54 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 55};
56
1c7ac018
JB		 57struct i2s_dai {
58 /* Platform device for this DAI */
59 struct platform_device *pdev;
af1cf5cf 60 /* Memory mapped SFR region */
1c7ac018 61 void __iomem *addr;
1c7ac018
JB		 62 /* Rate of RCLK source clock */
63 unsigned long rclk_srcrate;
64 /* Frame Clock */
65 unsigned frmclk;
66 /*
67 * Specifically requested RCLK,BCLK by MACHINE Driver.
68 * 0 indicates CPU driver is free to choose any value.
69 */
70 unsigned rfs, bfs;
71 /* I2S Controller's core clock */
72 struct clk *clk;
73 /* Clock for generating I2S signals */
74 struct clk *op_clk;
1c7ac018
JB		 75 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
76 struct i2s_dai *pri_dai;
77 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
78 struct i2s_dai *sec_dai;
79#define DAI_OPENED (1 << 0) /* Dai is opened */
80#define DAI_MANAGER (1 << 1) /* Dai is the manager */
81 unsigned mode;
82 /* Driver for this DAI */
83 struct snd_soc_dai_driver i2s_dai_drv;
84 /* DMA parameters */
69e7a69a
SN		 85 struct snd_dmaengine_dai_dma_data dma_playback;
86 struct snd_dmaengine_dai_dma_data dma_capture;
87 struct snd_dmaengine_dai_dma_data idma_playback;
9bdca822 88 dma_filter_fn filter;
1c7ac018
JB		 89 u32 quirks;
90 u32 suspend_i2smod;
91 u32 suspend_i2scon;
92 u32 suspend_i2spsr;
a5a56871 93 const struct samsung_i2s_variant_regs *variant_regs;
f3670536
SN		 94
95 /* Spinlock protecting access to the device's registers */
96 spinlock_t spinlock;
97 spinlock_t *lock;
074b89bb
SN		 98
99 /* Below fields are only valid if this is the primary FIFO */
100 struct clk *clk_table[3];
101 struct clk_onecell_data clk_data;
1c7ac018
JB		 102};
103
104/* Lock for cross i/f checks */
105static DEFINE_SPINLOCK(lock);
106
107/* If this is the 'overlay' stereo DAI */
108static inline bool is_secondary(struct i2s_dai *i2s)
109{
110 return i2s->pri_dai ? true : false;
111}
112
113/* If operating in SoC-Slave mode */
114static inline bool is_slave(struct i2s_dai *i2s)
115{
a5a56871
PV		 116 u32 mod = readl(i2s->addr + I2SMOD);
117 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 118}
119
120/* If this interface of the controller is transmitting data */
121static inline bool tx_active(struct i2s_dai *i2s)
122{
123 u32 active;
124
125 if (!i2s)
126 return false;
127
33195500 128 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 129
130 if (is_secondary(i2s))
131 active &= CON_TXSDMA_ACTIVE;
132 else
133 active &= CON_TXDMA_ACTIVE;
134
135 return active ? true : false;
136}
137
dcd60fc3
SN		 138/* Return pointer to the other DAI */
139static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
140{
141 return i2s->pri_dai ? : i2s->sec_dai;
142}
143
1c7ac018
JB		 144/* If the other interface of the controller is transmitting data */
145static inline bool other_tx_active(struct i2s_dai *i2s)
146{
dcd60fc3 147 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 148
149 return tx_active(other);
150}
151
152/* If any interface of the controller is transmitting data */
153static inline bool any_tx_active(struct i2s_dai *i2s)
154{
155 return tx_active(i2s) || other_tx_active(i2s);
156}
157
158/* If this interface of the controller is receiving data */
159static inline bool rx_active(struct i2s_dai *i2s)
160{
161 u32 active;
162
163 if (!i2s)
164 return false;
165
33195500 166 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 167
168 return active ? true : false;
169}
170
171/* If the other interface of the controller is receiving data */
172static inline bool other_rx_active(struct i2s_dai *i2s)
173{
dcd60fc3 174 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 175
176 return rx_active(other);
177}
178
179/* If any interface of the controller is receiving data */
180static inline bool any_rx_active(struct i2s_dai *i2s)
181{
182 return rx_active(i2s) || other_rx_active(i2s);
183}
184
185/* If the other DAI is transmitting or receiving data */
186static inline bool other_active(struct i2s_dai *i2s)
187{
188 return other_rx_active(i2s) || other_tx_active(i2s);
189}
190
191/* If this DAI is transmitting or receiving data */
192static inline bool this_active(struct i2s_dai *i2s)
193{
194 return tx_active(i2s) || rx_active(i2s);
195}
196
197/* If the controller is active anyway */
198static inline bool any_active(struct i2s_dai *i2s)
199{
200 return this_active(i2s) || other_active(i2s);
201}
202
203static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
204{
205 return snd_soc_dai_get_drvdata(dai);
206}
207
208static inline bool is_opened(struct i2s_dai *i2s)
209{
210 if (i2s && (i2s->mode & DAI_OPENED))
211 return true;
212 else
213 return false;
214}
215
216static inline bool is_manager(struct i2s_dai *i2s)
217{
218 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
219 return true;
220 else
221 return false;
222}
223
224/* Read RCLK of I2S (in multiples of LRCLK) */
225static inline unsigned get_rfs(struct i2s_dai *i2s)
226{
4ca0c0d4 227 u32 rfs;
a5a56871
PV		 228 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
229 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 230
231 switch (rfs) {
a5a56871
PV		 232 case 7: return 192;
233 case 6: return 96;
234 case 5: return 128;
235 case 4: return 64;
1c7ac018
JB		 236 case 3: return 768;
237 case 2: return 384;
238 case 1: return 512;
239 default: return 256;
240 }
241}
242
243/* Write RCLK of I2S (in multiples of LRCLK) */
244static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
245{
246 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 247 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 248
a5a56871 249 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 250
251 switch (rfs) {
a5a56871
PV		 252 case 192:
253 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
254 break;
255 case 96:
256 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
257 break;
258 case 128:
259 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
260 break;
261 case 64:
262 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
263 break;
1c7ac018 264 case 768:
b60be4aa 265 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 266 break;
267 case 512:
b60be4aa 268 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 269 break;
270 case 384:
b60be4aa 271 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 272 break;
273 default:
b60be4aa 274 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 275 break;
276 }
277
278 writel(mod, i2s->addr + I2SMOD);
279}
280
281/* Read Bit-Clock of I2S (in multiples of LRCLK) */
282static inline unsigned get_bfs(struct i2s_dai *i2s)
283{
4ca0c0d4 284 u32 bfs;
a5a56871
PV		 285 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
286 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 287
288 switch (bfs) {
4ca0c0d4
PV		 289 case 8: return 256;
290 case 7: return 192;
291 case 6: return 128;
292 case 5: return 96;
293 case 4: return 64;
1c7ac018
JB		 294 case 3: return 24;
295 case 2: return 16;
296 case 1: return 48;
297 default: return 32;
298 }
299}
300
301/* Write Bit-Clock of I2S (in multiples of LRCLK) */
302static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
303{
304 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 305 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 306 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 307
308 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
309 if (!tdm && bfs > 48) {
310 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
311 return;
312 }
1c7ac018 313
a5a56871
PV		 314 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
315
1c7ac018
JB		 316 switch (bfs) {
317 case 48:
b60be4aa 318 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 319 break;
320 case 32:
b60be4aa 321 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 322 break;
323 case 24:
b60be4aa 324 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 325 break;
326 case 16:
b60be4aa 327 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 328 break;
4ca0c0d4
PV		 329 case 64:
330 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
331 break;
332 case 96:
333 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
334 break;
335 case 128:
336 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
337 break;
338 case 192:
339 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
340 break;
341 case 256:
342 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 343 break;
344 default:
345 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
346 return;
347 }
348
349 writel(mod, i2s->addr + I2SMOD);
350}
351
352/* Sample-Size */
353static inline int get_blc(struct i2s_dai *i2s)
354{
355 int blc = readl(i2s->addr + I2SMOD);
356
357 blc = (blc >> 13) & 0x3;
358
359 switch (blc) {
360 case 2: return 24;
361 case 1: return 8;
362 default: return 16;
363 }
364}
365
366/* TX Channel Control */
367static void i2s_txctrl(struct i2s_dai *i2s, int on)
368{
369 void __iomem *addr = i2s->addr;
a5a56871 370 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 371 u32 con = readl(addr + I2SCON);
a5a56871 372 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 373
374 if (on) {
375 con |= CON_ACTIVE;
376 con &= ~CON_TXCH_PAUSE;
377
378 if (is_secondary(i2s)) {
379 con |= CON_TXSDMA_ACTIVE;
380 con &= ~CON_TXSDMA_PAUSE;
381 } else {
382 con |= CON_TXDMA_ACTIVE;
383 con &= ~CON_TXDMA_PAUSE;
384 }
385
386 if (any_rx_active(i2s))
a5a56871 387 mod |= 2 << txr_off;
1c7ac018 388 else
a5a56871 389 mod |= 0 << txr_off;
1c7ac018
JB		 390 } else {
391 if (is_secondary(i2s)) {
392 con |= CON_TXSDMA_PAUSE;
393 con &= ~CON_TXSDMA_ACTIVE;
394 } else {
395 con |= CON_TXDMA_PAUSE;
396 con &= ~CON_TXDMA_ACTIVE;
397 }
398
399 if (other_tx_active(i2s)) {
400 writel(con, addr + I2SCON);
401 return;
402 }
403
404 con |= CON_TXCH_PAUSE;
405
406 if (any_rx_active(i2s))
a5a56871 407 mod |= 1 << txr_off;
1c7ac018
JB		 408 else
409 con &= ~CON_ACTIVE;
410 }
411
412 writel(mod, addr + I2SMOD);
413 writel(con, addr + I2SCON);
414}
415
416/* RX Channel Control */
417static void i2s_rxctrl(struct i2s_dai *i2s, int on)
418{
419 void __iomem *addr = i2s->addr;
a5a56871 420 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 421 u32 con = readl(addr + I2SCON);
a5a56871 422 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 423
424 if (on) {
425 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
426 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
427
428 if (any_tx_active(i2s))
a5a56871 429 mod |= 2 << txr_off;
1c7ac018 430 else
a5a56871 431 mod |= 1 << txr_off;
1c7ac018
JB		 432 } else {
433 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
434 con &= ~CON_RXDMA_ACTIVE;
435
436 if (any_tx_active(i2s))
a5a56871 437 mod |= 0 << txr_off;
1c7ac018
JB		 438 else
439 con &= ~CON_ACTIVE;
440 }
441
442 writel(mod, addr + I2SMOD);
443 writel(con, addr + I2SCON);
444}
445
446/* Flush FIFO of an interface */
447static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
448{
449 void __iomem *fic;
450 u32 val;
451
452 if (!i2s)
453 return;
454
455 if (is_secondary(i2s))
456 fic = i2s->addr + I2SFICS;
457 else
458 fic = i2s->addr + I2SFIC;
459
460 /* Flush the FIFO */
461 writel(readl(fic) | flush, fic);
462
463 /* Be patient */
464 val = msecs_to_loops(1) / 1000; /* 1 usec */
465 while (--val)
466 cpu_relax();
467
468 writel(readl(fic) & ~flush, fic);
469}
470
471static int i2s_set_sysclk(struct snd_soc_dai *dai,
472 int clk_id, unsigned int rfs, int dir)
473{
474 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 475 struct i2s_dai *other = get_other_dai(i2s);
a5a56871
PV		 476 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
477 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
478 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
ce8bcdbb 479 u32 mod, mask, val = 0;
316fa9e0 480 unsigned long flags;
dc938ddb
MS		 481 int ret = 0;
482
483 pm_runtime_get_sync(dai->dev);
ce8bcdbb 484
316fa9e0 485 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 486 mod = readl(i2s->addr + I2SMOD);
316fa9e0 487 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 488
489 switch (clk_id) {
c86d50f9 490 case SAMSUNG_I2S_OPCLK:
ce8bcdbb
SN		 491 mask = MOD_OPCLK_MASK;
492 val = dir;
c86d50f9 493 break;
1c7ac018 494 case SAMSUNG_I2S_CDCLK:
ce8bcdbb 495 mask = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 496 /* Shouldn't matter in GATING(CLOCK_IN) mode */
497 if (dir == SND_SOC_CLOCK_IN)
498 rfs = 0;
499
133c2681 500 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 501 (any_active(i2s) &&
502 (((dir == SND_SOC_CLOCK_IN)
a5a56871 503 && !(mod & cdcon_mask)) ||
1c7ac018 504 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 505 && (mod & cdcon_mask))))) {
1c7ac018
JB		 506 dev_err(&i2s->pdev->dev,
507 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 508 ret = -EAGAIN;
509 goto err;
1c7ac018
JB		 510 }
511
512 if (dir == SND_SOC_CLOCK_IN)
ce8bcdbb 513 val = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 514
515 i2s->rfs = rfs;
516 break;
517
518 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
519 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
ce8bcdbb
SN		 520 mask = 1 << i2s_regs->rclksrc_off;
521
1c7ac018
JB		 522 if ((i2s->quirks & QUIRK_NO_MUXPSR)
523 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
524 clk_id = 0;
525 else
526 clk_id = 1;
527
528 if (!any_active(i2s)) {
a6aba536 529 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 530 if ((clk_id && !(mod & rsrc_mask)) ||
531 (!clk_id && (mod & rsrc_mask))) {
98614cf6 532 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 533 clk_put(i2s->op_clk);
534 } else {
6ce534aa
JB		 535 i2s->rclk_srcrate =
536 clk_get_rate(i2s->op_clk);
dc938ddb 537 goto done;
1c7ac018
JB		 538 }
539 }
540
1974a042
PV		 541 if (clk_id)
542 i2s->op_clk = clk_get(&i2s->pdev->dev,
543 "i2s_opclk1");
544 else
545 i2s->op_clk = clk_get(&i2s->pdev->dev,
546 "i2s_opclk0");
a6aba536 547
dc938ddb
MS		 548 if (WARN_ON(IS_ERR(i2s->op_clk))) {
549 ret = PTR_ERR(i2s->op_clk);
afa99da8 550 i2s->op_clk = NULL;
dc938ddb
MS		 551 goto err;
552 }
a6aba536 553
f5c97c7b 554 ret = clk_prepare_enable(i2s->op_clk);
6431a7e3
CJ		 555 if (ret) {
556 clk_put(i2s->op_clk);
557 i2s->op_clk = NULL;
f5c97c7b 558 goto err;
6431a7e3 559 }
1c7ac018
JB		 560 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
561
562 /* Over-ride the other's */
563 if (other) {
564 other->op_clk = i2s->op_clk;
565 other->rclk_srcrate = i2s->rclk_srcrate;
566 }
a5a56871
PV		 567 } else if ((!clk_id && (mod & rsrc_mask))
568 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 569 dev_err(&i2s->pdev->dev,
570 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 571 ret = -EAGAIN;
572 goto err;
1c7ac018
JB		 573 } else {
574 /* Call can't be on the active DAI */
575 i2s->op_clk = other->op_clk;
576 i2s->rclk_srcrate = other->rclk_srcrate;
dc938ddb 577 goto done;
1c7ac018
JB		 578 }
579
ce8bcdbb
SN		 580 if (clk_id == 1)
581 val = 1 << i2s_regs->rclksrc_off;
b2de1d20 582 break;
1c7ac018
JB		 583 default:
584 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
dc938ddb
MS		 585 ret = -EINVAL;
586 goto err;
1c7ac018
JB		 587 }
588
316fa9e0 589 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 590 mod = readl(i2s->addr + I2SMOD);
591 mod = (mod & ~mask) | val;
1c7ac018 592 writel(mod, i2s->addr + I2SMOD);
316fa9e0 593 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb
MS		 594done:
595 pm_runtime_put(dai->dev);
1c7ac018
JB		 596
597 return 0;
dc938ddb
MS		 598err:
599 pm_runtime_put(dai->dev);
600 return ret;
1c7ac018
JB		 601}
602
603static int i2s_set_fmt(struct snd_soc_dai *dai,
604 unsigned int fmt)
605{
606 struct i2s_dai *i2s = to_info(dai);
a5a56871 607 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
ce8bcdbb 608 u32 mod, tmp = 0;
316fa9e0 609 unsigned long flags;
1c7ac018 610
a5a56871
PV		 611 lrp_shift = i2s->variant_regs->lrp_off;
612 sdf_shift = i2s->variant_regs->sdf_off;
613 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 614
b60be4aa
PV		 615 sdf_mask = MOD_SDF_MASK << sdf_shift;
616 lrp_rlow = MOD_LR_RLOW << lrp_shift;
617
1c7ac018
JB		 618 /* Format is priority */
619 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
620 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 621 tmp |= lrp_rlow;
622 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 623 break;
624 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 625 tmp |= lrp_rlow;
626 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 627 break;
628 case SND_SOC_DAIFMT_I2S:
b60be4aa 629 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 630 break;
631 default:
632 dev_err(&i2s->pdev->dev, "Format not supported\n");
633 return -EINVAL;
634 }
635
636 /*
637 * INV flag is relative to the FORMAT flag - if set it simply
638 * flips the polarity specified by the Standard
639 */
640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
641 case SND_SOC_DAIFMT_NB_NF:
642 break;
643 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 644 if (tmp & lrp_rlow)
645 tmp &= ~lrp_rlow;
1c7ac018 646 else
b60be4aa 647 tmp |= lrp_rlow;
1c7ac018
JB		 648 break;
649 default:
650 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
651 return -EINVAL;
652 }
653
654 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
655 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 656 tmp |= mod_slave;
1c7ac018
JB		 657 break;
658 case SND_SOC_DAIFMT_CBS_CFS:
1370f9ec
SN		 659 /*
660 * Set default source clock in Master mode, only when the
661 * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
662 * clock configuration assigned in DT is not overwritten.
663 */
664 if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL)
1c7ac018
JB		 665 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
666 0, SND_SOC_CLOCK_IN);
667 break;
668 default:
669 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
670 return -EINVAL;
671 }
672
dc938ddb 673 pm_runtime_get_sync(dai->dev);
316fa9e0 674 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 675 mod = readl(i2s->addr + I2SMOD);
b60be4aa
PV		 676 /*
677 * Don't change the I2S mode if any controller is active on this
678 * channel.
679 */
1c7ac018 680 if (any_active(i2s) &&
a5a56871 681 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
316fa9e0 682 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 683 pm_runtime_put(dai->dev);
1c7ac018
JB		 684 dev_err(&i2s->pdev->dev,
685 "%s:%d Other DAI busy\n", __func__, __LINE__);
686 return -EAGAIN;
687 }
688
a5a56871 689 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 690 mod |= tmp;
691 writel(mod, i2s->addr + I2SMOD);
316fa9e0 692 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 693 pm_runtime_put(dai->dev);
1c7ac018
JB		 694
695 return 0;
696}
697
698static int i2s_hw_params(struct snd_pcm_substream *substream,
699 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
700{
701 struct i2s_dai *i2s = to_info(dai);
ce8bcdbb 702 u32 mod, mask = 0, val = 0;
316fa9e0 703 unsigned long flags;
1c7ac018 704
dc938ddb
MS		 705 WARN_ON(!pm_runtime_active(dai->dev));
706
1c7ac018 707 if (!is_secondary(i2s))
ce8bcdbb 708 mask |= (MOD_DC2_EN | MOD_DC1_EN);
1c7ac018
JB		 709
710 switch (params_channels(params)) {
711 case 6:
ce8bcdbb 712 val |= MOD_DC2_EN;
1c7ac018 713 case 4:
ce8bcdbb 714 val |= MOD_DC1_EN;
1c7ac018
JB		 715 break;
716 case 2:
588fb705 717 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 718 i2s->dma_playback.addr_width = 4;
588fb705 719 else
69e7a69a 720 i2s->dma_capture.addr_width = 4;
588fb705
SP		 721 break;
722 case 1:
723 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 724 i2s->dma_playback.addr_width = 2;
588fb705 725 else
69e7a69a 726 i2s->dma_capture.addr_width = 2;
588fb705 727
1c7ac018
JB		 728 break;
729 default:
730 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
731 params_channels(params));
732 return -EINVAL;
733 }
734
735 if (is_secondary(i2s))
ce8bcdbb 736 mask |= MOD_BLCS_MASK;
1c7ac018 737 else
ce8bcdbb 738 mask |= MOD_BLCP_MASK;
1c7ac018
JB		 739
740 if (is_manager(i2s))
ce8bcdbb 741 mask |= MOD_BLC_MASK;
1c7ac018 742
88ce1465
TB		 743 switch (params_width(params)) {
744 case 8:
1c7ac018 745 if (is_secondary(i2s))
ce8bcdbb 746 val |= MOD_BLCS_8BIT;
1c7ac018 747 else
ce8bcdbb 748 val |= MOD_BLCP_8BIT;
1c7ac018 749 if (is_manager(i2s))
ce8bcdbb 750 val |= MOD_BLC_8BIT;
1c7ac018 751 break;
88ce1465 752 case 16:
1c7ac018 753 if (is_secondary(i2s))
ce8bcdbb 754 val |= MOD_BLCS_16BIT;
1c7ac018 755 else
ce8bcdbb 756 val |= MOD_BLCP_16BIT;
1c7ac018 757 if (is_manager(i2s))
ce8bcdbb 758 val |= MOD_BLC_16BIT;
1c7ac018 759 break;
88ce1465 760 case 24:
1c7ac018 761 if (is_secondary(i2s))
ce8bcdbb 762 val |= MOD_BLCS_24BIT;
1c7ac018 763 else
ce8bcdbb 764 val |= MOD_BLCP_24BIT;
1c7ac018 765 if (is_manager(i2s))
ce8bcdbb 766 val |= MOD_BLC_24BIT;
1c7ac018
JB		 767 break;
768 default:
769 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
770 params_format(params));
771 return -EINVAL;
772 }
ce8bcdbb 773
316fa9e0 774 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 775 mod = readl(i2s->addr + I2SMOD);
776 mod = (mod & ~mask) | val;
1c7ac018 777 writel(mod, i2s->addr + I2SMOD);
316fa9e0 778 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018 779
69e7a69a 780 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
d37bdf73 781
1c7ac018
JB		 782 i2s->frmclk = params_rate(params);
783
784 return 0;
785}
786
787/* We set constraints on the substream acc to the version of I2S */
788static int i2s_startup(struct snd_pcm_substream *substream,
789 struct snd_soc_dai *dai)
790{
791 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 792 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 793 unsigned long flags;
794
dc938ddb
MS		 795 pm_runtime_get_sync(dai->dev);
796
1c7ac018
JB		 797 spin_lock_irqsave(&lock, flags);
798
799 i2s->mode |= DAI_OPENED;
800
801 if (is_manager(other))
802 i2s->mode &= ~DAI_MANAGER;
803 else
804 i2s->mode |= DAI_MANAGER;
805
2d77828d
PV		 806 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
807 writel(CON_RSTCLR, i2s->addr + I2SCON);
808
1c7ac018
JB		 809 spin_unlock_irqrestore(&lock, flags);
810
811 return 0;
812}
813
814static void i2s_shutdown(struct snd_pcm_substream *substream,
815 struct snd_soc_dai *dai)
816{
817 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 818 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 819 unsigned long flags;
820
821 spin_lock_irqsave(&lock, flags);
822
823 i2s->mode &= ~DAI_OPENED;
824 i2s->mode &= ~DAI_MANAGER;
825
074b89bb 826 if (is_opened(other))
1c7ac018 827 other->mode |= DAI_MANAGER;
074b89bb 828
1c7ac018
JB		 829 /* Reset any constraint on RFS and BFS */
830 i2s->rfs = 0;
831 i2s->bfs = 0;
832
833 spin_unlock_irqrestore(&lock, flags);
dc938ddb
MS		 834
835 pm_runtime_put(dai->dev);
1c7ac018
JB		 836}
837
838static int config_setup(struct i2s_dai *i2s)
839{
dcd60fc3 840 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 841 unsigned rfs, bfs, blc;
842 u32 psr;
843
844 blc = get_blc(i2s);
845
846 bfs = i2s->bfs;
847
848 if (!bfs && other)
849 bfs = other->bfs;
850
851 /* Select least possible multiple(2) if no constraint set */
852 if (!bfs)
853 bfs = blc * 2;
854
855 rfs = i2s->rfs;
856
857 if (!rfs && other)
858 rfs = other->rfs;
859
860 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
861 dev_err(&i2s->pdev->dev,
862 "%d-RFS not supported for 24-blc\n", rfs);
863 return -EINVAL;
864 }
865
866 if (!rfs) {
867 if (bfs == 16 || bfs == 32)
868 rfs = 256;
869 else
870 rfs = 384;
871 }
872
873 /* If already setup and running */
874 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
875 dev_err(&i2s->pdev->dev,
876 "%s:%d Other DAI busy\n", __func__, __LINE__);
877 return -EAGAIN;
878 }
879
1c7ac018
JB		 880 set_bfs(i2s, bfs);
881 set_rfs(i2s, rfs);
882
77010010
PV		 883 /* Don't bother with PSR in Slave mode */
884 if (is_slave(i2s))
885 return 0;
886
1c7ac018 887 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1370f9ec
SN		 888 struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC];
889
890 if (i2s->rclk_srcrate == 0 && rclksrc && !IS_ERR(rclksrc))
891 i2s->rclk_srcrate = clk_get_rate(rclksrc);
892
1c7ac018
JB		 893 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
894 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
895 dev_dbg(&i2s->pdev->dev,
896 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
897 i2s->rclk_srcrate, psr, rfs, bfs);
898 }
899
900 return 0;
901}
902
903static int i2s_trigger(struct snd_pcm_substream *substream,
904 int cmd, struct snd_soc_dai *dai)
905{
906 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
907 struct snd_soc_pcm_runtime *rtd = substream->private_data;
908 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
909 unsigned long flags;
910
911 switch (cmd) {
912 case SNDRV_PCM_TRIGGER_START:
913 case SNDRV_PCM_TRIGGER_RESUME:
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dc938ddb 915 pm_runtime_get_sync(dai->dev);
f3670536 916 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 917
1c7ac018 918 if (config_setup(i2s)) {
f3670536 919 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 920 return -EINVAL;
921 }
922
923 if (capture)
924 i2s_rxctrl(i2s, 1);
925 else
926 i2s_txctrl(i2s, 1);
927
f3670536 928 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 929 break;
930 case SNDRV_PCM_TRIGGER_STOP:
931 case SNDRV_PCM_TRIGGER_SUSPEND:
932 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f3670536 933 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 934
c90887fe 935 if (capture) {
1c7ac018 936 i2s_rxctrl(i2s, 0);
775bc971 937 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 938 } else {
939 i2s_txctrl(i2s, 0);
775bc971 940 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 941 }
775bc971 942
f3670536 943 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 944 pm_runtime_put(dai->dev);
1c7ac018
JB		 945 break;
946 }
947
948 return 0;
949}
950
951static int i2s_set_clkdiv(struct snd_soc_dai *dai,
952 int div_id, int div)
953{
954 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 955 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 956
957 switch (div_id) {
958 case SAMSUNG_I2S_DIV_BCLK:
dc938ddb 959 pm_runtime_get_sync(dai->dev);
1c7ac018
JB		 960 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
961 || (other && other->bfs && (other->bfs != div))) {
dc938ddb 962 pm_runtime_put(dai->dev);
1c7ac018
JB		 963 dev_err(&i2s->pdev->dev,
964 "%s:%d Other DAI busy\n", __func__, __LINE__);
965 return -EAGAIN;
966 }
967 i2s->bfs = div;
dc938ddb 968 pm_runtime_put(dai->dev);
1c7ac018
JB		 969 break;
970 default:
971 dev_err(&i2s->pdev->dev,
972 "Invalid clock divider(%d)\n", div_id);
973 return -EINVAL;
974 }
975
976 return 0;
977}
978
979static snd_pcm_sframes_t
980i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
981{
982 struct i2s_dai *i2s = to_info(dai);
983 u32 reg = readl(i2s->addr + I2SFIC);
984 snd_pcm_sframes_t delay;
a5a56871 985 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018 986
dc938ddb
MS		 987 WARN_ON(!pm_runtime_active(dai->dev));
988
1c7ac018
JB		 989 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
990 delay = FIC_RXCOUNT(reg);
991 else if (is_secondary(i2s))
992 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
993 else
a5a56871 994 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 995
996 return delay;
997}
998
999#ifdef CONFIG_PM
1000static int i2s_suspend(struct snd_soc_dai *dai)
1001{
e7e52dfc 1002 return pm_runtime_force_suspend(dai->dev);
1c7ac018
JB		 1003}
1004
1005static int i2s_resume(struct snd_soc_dai *dai)
1006{
e7e52dfc 1007 return pm_runtime_force_resume(dai->dev);
1c7ac018
JB		 1008}
1009#else
1010#define i2s_suspend NULL
1011#define i2s_resume NULL
1012#endif
1013
1014static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
1015{
1016 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 1017 struct i2s_dai *other = get_other_dai(i2s);
ce8bcdbb 1018 unsigned long flags;
1c7ac018 1019
dc938ddb
MS		 1020 pm_runtime_get_sync(dai->dev);
1021
0ec2ba80 1022 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
69e7a69a 1023 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback,
3688569e 1024 NULL);
872c26bd 1025 } else {
69e7a69a 1026 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
872c26bd 1027 &i2s->dma_capture);
511e3033 1028
872c26bd
SN		 1029 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1030 writel(CON_RSTCLR, i2s->addr + I2SCON);
1c7ac018 1031
872c26bd
SN		 1032 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1033 idma_reg_addr_init(i2s->addr,
69e7a69a 1034 i2s->sec_dai->idma_playback.addr);
872c26bd 1035 }
61100f40 1036
1c7ac018
JB		 1037 /* Reset any constraint on RFS and BFS */
1038 i2s->rfs = 0;
1039 i2s->bfs = 0;
d66eac3e 1040 i2s->rclk_srcrate = 0;
ce8bcdbb
SN		 1041
1042 spin_lock_irqsave(i2s->lock, flags);
1c7ac018
JB		 1043 i2s_txctrl(i2s, 0);
1044 i2s_rxctrl(i2s, 0);
1045 i2s_fifo(i2s, FIC_TXFLUSH);
1046 i2s_fifo(other, FIC_TXFLUSH);
1047 i2s_fifo(i2s, FIC_RXFLUSH);
ce8bcdbb 1048 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 1049
1050 /* Gate CDCLK by default */
1051 if (!is_opened(other))
1052 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1053 0, SND_SOC_CLOCK_IN);
dc938ddb 1054 pm_runtime_put(dai->dev);
1c7ac018
JB		 1055
1056 return 0;
1057}
1058
1059static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1060{
1061 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
5faf071d 1062 unsigned long flags;
1c7ac018 1063
dc938ddb
MS		 1064 pm_runtime_get_sync(dai->dev);
1065
c92f1d0e 1066 if (!is_secondary(i2s)) {
ce8bcdbb 1067 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
5faf071d 1068 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 1069 writel(0, i2s->addr + I2SCON);
5faf071d 1070 spin_unlock_irqrestore(i2s->lock, flags);
ce8bcdbb 1071 }
1c7ac018
JB		 1072 }
1073
dc938ddb
MS		 1074 pm_runtime_put(dai->dev);
1075
1c7ac018
JB		 1076 return 0;
1077}
1078
85e7652d 1079static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1080 .trigger = i2s_trigger,
1081 .hw_params = i2s_hw_params,
1082 .set_fmt = i2s_set_fmt,
1083 .set_clkdiv = i2s_set_clkdiv,
1084 .set_sysclk = i2s_set_sysclk,
1085 .startup = i2s_startup,
1086 .shutdown = i2s_shutdown,
1087 .delay = i2s_delay,
1088};
1089
4b828535
KM		 1090static const struct snd_soc_component_driver samsung_i2s_component = {
1091 .name = "samsung-i2s",
1092};
1093
1c7ac018
JB		 1094#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1095 SNDRV_PCM_FMTBIT_S16_LE | \
1096 SNDRV_PCM_FMTBIT_S24_LE)
1097
4720c2fe
JL		 1098static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
1099 const struct samsung_i2s_dai_data *i2s_dai_data,
1100 bool sec)
1c7ac018
JB		 1101{
1102 struct i2s_dai *i2s;
1103
b960ce74 1104 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1105 if (i2s == NULL)
1106 return NULL;
1107
1108 i2s->pdev = pdev;
1109 i2s->pri_dai = NULL;
1110 i2s->sec_dai = NULL;
22289ddc 1111 i2s->i2s_dai_drv.id = 1;
1c7ac018
JB		 1112 i2s->i2s_dai_drv.symmetric_rates = 1;
1113 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1114 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1115 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1116 i2s->i2s_dai_drv.suspend = i2s_suspend;
1117 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1118 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018 1119 i2s->i2s_dai_drv.playback.channels_max = 2;
4720c2fe 1120 i2s->i2s_dai_drv.playback.rates = i2s_dai_data->pcm_rates;
1c7ac018
JB		 1121 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1122
1123 if (!sec) {
22289ddc 1124 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI;
588fb705 1125 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018 1126 i2s->i2s_dai_drv.capture.channels_max = 2;
4720c2fe 1127 i2s->i2s_dai_drv.capture.rates = i2s_dai_data->pcm_rates;
1c7ac018 1128 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
22289ddc
JL		 1129 } else {
1130 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI_SEC;
c6f9b1eb 1131 }
1c7ac018
JB		 1132 return i2s;
1133}
1134
641d334b 1135#ifdef CONFIG_PM
5b1d3c34
C		 1136static int i2s_runtime_suspend(struct device *dev)
1137{
1138 struct i2s_dai *i2s = dev_get_drvdata(dev);
1139
e7e52dfc
MS		 1140 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
1141 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
1142 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1143
afa99da8
MS		 1144 if (i2s->op_clk)
1145 clk_disable_unprepare(i2s->op_clk);
5b1d3c34
C		 1146 clk_disable_unprepare(i2s->clk);
1147
1148 return 0;
1149}
1150
1151static int i2s_runtime_resume(struct device *dev)
1152{
1153 struct i2s_dai *i2s = dev_get_drvdata(dev);
f5c97c7b 1154 int ret;
5b1d3c34 1155
f5c97c7b
AY		 1156 ret = clk_prepare_enable(i2s->clk);
1157 if (ret)
1158 return ret;
1159
1160 if (i2s->op_clk) {
1161 ret = clk_prepare_enable(i2s->op_clk);
1162 if (ret) {
1163 clk_disable_unprepare(i2s->clk);
1164 return ret;
1165 }
1166 }
5b1d3c34 1167
e7e52dfc
MS		 1168 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
1169 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
1170 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
5b1d3c34
C		 1171
1172 return 0;
1173}
641d334b 1174#endif /* CONFIG_PM */
5b1d3c34 1175
074b89bb
SN		 1176static void i2s_unregister_clocks(struct i2s_dai *i2s)
1177{
1178 int i;
1179
1180 for (i = 0; i < i2s->clk_data.clk_num; i++) {
1181 if (!IS_ERR(i2s->clk_table[i]))
1182 clk_unregister(i2s->clk_table[i]);
1183 }
1184}
1185
1186static void i2s_unregister_clock_provider(struct platform_device *pdev)
1187{
1188 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev);
1189
1190 of_clk_del_provider(pdev->dev.of_node);
1191 i2s_unregister_clocks(i2s);
1192}
1193
1194static int i2s_register_clock_provider(struct platform_device *pdev)
1195{
1196 struct device *dev = &pdev->dev;
1197 struct i2s_dai *i2s = dev_get_drvdata(dev);
1198 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
1199 const char *p_names[2] = { NULL };
1200 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs;
1201 struct clk *rclksrc;
1202 int ret, i;
1203
1204 /* Register the clock provider only if it's expected in the DTB */
1205 if (!of_find_property(dev->of_node, "#clock-cells", NULL))
1206 return 0;
1207
1208 /* Get the RCLKSRC mux clock parent clock names */
1209 for (i = 0; i < ARRAY_SIZE(p_names); i++) {
1210 rclksrc = clk_get(dev, clk_name[i]);
1211 if (IS_ERR(rclksrc))
1212 continue;
1213 p_names[i] = __clk_get_name(rclksrc);
1214 clk_put(rclksrc);
1215 }
1216
1217 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1218 /* Activate the prescaler */
1219 u32 val = readl(i2s->addr + I2SPSR);
1220 writel(val | PSR_PSREN, i2s->addr + I2SPSR);
1221
9b41da80 1222 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
074b89bb
SN		 1223 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
1224 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
1225 i2s->addr + I2SMOD, reg_info->rclksrc_off,
1226 1, 0, i2s->lock);
1227
9b41da80 1228 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
074b89bb
SN		 1229 "i2s_presc", "i2s_rclksrc",
1230 CLK_SET_RATE_PARENT,
1231 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
1232
1233 p_names[0] = "i2s_presc";
1234 i2s->clk_data.clk_num = 2;
1235 }
1236 of_property_read_string_index(dev->of_node,
1237 "clock-output-names", 0, &clk_name[0]);
1238
9b41da80 1239 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, clk_name[0],
074b89bb
SN		 1240 p_names[0], CLK_SET_RATE_PARENT,
1241 i2s->addr + I2SMOD, reg_info->cdclkcon_off,
1242 CLK_GATE_SET_TO_DISABLE, i2s->lock);
1243
1244 i2s->clk_data.clk_num += 1;
1245 i2s->clk_data.clks = i2s->clk_table;
1246
1247 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1248 &i2s->clk_data);
1249 if (ret < 0) {
1250 dev_err(dev, "failed to add clock provider: %d\n", ret);
1251 i2s_unregister_clocks(i2s);
1252 }
1253
1254 return ret;
1255}
1256
fdca21ad 1257static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1258{
1c7ac018 1259 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61 1260 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1c7ac018 1261 struct resource *res;
40476f61
PV		 1262 u32 regs_base, quirks = 0, idma_addr = 0;
1263 struct device_node *np = pdev->dev.of_node;
7da493e9 1264 const struct samsung_i2s_dai_data *i2s_dai_data;
c92f1d0e 1265 int ret;
1c7ac018 1266
2f7b5d14
SN		 1267 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
1268 i2s_dai_data = of_device_get_match_data(&pdev->dev);
1269 else
1270 i2s_dai_data = (struct samsung_i2s_dai_data *)
1271 platform_get_device_id(pdev)->driver_data;
7c62eebb 1272
4720c2fe 1273 pri_dai = i2s_alloc_dai(pdev, i2s_dai_data, false);
40476f61
PV		 1274 if (!pri_dai) {
1275 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1276 return -ENOMEM;
1c7ac018
JB		 1277 }
1278
f3670536
SN		 1279 spin_lock_init(&pri_dai->spinlock);
1280 pri_dai->lock = &pri_dai->spinlock;
1281
40476f61 1282 if (!np) {
40476f61
PV		 1283 if (i2s_pdata == NULL) {
1284 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1285 return -EINVAL;
1286 }
1287
69e7a69a
SN		 1288 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
1289 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
9bdca822 1290 pri_dai->filter = i2s_pdata->dma_filter;
b9a1a743 1291
409c69be
KK		 1292 quirks = i2s_pdata->type.quirks;
1293 idma_addr = i2s_pdata->type.idma_addr;
40476f61 1294 } else {
7da493e9 1295 quirks = i2s_dai_data->quirks;
40476f61
PV		 1296 if (of_property_read_u32(np, "samsung,idma-addr",
1297 &idma_addr)) {
b0759736
PV		 1298 if (quirks & QUIRK_SUPPORTS_IDMA) {
1299 dev_info(&pdev->dev, "idma address is not"\
40476f61 1300 "specified");
40476f61
PV		 1301 }
1302 }
1303 }
064970a0 1304 quirks &= ~(QUIRK_SEC_DAI | QUIRK_SUPPORTS_IDMA);
1c7ac018
JB		 1305
1306 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af1cf5cf
SN		 1307 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1308 if (IS_ERR(pri_dai->addr))
1309 return PTR_ERR(pri_dai->addr);
1c7ac018 1310
1c7ac018
JB		 1311 regs_base = res->start;
1312
0ec2ba80
SN		 1313 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1314 if (IS_ERR(pri_dai->clk)) {
1315 dev_err(&pdev->dev, "Failed to get iis clock\n");
1316 return PTR_ERR(pri_dai->clk);
1317 }
c92f1d0e
SN		 1318
1319 ret = clk_prepare_enable(pri_dai->clk);
1320 if (ret != 0) {
1321 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1322 return ret;
1323 }
69e7a69a
SN		 1324 pri_dai->dma_playback.addr = regs_base + I2STXD;
1325 pri_dai->dma_capture.addr = regs_base + I2SRXD;
b8ab0ccc
SN		 1326 pri_dai->dma_playback.chan_name = "tx";
1327 pri_dai->dma_capture.chan_name = "rx";
69e7a69a
SN		 1328 pri_dai->dma_playback.addr_width = 4;
1329 pri_dai->dma_capture.addr_width = 4;
1c7ac018 1330 pri_dai->quirks = quirks;
a5a56871 1331 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1332
1333 if (quirks & QUIRK_PRI_6CHAN)
1334 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1335
73f5dfc6
MS		 1336 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
1337 NULL, NULL);
1338 if (ret < 0)
1339 goto err_disable_clk;
1340
be2c92eb
MS		 1341 ret = devm_snd_soc_register_component(&pdev->dev,
1342 &samsung_i2s_component,
1343 &pri_dai->i2s_dai_drv, 1);
1344 if (ret < 0)
1345 goto err_disable_clk;
1346
1c7ac018 1347 if (quirks & QUIRK_SEC_DAI) {
4720c2fe 1348 sec_dai = i2s_alloc_dai(pdev, i2s_dai_data, true);
1c7ac018
JB		 1349 if (!sec_dai) {
1350 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
fd61576f
WY		 1351 ret = -ENOMEM;
1352 goto err_disable_clk;
1c7ac018 1353 }
7e5d8706 1354
f3670536 1355 sec_dai->lock = &pri_dai->spinlock;
7e5d8706 1356 sec_dai->variant_regs = pri_dai->variant_regs;
69e7a69a 1357 sec_dai->dma_playback.addr = regs_base + I2STXDS;
b8ab0ccc 1358 sec_dai->dma_playback.chan_name = "tx-sec";
40476f61 1359
9bdca822 1360 if (!np) {
69e7a69a 1361 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
9bdca822
AB		 1362 sec_dai->filter = i2s_pdata->dma_filter;
1363 }
40476f61 1364
69e7a69a 1365 sec_dai->dma_playback.addr_width = 4;
af1cf5cf 1366 sec_dai->addr = pri_dai->addr;
0ec2ba80 1367 sec_dai->clk = pri_dai->clk;
1c7ac018 1368 sec_dai->quirks = quirks;
69e7a69a 1369 sec_dai->idma_playback.addr = idma_addr;
1c7ac018
JB		 1370 sec_dai->pri_dai = pri_dai;
1371 pri_dai->sec_dai = sec_dai;
be2c92eb
MS		 1372
1373 ret = samsung_asoc_dma_platform_register(&pdev->dev,
1374 sec_dai->filter, "tx-sec", NULL);
1375 if (ret < 0)
1376 goto err_disable_clk;
1377
1378 ret = devm_snd_soc_register_component(&pdev->dev,
1379 &samsung_i2s_component,
1380 &sec_dai->i2s_dai_drv, 1);
1381 if (ret < 0)
1382 goto err_disable_clk;
1c7ac018
JB		 1383 }
1384
0429ffef
MB		 1385 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1386 dev_err(&pdev->dev, "Unable to configure gpio\n");
fd61576f
WY		 1387 ret = -EINVAL;
1388 goto err_disable_clk;
1c7ac018
JB		 1389 }
1390
be2c92eb 1391 dev_set_drvdata(&pdev->dev, pri_dai);
1c7ac018 1392
dc938ddb 1393 pm_runtime_set_active(&pdev->dev);
c5cf4dbc
MB		 1394 pm_runtime_enable(&pdev->dev);
1395
2b960386
SN		 1396 ret = i2s_register_clock_provider(pdev);
1397 if (!ret)
1398 return 0;
a08485d8 1399
2b960386 1400 pm_runtime_disable(&pdev->dev);
fd61576f
WY		 1401err_disable_clk:
1402 clk_disable_unprepare(pri_dai->clk);
2b960386 1403 return ret;
1c7ac018
JB		 1404}
1405
fdca21ad 1406static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018 1407{
7b814a7d 1408 struct i2s_dai *pri_dai;
1c7ac018 1409
be2c92eb 1410 pri_dai = dev_get_drvdata(&pdev->dev);
1c7ac018 1411
dc938ddb 1412 pm_runtime_get_sync(&pdev->dev);
be2c92eb 1413 pm_runtime_disable(&pdev->dev);
c92f1d0e 1414
be2c92eb
MS		 1415 i2s_unregister_clock_provider(pdev);
1416 clk_disable_unprepare(pri_dai->clk);
dc938ddb 1417 pm_runtime_put_noidle(&pdev->dev);
1c7ac018 1418
1c7ac018
JB		 1419 return 0;
1420}
1421
a5a56871
PV		 1422static const struct samsung_i2s_variant_regs i2sv3_regs = {
1423 .bfs_off = 1,
1424 .rfs_off = 3,
1425 .sdf_off = 5,
1426 .txr_off = 8,
1427 .rclksrc_off = 10,
1428 .mss_off = 11,
1429 .cdclkcon_off = 12,
1430 .lrp_off = 7,
1431 .bfs_mask = 0x3,
1432 .rfs_mask = 0x3,
1433 .ftx0cnt_off = 8,
1434};
1435
1436static const struct samsung_i2s_variant_regs i2sv6_regs = {
1437 .bfs_off = 0,
1438 .rfs_off = 4,
1439 .sdf_off = 6,
1440 .txr_off = 8,
1441 .rclksrc_off = 10,
1442 .mss_off = 11,
1443 .cdclkcon_off = 12,
1444 .lrp_off = 15,
1445 .bfs_mask = 0xf,
1446 .rfs_mask = 0x3,
1447 .ftx0cnt_off = 8,
1448};
1449
1450static const struct samsung_i2s_variant_regs i2sv7_regs = {
1451 .bfs_off = 0,
1452 .rfs_off = 4,
1453 .sdf_off = 7,
1454 .txr_off = 9,
1455 .rclksrc_off = 11,
1456 .mss_off = 12,
1457 .cdclkcon_off = 22,
1458 .lrp_off = 15,
1459 .bfs_mask = 0xf,
1460 .rfs_mask = 0x7,
1461 .ftx0cnt_off = 0,
1462};
1463
1464static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1465 .bfs_off = 0,
1466 .rfs_off = 3,
1467 .sdf_off = 6,
1468 .txr_off = 8,
1469 .rclksrc_off = 10,
1470 .mss_off = 11,
1471 .cdclkcon_off = 12,
1472 .lrp_off = 15,
1473 .bfs_mask = 0x7,
1474 .rfs_mask = 0x7,
1475 .ftx0cnt_off = 8,
1476};
1477
7da493e9 1478static const struct samsung_i2s_dai_data i2sv3_dai_type = {
7da493e9 1479 .quirks = QUIRK_NO_MUXPSR,
4720c2fe 1480 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1481 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1482};
1483
1484static const struct samsung_i2s_dai_data i2sv5_dai_type = {
b0759736
PV		 1485 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1486 QUIRK_SUPPORTS_IDMA,
4720c2fe 1487 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1488 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1489};
1490
4ca0c0d4 1491static const struct samsung_i2s_dai_data i2sv6_dai_type = {
4ca0c0d4 1492 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1493 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
4720c2fe 1494 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871
PV		 1495 .i2s_variant_regs = &i2sv6_regs,
1496};
1497
1498static const struct samsung_i2s_dai_data i2sv7_dai_type = {
a5a56871
PV		 1499 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1500 QUIRK_SUPPORTS_TDM,
4720c2fe 1501 .pcm_rates = SNDRV_PCM_RATE_8000_192000,
a5a56871
PV		 1502 .i2s_variant_regs = &i2sv7_regs,
1503};
1504
1505static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
a5a56871 1506 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
4720c2fe 1507 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
a5a56871 1508 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1509};
1510
eb8ca0fa 1511static const struct platform_device_id samsung_i2s_driver_ids[] = {
7c62eebb
PV		 1512 {
1513 .name = "samsung-i2s",
3f024980 1514 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1515 },
1516 {},
1517};
2af19558 1518MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1519
40476f61 1520#ifdef CONFIG_OF
40476f61 1521static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1522 {
1523 .compatible = "samsung,s3c6410-i2s",
1524 .data = &i2sv3_dai_type,
1525 }, {
1526 .compatible = "samsung,s5pv210-i2s",
1527 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1528 }, {
1529 .compatible = "samsung,exynos5420-i2s",
1530 .data = &i2sv6_dai_type,
a5a56871
PV		 1531 }, {
1532 .compatible = "samsung,exynos7-i2s",
1533 .data = &i2sv7_dai_type,
1534 }, {
1535 .compatible = "samsung,exynos7-i2s1",
1536 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1537 },
1538 {},
1539};
1540MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1541#endif
1542
5b1d3c34
C		 1543static const struct dev_pm_ops samsung_i2s_pm = {
1544 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1545 i2s_runtime_resume, NULL)
e7e52dfc
MS		 1546 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1547 pm_runtime_force_resume)
5b1d3c34
C		 1548};
1549
1c7ac018
JB		 1550static struct platform_driver samsung_i2s_driver = {
1551 .probe = samsung_i2s_probe,
fdca21ad 1552 .remove = samsung_i2s_remove,
7c62eebb 1553 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1554 .driver = {
1555 .name = "samsung-i2s",
40476f61 1556 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1557 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1558 },
1559};
1560
e00c3f55 1561module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1562
1563/* Module information */
df8ad335 1564MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1565MODULE_DESCRIPTION("Samsung I2S Interface");
1566MODULE_ALIAS("platform:samsung-i2s");
1567MODULE_LICENSE("GPL");
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