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ASoC: samsung: i2s: Ensure proper runtime PM state of I2S device
[mirror_ubuntu-bionic-kernel.git] / sound / soc / samsung / i2s.c
CommitLineData
5033f43c 1/* sound/soc/samsung/i2s.c
1c7ac018
JB		 2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
df8ad335 6 * Jaswinder Singh <jassisinghbrar@gmail.com>
1c7ac018
JB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
074b89bb 13#include <dt-bindings/sound/samsung-i2s.h>
1c7ac018
JB		 14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
074b89bb 17#include <linux/clk-provider.h>
1c7ac018 18#include <linux/io.h>
da155d5b 19#include <linux/module.h>
40476f61 20#include <linux/of.h>
2f7b5d14 21#include <linux/of_device.h>
40476f61 22#include <linux/of_gpio.h>
c5cf4dbc 23#include <linux/pm_runtime.h>
1c7ac018 24
1c7ac018 25#include <sound/soc.h>
0378b6ac 26#include <sound/pcm_params.h>
1c7ac018 27
436d42c6 28#include <linux/platform_data/asoc-s3c.h>
1c7ac018
JB		 29
30#include "dma.h"
61100f40 31#include "idma.h"
1c7ac018 32#include "i2s.h"
172a453d 33#include "i2s-regs.h"
1c7ac018
JB		 34
35#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
36
a5a56871
PV		 37struct samsung_i2s_variant_regs {
38 unsigned int bfs_off;
39 unsigned int rfs_off;
40 unsigned int sdf_off;
41 unsigned int txr_off;
42 unsigned int rclksrc_off;
43 unsigned int mss_off;
44 unsigned int cdclkcon_off;
45 unsigned int lrp_off;
46 unsigned int bfs_mask;
47 unsigned int rfs_mask;
48 unsigned int ftx0cnt_off;
49};
50
40476f61 51struct samsung_i2s_dai_data {
7da493e9 52 u32 quirks;
a5a56871 53 const struct samsung_i2s_variant_regs *i2s_variant_regs;
40476f61
PV		 54};
55
1c7ac018
JB		 56struct i2s_dai {
57 /* Platform device for this DAI */
58 struct platform_device *pdev;
af1cf5cf 59 /* Memory mapped SFR region */
1c7ac018 60 void __iomem *addr;
1c7ac018
JB		 61 /* Rate of RCLK source clock */
62 unsigned long rclk_srcrate;
63 /* Frame Clock */
64 unsigned frmclk;
65 /*
66 * Specifically requested RCLK,BCLK by MACHINE Driver.
67 * 0 indicates CPU driver is free to choose any value.
68 */
69 unsigned rfs, bfs;
70 /* I2S Controller's core clock */
71 struct clk *clk;
72 /* Clock for generating I2S signals */
73 struct clk *op_clk;
1c7ac018
JB		 74 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
75 struct i2s_dai *pri_dai;
76 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
77 struct i2s_dai *sec_dai;
78#define DAI_OPENED (1 << 0) /* Dai is opened */
79#define DAI_MANAGER (1 << 1) /* Dai is the manager */
80 unsigned mode;
81 /* Driver for this DAI */
82 struct snd_soc_dai_driver i2s_dai_drv;
83 /* DMA parameters */
69e7a69a
SN		 84 struct snd_dmaengine_dai_dma_data dma_playback;
85 struct snd_dmaengine_dai_dma_data dma_capture;
86 struct snd_dmaengine_dai_dma_data idma_playback;
9bdca822 87 dma_filter_fn filter;
1c7ac018
JB		 88 u32 quirks;
89 u32 suspend_i2smod;
90 u32 suspend_i2scon;
91 u32 suspend_i2spsr;
a5a56871 92 const struct samsung_i2s_variant_regs *variant_regs;
f3670536
SN		 93
94 /* Spinlock protecting access to the device's registers */
95 spinlock_t spinlock;
96 spinlock_t *lock;
074b89bb
SN		 97
98 /* Below fields are only valid if this is the primary FIFO */
99 struct clk *clk_table[3];
100 struct clk_onecell_data clk_data;
1c7ac018
JB		 101};
102
103/* Lock for cross i/f checks */
104static DEFINE_SPINLOCK(lock);
105
106/* If this is the 'overlay' stereo DAI */
107static inline bool is_secondary(struct i2s_dai *i2s)
108{
109 return i2s->pri_dai ? true : false;
110}
111
112/* If operating in SoC-Slave mode */
113static inline bool is_slave(struct i2s_dai *i2s)
114{
a5a56871
PV		 115 u32 mod = readl(i2s->addr + I2SMOD);
116 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
1c7ac018
JB		 117}
118
119/* If this interface of the controller is transmitting data */
120static inline bool tx_active(struct i2s_dai *i2s)
121{
122 u32 active;
123
124 if (!i2s)
125 return false;
126
33195500 127 active = readl(i2s->addr + I2SCON);
1c7ac018
JB		 128
129 if (is_secondary(i2s))
130 active &= CON_TXSDMA_ACTIVE;
131 else
132 active &= CON_TXDMA_ACTIVE;
133
134 return active ? true : false;
135}
136
dcd60fc3
SN		 137/* Return pointer to the other DAI */
138static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
139{
140 return i2s->pri_dai ? : i2s->sec_dai;
141}
142
1c7ac018
JB		 143/* If the other interface of the controller is transmitting data */
144static inline bool other_tx_active(struct i2s_dai *i2s)
145{
dcd60fc3 146 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 147
148 return tx_active(other);
149}
150
151/* If any interface of the controller is transmitting data */
152static inline bool any_tx_active(struct i2s_dai *i2s)
153{
154 return tx_active(i2s) || other_tx_active(i2s);
155}
156
157/* If this interface of the controller is receiving data */
158static inline bool rx_active(struct i2s_dai *i2s)
159{
160 u32 active;
161
162 if (!i2s)
163 return false;
164
33195500 165 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
1c7ac018
JB		 166
167 return active ? true : false;
168}
169
170/* If the other interface of the controller is receiving data */
171static inline bool other_rx_active(struct i2s_dai *i2s)
172{
dcd60fc3 173 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 174
175 return rx_active(other);
176}
177
178/* If any interface of the controller is receiving data */
179static inline bool any_rx_active(struct i2s_dai *i2s)
180{
181 return rx_active(i2s) || other_rx_active(i2s);
182}
183
184/* If the other DAI is transmitting or receiving data */
185static inline bool other_active(struct i2s_dai *i2s)
186{
187 return other_rx_active(i2s) || other_tx_active(i2s);
188}
189
190/* If this DAI is transmitting or receiving data */
191static inline bool this_active(struct i2s_dai *i2s)
192{
193 return tx_active(i2s) || rx_active(i2s);
194}
195
196/* If the controller is active anyway */
197static inline bool any_active(struct i2s_dai *i2s)
198{
199 return this_active(i2s) || other_active(i2s);
200}
201
202static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
203{
204 return snd_soc_dai_get_drvdata(dai);
205}
206
207static inline bool is_opened(struct i2s_dai *i2s)
208{
209 if (i2s && (i2s->mode & DAI_OPENED))
210 return true;
211 else
212 return false;
213}
214
215static inline bool is_manager(struct i2s_dai *i2s)
216{
217 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
218 return true;
219 else
220 return false;
221}
222
223/* Read RCLK of I2S (in multiples of LRCLK) */
224static inline unsigned get_rfs(struct i2s_dai *i2s)
225{
4ca0c0d4 226 u32 rfs;
a5a56871
PV		 227 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
228 rfs &= i2s->variant_regs->rfs_mask;
1c7ac018
JB		 229
230 switch (rfs) {
a5a56871
PV		 231 case 7: return 192;
232 case 6: return 96;
233 case 5: return 128;
234 case 4: return 64;
1c7ac018
JB		 235 case 3: return 768;
236 case 2: return 384;
237 case 1: return 512;
238 default: return 256;
239 }
240}
241
242/* Write RCLK of I2S (in multiples of LRCLK) */
243static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
244{
245 u32 mod = readl(i2s->addr + I2SMOD);
a5a56871 246 int rfs_shift = i2s->variant_regs->rfs_off;
1c7ac018 247
a5a56871 248 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
1c7ac018
JB		 249
250 switch (rfs) {
a5a56871
PV		 251 case 192:
252 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
253 break;
254 case 96:
255 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
256 break;
257 case 128:
258 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
259 break;
260 case 64:
261 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
262 break;
1c7ac018 263 case 768:
b60be4aa 264 mod |= (MOD_RCLK_768FS << rfs_shift);
1c7ac018
JB		 265 break;
266 case 512:
b60be4aa 267 mod |= (MOD_RCLK_512FS << rfs_shift);
1c7ac018
JB		 268 break;
269 case 384:
b60be4aa 270 mod |= (MOD_RCLK_384FS << rfs_shift);
1c7ac018
JB		 271 break;
272 default:
b60be4aa 273 mod |= (MOD_RCLK_256FS << rfs_shift);
1c7ac018
JB		 274 break;
275 }
276
277 writel(mod, i2s->addr + I2SMOD);
278}
279
280/* Read Bit-Clock of I2S (in multiples of LRCLK) */
281static inline unsigned get_bfs(struct i2s_dai *i2s)
282{
4ca0c0d4 283 u32 bfs;
a5a56871
PV		 284 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
285 bfs &= i2s->variant_regs->bfs_mask;
1c7ac018
JB		 286
287 switch (bfs) {
4ca0c0d4
PV		 288 case 8: return 256;
289 case 7: return 192;
290 case 6: return 128;
291 case 5: return 96;
292 case 4: return 64;
1c7ac018
JB		 293 case 3: return 24;
294 case 2: return 16;
295 case 1: return 48;
296 default: return 32;
297 }
298}
299
300/* Write Bit-Clock of I2S (in multiples of LRCLK) */
301static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
302{
303 u32 mod = readl(i2s->addr + I2SMOD);
4ca0c0d4 304 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
a5a56871 305 int bfs_shift = i2s->variant_regs->bfs_off;
4ca0c0d4
PV		 306
307 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
308 if (!tdm && bfs > 48) {
309 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
310 return;
311 }
1c7ac018 312
a5a56871
PV		 313 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
314
1c7ac018
JB		 315 switch (bfs) {
316 case 48:
b60be4aa 317 mod |= (MOD_BCLK_48FS << bfs_shift);
1c7ac018
JB		 318 break;
319 case 32:
b60be4aa 320 mod |= (MOD_BCLK_32FS << bfs_shift);
1c7ac018
JB		 321 break;
322 case 24:
b60be4aa 323 mod |= (MOD_BCLK_24FS << bfs_shift);
1c7ac018
JB		 324 break;
325 case 16:
b60be4aa 326 mod |= (MOD_BCLK_16FS << bfs_shift);
1c7ac018 327 break;
4ca0c0d4
PV		 328 case 64:
329 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
330 break;
331 case 96:
332 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
333 break;
334 case 128:
335 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
336 break;
337 case 192:
338 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
339 break;
340 case 256:
341 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
1c7ac018
JB		 342 break;
343 default:
344 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
345 return;
346 }
347
348 writel(mod, i2s->addr + I2SMOD);
349}
350
351/* Sample-Size */
352static inline int get_blc(struct i2s_dai *i2s)
353{
354 int blc = readl(i2s->addr + I2SMOD);
355
356 blc = (blc >> 13) & 0x3;
357
358 switch (blc) {
359 case 2: return 24;
360 case 1: return 8;
361 default: return 16;
362 }
363}
364
365/* TX Channel Control */
366static void i2s_txctrl(struct i2s_dai *i2s, int on)
367{
368 void __iomem *addr = i2s->addr;
a5a56871 369 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 370 u32 con = readl(addr + I2SCON);
a5a56871 371 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 372
373 if (on) {
374 con |= CON_ACTIVE;
375 con &= ~CON_TXCH_PAUSE;
376
377 if (is_secondary(i2s)) {
378 con |= CON_TXSDMA_ACTIVE;
379 con &= ~CON_TXSDMA_PAUSE;
380 } else {
381 con |= CON_TXDMA_ACTIVE;
382 con &= ~CON_TXDMA_PAUSE;
383 }
384
385 if (any_rx_active(i2s))
a5a56871 386 mod |= 2 << txr_off;
1c7ac018 387 else
a5a56871 388 mod |= 0 << txr_off;
1c7ac018
JB		 389 } else {
390 if (is_secondary(i2s)) {
391 con |= CON_TXSDMA_PAUSE;
392 con &= ~CON_TXSDMA_ACTIVE;
393 } else {
394 con |= CON_TXDMA_PAUSE;
395 con &= ~CON_TXDMA_ACTIVE;
396 }
397
398 if (other_tx_active(i2s)) {
399 writel(con, addr + I2SCON);
400 return;
401 }
402
403 con |= CON_TXCH_PAUSE;
404
405 if (any_rx_active(i2s))
a5a56871 406 mod |= 1 << txr_off;
1c7ac018
JB		 407 else
408 con &= ~CON_ACTIVE;
409 }
410
411 writel(mod, addr + I2SMOD);
412 writel(con, addr + I2SCON);
413}
414
415/* RX Channel Control */
416static void i2s_rxctrl(struct i2s_dai *i2s, int on)
417{
418 void __iomem *addr = i2s->addr;
a5a56871 419 int txr_off = i2s->variant_regs->txr_off;
1c7ac018 420 u32 con = readl(addr + I2SCON);
a5a56871 421 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
1c7ac018
JB		 422
423 if (on) {
424 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
425 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
426
427 if (any_tx_active(i2s))
a5a56871 428 mod |= 2 << txr_off;
1c7ac018 429 else
a5a56871 430 mod |= 1 << txr_off;
1c7ac018
JB		 431 } else {
432 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
433 con &= ~CON_RXDMA_ACTIVE;
434
435 if (any_tx_active(i2s))
a5a56871 436 mod |= 0 << txr_off;
1c7ac018
JB		 437 else
438 con &= ~CON_ACTIVE;
439 }
440
441 writel(mod, addr + I2SMOD);
442 writel(con, addr + I2SCON);
443}
444
445/* Flush FIFO of an interface */
446static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
447{
448 void __iomem *fic;
449 u32 val;
450
451 if (!i2s)
452 return;
453
454 if (is_secondary(i2s))
455 fic = i2s->addr + I2SFICS;
456 else
457 fic = i2s->addr + I2SFIC;
458
459 /* Flush the FIFO */
460 writel(readl(fic) | flush, fic);
461
462 /* Be patient */
463 val = msecs_to_loops(1) / 1000; /* 1 usec */
464 while (--val)
465 cpu_relax();
466
467 writel(readl(fic) & ~flush, fic);
468}
469
470static int i2s_set_sysclk(struct snd_soc_dai *dai,
471 int clk_id, unsigned int rfs, int dir)
472{
473 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 474 struct i2s_dai *other = get_other_dai(i2s);
a5a56871
PV		 475 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
476 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
477 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
ce8bcdbb 478 u32 mod, mask, val = 0;
316fa9e0 479 unsigned long flags;
dc938ddb
MS		 480 int ret = 0;
481
482 pm_runtime_get_sync(dai->dev);
ce8bcdbb 483
316fa9e0 484 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 485 mod = readl(i2s->addr + I2SMOD);
316fa9e0 486 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 487
488 switch (clk_id) {
c86d50f9 489 case SAMSUNG_I2S_OPCLK:
ce8bcdbb
SN		 490 mask = MOD_OPCLK_MASK;
491 val = dir;
c86d50f9 492 break;
1c7ac018 493 case SAMSUNG_I2S_CDCLK:
ce8bcdbb 494 mask = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 495 /* Shouldn't matter in GATING(CLOCK_IN) mode */
496 if (dir == SND_SOC_CLOCK_IN)
497 rfs = 0;
498
133c2681 499 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
1c7ac018
JB		 500 (any_active(i2s) &&
501 (((dir == SND_SOC_CLOCK_IN)
a5a56871 502 && !(mod & cdcon_mask)) ||
1c7ac018 503 ((dir == SND_SOC_CLOCK_OUT)
a5a56871 504 && (mod & cdcon_mask))))) {
1c7ac018
JB		 505 dev_err(&i2s->pdev->dev,
506 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 507 ret = -EAGAIN;
508 goto err;
1c7ac018
JB		 509 }
510
511 if (dir == SND_SOC_CLOCK_IN)
ce8bcdbb 512 val = 1 << i2s_regs->cdclkcon_off;
1c7ac018
JB		 513
514 i2s->rfs = rfs;
515 break;
516
517 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
518 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
ce8bcdbb
SN		 519 mask = 1 << i2s_regs->rclksrc_off;
520
1c7ac018
JB		 521 if ((i2s->quirks & QUIRK_NO_MUXPSR)
522 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
523 clk_id = 0;
524 else
525 clk_id = 1;
526
527 if (!any_active(i2s)) {
a6aba536 528 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
a5a56871
PV		 529 if ((clk_id && !(mod & rsrc_mask)) ||
530 (!clk_id && (mod & rsrc_mask))) {
98614cf6 531 clk_disable_unprepare(i2s->op_clk);
1c7ac018
JB		 532 clk_put(i2s->op_clk);
533 } else {
6ce534aa
JB		 534 i2s->rclk_srcrate =
535 clk_get_rate(i2s->op_clk);
dc938ddb 536 goto done;
1c7ac018
JB		 537 }
538 }
539
1974a042
PV		 540 if (clk_id)
541 i2s->op_clk = clk_get(&i2s->pdev->dev,
542 "i2s_opclk1");
543 else
544 i2s->op_clk = clk_get(&i2s->pdev->dev,
545 "i2s_opclk0");
a6aba536 546
dc938ddb
MS		 547 if (WARN_ON(IS_ERR(i2s->op_clk))) {
548 ret = PTR_ERR(i2s->op_clk);
549 goto err;
550 }
a6aba536 551
98614cf6 552 clk_prepare_enable(i2s->op_clk);
1c7ac018
JB		 553 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
554
555 /* Over-ride the other's */
556 if (other) {
557 other->op_clk = i2s->op_clk;
558 other->rclk_srcrate = i2s->rclk_srcrate;
559 }
a5a56871
PV		 560 } else if ((!clk_id && (mod & rsrc_mask))
561 || (clk_id && !(mod & rsrc_mask))) {
1c7ac018
JB		 562 dev_err(&i2s->pdev->dev,
563 "%s:%d Other DAI busy\n", __func__, __LINE__);
dc938ddb
MS		 564 ret = -EAGAIN;
565 goto err;
1c7ac018
JB		 566 } else {
567 /* Call can't be on the active DAI */
568 i2s->op_clk = other->op_clk;
569 i2s->rclk_srcrate = other->rclk_srcrate;
dc938ddb 570 goto done;
1c7ac018
JB		 571 }
572
ce8bcdbb
SN		 573 if (clk_id == 1)
574 val = 1 << i2s_regs->rclksrc_off;
b2de1d20 575 break;
1c7ac018
JB		 576 default:
577 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
dc938ddb
MS		 578 ret = -EINVAL;
579 goto err;
1c7ac018
JB		 580 }
581
316fa9e0 582 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 583 mod = readl(i2s->addr + I2SMOD);
584 mod = (mod & ~mask) | val;
1c7ac018 585 writel(mod, i2s->addr + I2SMOD);
316fa9e0 586 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb
MS		 587done:
588 pm_runtime_put(dai->dev);
1c7ac018
JB		 589
590 return 0;
dc938ddb
MS		 591err:
592 pm_runtime_put(dai->dev);
593 return ret;
1c7ac018
JB		 594}
595
596static int i2s_set_fmt(struct snd_soc_dai *dai,
597 unsigned int fmt)
598{
599 struct i2s_dai *i2s = to_info(dai);
a5a56871 600 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
ce8bcdbb 601 u32 mod, tmp = 0;
316fa9e0 602 unsigned long flags;
1c7ac018 603
a5a56871
PV		 604 lrp_shift = i2s->variant_regs->lrp_off;
605 sdf_shift = i2s->variant_regs->sdf_off;
606 mod_slave = 1 << i2s->variant_regs->mss_off;
4ca0c0d4 607
b60be4aa
PV		 608 sdf_mask = MOD_SDF_MASK << sdf_shift;
609 lrp_rlow = MOD_LR_RLOW << lrp_shift;
610
1c7ac018
JB		 611 /* Format is priority */
612 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
613 case SND_SOC_DAIFMT_RIGHT_J:
b60be4aa
PV		 614 tmp |= lrp_rlow;
615 tmp |= (MOD_SDF_MSB << sdf_shift);
1c7ac018
JB		 616 break;
617 case SND_SOC_DAIFMT_LEFT_J:
b60be4aa
PV		 618 tmp |= lrp_rlow;
619 tmp |= (MOD_SDF_LSB << sdf_shift);
1c7ac018
JB		 620 break;
621 case SND_SOC_DAIFMT_I2S:
b60be4aa 622 tmp |= (MOD_SDF_IIS << sdf_shift);
1c7ac018
JB		 623 break;
624 default:
625 dev_err(&i2s->pdev->dev, "Format not supported\n");
626 return -EINVAL;
627 }
628
629 /*
630 * INV flag is relative to the FORMAT flag - if set it simply
631 * flips the polarity specified by the Standard
632 */
633 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
634 case SND_SOC_DAIFMT_NB_NF:
635 break;
636 case SND_SOC_DAIFMT_NB_IF:
b60be4aa
PV		 637 if (tmp & lrp_rlow)
638 tmp &= ~lrp_rlow;
1c7ac018 639 else
b60be4aa 640 tmp |= lrp_rlow;
1c7ac018
JB		 641 break;
642 default:
643 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
644 return -EINVAL;
645 }
646
647 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
648 case SND_SOC_DAIFMT_CBM_CFM:
a5a56871 649 tmp |= mod_slave;
1c7ac018
JB		 650 break;
651 case SND_SOC_DAIFMT_CBS_CFS:
652 /* Set default source clock in Master mode */
653 if (i2s->rclk_srcrate == 0)
654 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
655 0, SND_SOC_CLOCK_IN);
656 break;
657 default:
658 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
659 return -EINVAL;
660 }
661
dc938ddb 662 pm_runtime_get_sync(dai->dev);
316fa9e0 663 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb 664 mod = readl(i2s->addr + I2SMOD);
b60be4aa
PV		 665 /*
666 * Don't change the I2S mode if any controller is active on this
667 * channel.
668 */
1c7ac018 669 if (any_active(i2s) &&
a5a56871 670 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
316fa9e0 671 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 672 pm_runtime_put(dai->dev);
1c7ac018
JB		 673 dev_err(&i2s->pdev->dev,
674 "%s:%d Other DAI busy\n", __func__, __LINE__);
675 return -EAGAIN;
676 }
677
a5a56871 678 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
1c7ac018
JB		 679 mod |= tmp;
680 writel(mod, i2s->addr + I2SMOD);
316fa9e0 681 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 682 pm_runtime_put(dai->dev);
1c7ac018
JB		 683
684 return 0;
685}
686
687static int i2s_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
689{
690 struct i2s_dai *i2s = to_info(dai);
ce8bcdbb 691 u32 mod, mask = 0, val = 0;
316fa9e0 692 unsigned long flags;
1c7ac018 693
dc938ddb
MS		 694 WARN_ON(!pm_runtime_active(dai->dev));
695
1c7ac018 696 if (!is_secondary(i2s))
ce8bcdbb 697 mask |= (MOD_DC2_EN | MOD_DC1_EN);
1c7ac018
JB		 698
699 switch (params_channels(params)) {
700 case 6:
ce8bcdbb 701 val |= MOD_DC2_EN;
1c7ac018 702 case 4:
ce8bcdbb 703 val |= MOD_DC1_EN;
1c7ac018
JB		 704 break;
705 case 2:
588fb705 706 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 707 i2s->dma_playback.addr_width = 4;
588fb705 708 else
69e7a69a 709 i2s->dma_capture.addr_width = 4;
588fb705
SP		 710 break;
711 case 1:
712 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
69e7a69a 713 i2s->dma_playback.addr_width = 2;
588fb705 714 else
69e7a69a 715 i2s->dma_capture.addr_width = 2;
588fb705 716
1c7ac018
JB		 717 break;
718 default:
719 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
720 params_channels(params));
721 return -EINVAL;
722 }
723
724 if (is_secondary(i2s))
ce8bcdbb 725 mask |= MOD_BLCS_MASK;
1c7ac018 726 else
ce8bcdbb 727 mask |= MOD_BLCP_MASK;
1c7ac018
JB		 728
729 if (is_manager(i2s))
ce8bcdbb 730 mask |= MOD_BLC_MASK;
1c7ac018 731
88ce1465
TB		 732 switch (params_width(params)) {
733 case 8:
1c7ac018 734 if (is_secondary(i2s))
ce8bcdbb 735 val |= MOD_BLCS_8BIT;
1c7ac018 736 else
ce8bcdbb 737 val |= MOD_BLCP_8BIT;
1c7ac018 738 if (is_manager(i2s))
ce8bcdbb 739 val |= MOD_BLC_8BIT;
1c7ac018 740 break;
88ce1465 741 case 16:
1c7ac018 742 if (is_secondary(i2s))
ce8bcdbb 743 val |= MOD_BLCS_16BIT;
1c7ac018 744 else
ce8bcdbb 745 val |= MOD_BLCP_16BIT;
1c7ac018 746 if (is_manager(i2s))
ce8bcdbb 747 val |= MOD_BLC_16BIT;
1c7ac018 748 break;
88ce1465 749 case 24:
1c7ac018 750 if (is_secondary(i2s))
ce8bcdbb 751 val |= MOD_BLCS_24BIT;
1c7ac018 752 else
ce8bcdbb 753 val |= MOD_BLCP_24BIT;
1c7ac018 754 if (is_manager(i2s))
ce8bcdbb 755 val |= MOD_BLC_24BIT;
1c7ac018
JB		 756 break;
757 default:
758 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
759 params_format(params));
760 return -EINVAL;
761 }
ce8bcdbb 762
316fa9e0 763 spin_lock_irqsave(i2s->lock, flags);
ce8bcdbb
SN		 764 mod = readl(i2s->addr + I2SMOD);
765 mod = (mod & ~mask) | val;
1c7ac018 766 writel(mod, i2s->addr + I2SMOD);
316fa9e0 767 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018 768
69e7a69a 769 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
d37bdf73 770
1c7ac018
JB		 771 i2s->frmclk = params_rate(params);
772
773 return 0;
774}
775
776/* We set constraints on the substream acc to the version of I2S */
777static int i2s_startup(struct snd_pcm_substream *substream,
778 struct snd_soc_dai *dai)
779{
780 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 781 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 782 unsigned long flags;
783
dc938ddb
MS		 784 pm_runtime_get_sync(dai->dev);
785
1c7ac018
JB		 786 spin_lock_irqsave(&lock, flags);
787
788 i2s->mode |= DAI_OPENED;
789
790 if (is_manager(other))
791 i2s->mode &= ~DAI_MANAGER;
792 else
793 i2s->mode |= DAI_MANAGER;
794
2d77828d
PV		 795 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
796 writel(CON_RSTCLR, i2s->addr + I2SCON);
797
1c7ac018
JB		 798 spin_unlock_irqrestore(&lock, flags);
799
800 return 0;
801}
802
803static void i2s_shutdown(struct snd_pcm_substream *substream,
804 struct snd_soc_dai *dai)
805{
806 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 807 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 808 unsigned long flags;
809
810 spin_lock_irqsave(&lock, flags);
811
812 i2s->mode &= ~DAI_OPENED;
813 i2s->mode &= ~DAI_MANAGER;
814
074b89bb 815 if (is_opened(other))
1c7ac018 816 other->mode |= DAI_MANAGER;
074b89bb 817
1c7ac018
JB		 818 /* Reset any constraint on RFS and BFS */
819 i2s->rfs = 0;
820 i2s->bfs = 0;
821
822 spin_unlock_irqrestore(&lock, flags);
dc938ddb
MS		 823
824 pm_runtime_put(dai->dev);
1c7ac018
JB		 825}
826
827static int config_setup(struct i2s_dai *i2s)
828{
dcd60fc3 829 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 830 unsigned rfs, bfs, blc;
831 u32 psr;
832
833 blc = get_blc(i2s);
834
835 bfs = i2s->bfs;
836
837 if (!bfs && other)
838 bfs = other->bfs;
839
840 /* Select least possible multiple(2) if no constraint set */
841 if (!bfs)
842 bfs = blc * 2;
843
844 rfs = i2s->rfs;
845
846 if (!rfs && other)
847 rfs = other->rfs;
848
849 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
850 dev_err(&i2s->pdev->dev,
851 "%d-RFS not supported for 24-blc\n", rfs);
852 return -EINVAL;
853 }
854
855 if (!rfs) {
856 if (bfs == 16 || bfs == 32)
857 rfs = 256;
858 else
859 rfs = 384;
860 }
861
862 /* If already setup and running */
863 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
864 dev_err(&i2s->pdev->dev,
865 "%s:%d Other DAI busy\n", __func__, __LINE__);
866 return -EAGAIN;
867 }
868
1c7ac018
JB		 869 set_bfs(i2s, bfs);
870 set_rfs(i2s, rfs);
871
77010010
PV		 872 /* Don't bother with PSR in Slave mode */
873 if (is_slave(i2s))
874 return 0;
875
1c7ac018
JB		 876 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
877 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
878 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
879 dev_dbg(&i2s->pdev->dev,
880 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
881 i2s->rclk_srcrate, psr, rfs, bfs);
882 }
883
884 return 0;
885}
886
887static int i2s_trigger(struct snd_pcm_substream *substream,
888 int cmd, struct snd_soc_dai *dai)
889{
890 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
891 struct snd_soc_pcm_runtime *rtd = substream->private_data;
892 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
893 unsigned long flags;
894
895 switch (cmd) {
896 case SNDRV_PCM_TRIGGER_START:
897 case SNDRV_PCM_TRIGGER_RESUME:
898 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dc938ddb 899 pm_runtime_get_sync(dai->dev);
f3670536 900 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 901
1c7ac018 902 if (config_setup(i2s)) {
f3670536 903 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 904 return -EINVAL;
905 }
906
907 if (capture)
908 i2s_rxctrl(i2s, 1);
909 else
910 i2s_txctrl(i2s, 1);
911
f3670536 912 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 913 break;
914 case SNDRV_PCM_TRIGGER_STOP:
915 case SNDRV_PCM_TRIGGER_SUSPEND:
916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f3670536 917 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 918
c90887fe 919 if (capture) {
1c7ac018 920 i2s_rxctrl(i2s, 0);
775bc971 921 i2s_fifo(i2s, FIC_RXFLUSH);
c90887fe
JB		 922 } else {
923 i2s_txctrl(i2s, 0);
775bc971 924 i2s_fifo(i2s, FIC_TXFLUSH);
c90887fe 925 }
775bc971 926
f3670536 927 spin_unlock_irqrestore(i2s->lock, flags);
dc938ddb 928 pm_runtime_put(dai->dev);
1c7ac018
JB		 929 break;
930 }
931
932 return 0;
933}
934
935static int i2s_set_clkdiv(struct snd_soc_dai *dai,
936 int div_id, int div)
937{
938 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 939 struct i2s_dai *other = get_other_dai(i2s);
1c7ac018
JB		 940
941 switch (div_id) {
942 case SAMSUNG_I2S_DIV_BCLK:
dc938ddb 943 pm_runtime_get_sync(dai->dev);
1c7ac018
JB		 944 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
945 || (other && other->bfs && (other->bfs != div))) {
dc938ddb 946 pm_runtime_put(dai->dev);
1c7ac018
JB		 947 dev_err(&i2s->pdev->dev,
948 "%s:%d Other DAI busy\n", __func__, __LINE__);
949 return -EAGAIN;
950 }
951 i2s->bfs = div;
dc938ddb 952 pm_runtime_put(dai->dev);
1c7ac018
JB		 953 break;
954 default:
955 dev_err(&i2s->pdev->dev,
956 "Invalid clock divider(%d)\n", div_id);
957 return -EINVAL;
958 }
959
960 return 0;
961}
962
963static snd_pcm_sframes_t
964i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
965{
966 struct i2s_dai *i2s = to_info(dai);
967 u32 reg = readl(i2s->addr + I2SFIC);
968 snd_pcm_sframes_t delay;
a5a56871 969 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
1c7ac018 970
dc938ddb
MS		 971 WARN_ON(!pm_runtime_active(dai->dev));
972
1c7ac018
JB		 973 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
974 delay = FIC_RXCOUNT(reg);
975 else if (is_secondary(i2s))
976 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
977 else
a5a56871 978 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
1c7ac018
JB		 979
980 return delay;
981}
982
983#ifdef CONFIG_PM
984static int i2s_suspend(struct snd_soc_dai *dai)
985{
986 struct i2s_dai *i2s = to_info(dai);
987
d3d4e524
SN		 988 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
989 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
990 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1c7ac018
JB		 991
992 return 0;
993}
994
995static int i2s_resume(struct snd_soc_dai *dai)
996{
997 struct i2s_dai *i2s = to_info(dai);
998
d3d4e524
SN		 999 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
1000 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
1001 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1c7ac018
JB		 1002
1003 return 0;
1004}
1005#else
1006#define i2s_suspend NULL
1007#define i2s_resume NULL
1008#endif
1009
1010static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
1011{
1012 struct i2s_dai *i2s = to_info(dai);
dcd60fc3 1013 struct i2s_dai *other = get_other_dai(i2s);
ce8bcdbb 1014 unsigned long flags;
1c7ac018 1015
dc938ddb
MS		 1016 pm_runtime_get_sync(dai->dev);
1017
0ec2ba80 1018 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
69e7a69a 1019 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback,
3688569e 1020 NULL);
872c26bd 1021 } else {
69e7a69a 1022 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
872c26bd 1023 &i2s->dma_capture);
511e3033 1024
872c26bd
SN		 1025 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1026 writel(CON_RSTCLR, i2s->addr + I2SCON);
1c7ac018 1027
872c26bd
SN		 1028 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1029 idma_reg_addr_init(i2s->addr,
69e7a69a 1030 i2s->sec_dai->idma_playback.addr);
872c26bd 1031 }
61100f40 1032
1c7ac018
JB		 1033 /* Reset any constraint on RFS and BFS */
1034 i2s->rfs = 0;
1035 i2s->bfs = 0;
d66eac3e 1036 i2s->rclk_srcrate = 0;
ce8bcdbb
SN		 1037
1038 spin_lock_irqsave(i2s->lock, flags);
1c7ac018
JB		 1039 i2s_txctrl(i2s, 0);
1040 i2s_rxctrl(i2s, 0);
1041 i2s_fifo(i2s, FIC_TXFLUSH);
1042 i2s_fifo(other, FIC_TXFLUSH);
1043 i2s_fifo(i2s, FIC_RXFLUSH);
ce8bcdbb 1044 spin_unlock_irqrestore(i2s->lock, flags);
1c7ac018
JB		 1045
1046 /* Gate CDCLK by default */
1047 if (!is_opened(other))
1048 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1049 0, SND_SOC_CLOCK_IN);
dc938ddb 1050 pm_runtime_put(dai->dev);
1c7ac018
JB		 1051
1052 return 0;
1053}
1054
1055static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1056{
1057 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
5faf071d 1058 unsigned long flags;
1c7ac018 1059
dc938ddb
MS		 1060 pm_runtime_get_sync(dai->dev);
1061
c92f1d0e 1062 if (!is_secondary(i2s)) {
ce8bcdbb 1063 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
5faf071d 1064 spin_lock_irqsave(i2s->lock, flags);
1c7ac018 1065 writel(0, i2s->addr + I2SCON);
5faf071d 1066 spin_unlock_irqrestore(i2s->lock, flags);
ce8bcdbb 1067 }
1c7ac018
JB		 1068 }
1069
dc938ddb
MS		 1070 pm_runtime_put(dai->dev);
1071
1c7ac018
JB		 1072 return 0;
1073}
1074
85e7652d 1075static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1c7ac018
JB		 1076 .trigger = i2s_trigger,
1077 .hw_params = i2s_hw_params,
1078 .set_fmt = i2s_set_fmt,
1079 .set_clkdiv = i2s_set_clkdiv,
1080 .set_sysclk = i2s_set_sysclk,
1081 .startup = i2s_startup,
1082 .shutdown = i2s_shutdown,
1083 .delay = i2s_delay,
1084};
1085
4b828535
KM		 1086static const struct snd_soc_component_driver samsung_i2s_component = {
1087 .name = "samsung-i2s",
1088};
1089
1c7ac018
JB		 1090#define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1091
1092#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1093 SNDRV_PCM_FMTBIT_S16_LE | \
1094 SNDRV_PCM_FMTBIT_S24_LE)
1095
fdca21ad 1096static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1c7ac018
JB		 1097{
1098 struct i2s_dai *i2s;
1099
b960ce74 1100 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1c7ac018
JB		 1101 if (i2s == NULL)
1102 return NULL;
1103
1104 i2s->pdev = pdev;
1105 i2s->pri_dai = NULL;
1106 i2s->sec_dai = NULL;
1107 i2s->i2s_dai_drv.symmetric_rates = 1;
1108 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1109 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1110 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1111 i2s->i2s_dai_drv.suspend = i2s_suspend;
1112 i2s->i2s_dai_drv.resume = i2s_resume;
a0ff6ea2 1113 i2s->i2s_dai_drv.playback.channels_min = 1;
1c7ac018
JB		 1114 i2s->i2s_dai_drv.playback.channels_max = 2;
1115 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1116 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1117
1118 if (!sec) {
588fb705 1119 i2s->i2s_dai_drv.capture.channels_min = 1;
1c7ac018
JB		 1120 i2s->i2s_dai_drv.capture.channels_max = 2;
1121 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1122 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
c6f9b1eb 1123 }
1c7ac018
JB		 1124 return i2s;
1125}
1126
641d334b 1127#ifdef CONFIG_PM
5b1d3c34
C		 1128static int i2s_runtime_suspend(struct device *dev)
1129{
1130 struct i2s_dai *i2s = dev_get_drvdata(dev);
1131
1132 clk_disable_unprepare(i2s->clk);
1133
1134 return 0;
1135}
1136
1137static int i2s_runtime_resume(struct device *dev)
1138{
1139 struct i2s_dai *i2s = dev_get_drvdata(dev);
1140
1141 clk_prepare_enable(i2s->clk);
1142
1143 return 0;
1144}
641d334b 1145#endif /* CONFIG_PM */
5b1d3c34 1146
074b89bb
SN		 1147static void i2s_unregister_clocks(struct i2s_dai *i2s)
1148{
1149 int i;
1150
1151 for (i = 0; i < i2s->clk_data.clk_num; i++) {
1152 if (!IS_ERR(i2s->clk_table[i]))
1153 clk_unregister(i2s->clk_table[i]);
1154 }
1155}
1156
1157static void i2s_unregister_clock_provider(struct platform_device *pdev)
1158{
1159 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev);
1160
1161 of_clk_del_provider(pdev->dev.of_node);
1162 i2s_unregister_clocks(i2s);
1163}
1164
1165static int i2s_register_clock_provider(struct platform_device *pdev)
1166{
1167 struct device *dev = &pdev->dev;
1168 struct i2s_dai *i2s = dev_get_drvdata(dev);
1169 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
1170 const char *p_names[2] = { NULL };
1171 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs;
1172 struct clk *rclksrc;
1173 int ret, i;
1174
1175 /* Register the clock provider only if it's expected in the DTB */
1176 if (!of_find_property(dev->of_node, "#clock-cells", NULL))
1177 return 0;
1178
1179 /* Get the RCLKSRC mux clock parent clock names */
1180 for (i = 0; i < ARRAY_SIZE(p_names); i++) {
1181 rclksrc = clk_get(dev, clk_name[i]);
1182 if (IS_ERR(rclksrc))
1183 continue;
1184 p_names[i] = __clk_get_name(rclksrc);
1185 clk_put(rclksrc);
1186 }
1187
1188 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1189 /* Activate the prescaler */
1190 u32 val = readl(i2s->addr + I2SPSR);
1191 writel(val | PSR_PSREN, i2s->addr + I2SPSR);
1192
1193 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL,
1194 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
1195 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
1196 i2s->addr + I2SMOD, reg_info->rclksrc_off,
1197 1, 0, i2s->lock);
1198
1199 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL,
1200 "i2s_presc", "i2s_rclksrc",
1201 CLK_SET_RATE_PARENT,
1202 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
1203
1204 p_names[0] = "i2s_presc";
1205 i2s->clk_data.clk_num = 2;
1206 }
1207 of_property_read_string_index(dev->of_node,
1208 "clock-output-names", 0, &clk_name[0]);
1209
1210 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0],
1211 p_names[0], CLK_SET_RATE_PARENT,
1212 i2s->addr + I2SMOD, reg_info->cdclkcon_off,
1213 CLK_GATE_SET_TO_DISABLE, i2s->lock);
1214
1215 i2s->clk_data.clk_num += 1;
1216 i2s->clk_data.clks = i2s->clk_table;
1217
1218 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1219 &i2s->clk_data);
1220 if (ret < 0) {
1221 dev_err(dev, "failed to add clock provider: %d\n", ret);
1222 i2s_unregister_clocks(i2s);
1223 }
1224
1225 return ret;
1226}
1227
fdca21ad 1228static int samsung_i2s_probe(struct platform_device *pdev)
1c7ac018 1229{
1c7ac018 1230 struct i2s_dai *pri_dai, *sec_dai = NULL;
40476f61 1231 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1c7ac018 1232 struct resource *res;
40476f61
PV		 1233 u32 regs_base, quirks = 0, idma_addr = 0;
1234 struct device_node *np = pdev->dev.of_node;
7da493e9 1235 const struct samsung_i2s_dai_data *i2s_dai_data;
c92f1d0e 1236 int ret;
1c7ac018 1237
2f7b5d14
SN		 1238 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
1239 i2s_dai_data = of_device_get_match_data(&pdev->dev);
1240 else
1241 i2s_dai_data = (struct samsung_i2s_dai_data *)
1242 platform_get_device_id(pdev)->driver_data;
7c62eebb 1243
1c7ac018 1244
40476f61
PV		 1245 pri_dai = i2s_alloc_dai(pdev, false);
1246 if (!pri_dai) {
1247 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1248 return -ENOMEM;
1c7ac018
JB		 1249 }
1250
f3670536
SN		 1251 spin_lock_init(&pri_dai->spinlock);
1252 pri_dai->lock = &pri_dai->spinlock;
1253
40476f61 1254 if (!np) {
40476f61
PV		 1255 if (i2s_pdata == NULL) {
1256 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1257 return -EINVAL;
1258 }
1259
69e7a69a
SN		 1260 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
1261 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
9bdca822 1262 pri_dai->filter = i2s_pdata->dma_filter;
b9a1a743 1263
409c69be
KK		 1264 quirks = i2s_pdata->type.quirks;
1265 idma_addr = i2s_pdata->type.idma_addr;
40476f61 1266 } else {
7da493e9 1267 quirks = i2s_dai_data->quirks;
40476f61
PV		 1268 if (of_property_read_u32(np, "samsung,idma-addr",
1269 &idma_addr)) {
b0759736
PV		 1270 if (quirks & QUIRK_SUPPORTS_IDMA) {
1271 dev_info(&pdev->dev, "idma address is not"\
40476f61 1272 "specified");
40476f61
PV		 1273 }
1274 }
1275 }
1c7ac018
JB		 1276
1277 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
af1cf5cf
SN		 1278 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1279 if (IS_ERR(pri_dai->addr))
1280 return PTR_ERR(pri_dai->addr);
1c7ac018 1281
1c7ac018
JB		 1282 regs_base = res->start;
1283
0ec2ba80
SN		 1284 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1285 if (IS_ERR(pri_dai->clk)) {
1286 dev_err(&pdev->dev, "Failed to get iis clock\n");
1287 return PTR_ERR(pri_dai->clk);
1288 }
c92f1d0e
SN		 1289
1290 ret = clk_prepare_enable(pri_dai->clk);
1291 if (ret != 0) {
1292 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1293 return ret;
1294 }
69e7a69a
SN		 1295 pri_dai->dma_playback.addr = regs_base + I2STXD;
1296 pri_dai->dma_capture.addr = regs_base + I2SRXD;
69e7a69a
SN		 1297 pri_dai->dma_playback.addr_width = 4;
1298 pri_dai->dma_capture.addr_width = 4;
1c7ac018 1299 pri_dai->quirks = quirks;
a5a56871 1300 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1c7ac018
JB		 1301
1302 if (quirks & QUIRK_PRI_6CHAN)
1303 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1304
73f5dfc6
MS		 1305 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
1306 NULL, NULL);
1307 if (ret < 0)
1308 goto err_disable_clk;
1309
be2c92eb
MS		 1310 ret = devm_snd_soc_register_component(&pdev->dev,
1311 &samsung_i2s_component,
1312 &pri_dai->i2s_dai_drv, 1);
1313 if (ret < 0)
1314 goto err_disable_clk;
1315
1c7ac018
JB		 1316 if (quirks & QUIRK_SEC_DAI) {
1317 sec_dai = i2s_alloc_dai(pdev, true);
1318 if (!sec_dai) {
1319 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
fd61576f
WY		 1320 ret = -ENOMEM;
1321 goto err_disable_clk;
1c7ac018 1322 }
7e5d8706 1323
f3670536 1324 sec_dai->lock = &pri_dai->spinlock;
7e5d8706 1325 sec_dai->variant_regs = pri_dai->variant_regs;
69e7a69a 1326 sec_dai->dma_playback.addr = regs_base + I2STXDS;
40476f61 1327
9bdca822 1328 if (!np) {
69e7a69a 1329 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
9bdca822
AB		 1330 sec_dai->filter = i2s_pdata->dma_filter;
1331 }
40476f61 1332
69e7a69a 1333 sec_dai->dma_playback.addr_width = 4;
af1cf5cf 1334 sec_dai->addr = pri_dai->addr;
0ec2ba80 1335 sec_dai->clk = pri_dai->clk;
1c7ac018 1336 sec_dai->quirks = quirks;
69e7a69a 1337 sec_dai->idma_playback.addr = idma_addr;
1c7ac018
JB		 1338 sec_dai->pri_dai = pri_dai;
1339 pri_dai->sec_dai = sec_dai;
be2c92eb
MS		 1340
1341 ret = samsung_asoc_dma_platform_register(&pdev->dev,
1342 sec_dai->filter, "tx-sec", NULL);
1343 if (ret < 0)
1344 goto err_disable_clk;
1345
1346 ret = devm_snd_soc_register_component(&pdev->dev,
1347 &samsung_i2s_component,
1348 &sec_dai->i2s_dai_drv, 1);
1349 if (ret < 0)
1350 goto err_disable_clk;
1c7ac018
JB		 1351 }
1352
0429ffef
MB		 1353 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1354 dev_err(&pdev->dev, "Unable to configure gpio\n");
fd61576f
WY		 1355 ret = -EINVAL;
1356 goto err_disable_clk;
1c7ac018
JB		 1357 }
1358
be2c92eb 1359 dev_set_drvdata(&pdev->dev, pri_dai);
2b960386 1360
dc938ddb 1361 pm_runtime_set_active(&pdev->dev);
c5cf4dbc
MB		 1362 pm_runtime_enable(&pdev->dev);
1363
2b960386
SN		 1364 ret = i2s_register_clock_provider(pdev);
1365 if (!ret)
1366 return 0;
a08485d8 1367
2b960386 1368 pm_runtime_disable(&pdev->dev);
fd61576f
WY		 1369err_disable_clk:
1370 clk_disable_unprepare(pri_dai->clk);
2b960386 1371 return ret;
1c7ac018
JB		 1372}
1373
fdca21ad 1374static int samsung_i2s_remove(struct platform_device *pdev)
1c7ac018 1375{
be2c92eb 1376 struct i2s_dai *pri_dai, *sec_dai;
1c7ac018 1377
be2c92eb
MS		 1378 pri_dai = dev_get_drvdata(&pdev->dev);
1379 sec_dai = pri_dai->sec_dai;
1c7ac018 1380
be2c92eb
MS		 1381 pri_dai->sec_dai = NULL;
1382 sec_dai->pri_dai = NULL;
1c7ac018 1383
dc938ddb 1384 pm_runtime_get_sync(&pdev->dev);
be2c92eb 1385 pm_runtime_disable(&pdev->dev);
c92f1d0e 1386
be2c92eb
MS		 1387 i2s_unregister_clock_provider(pdev);
1388 clk_disable_unprepare(pri_dai->clk);
dc938ddb 1389 pm_runtime_put_noidle(&pdev->dev);
1c7ac018 1390
1c7ac018
JB		 1391 return 0;
1392}
1393
a5a56871
PV		 1394static const struct samsung_i2s_variant_regs i2sv3_regs = {
1395 .bfs_off = 1,
1396 .rfs_off = 3,
1397 .sdf_off = 5,
1398 .txr_off = 8,
1399 .rclksrc_off = 10,
1400 .mss_off = 11,
1401 .cdclkcon_off = 12,
1402 .lrp_off = 7,
1403 .bfs_mask = 0x3,
1404 .rfs_mask = 0x3,
1405 .ftx0cnt_off = 8,
1406};
1407
1408static const struct samsung_i2s_variant_regs i2sv6_regs = {
1409 .bfs_off = 0,
1410 .rfs_off = 4,
1411 .sdf_off = 6,
1412 .txr_off = 8,
1413 .rclksrc_off = 10,
1414 .mss_off = 11,
1415 .cdclkcon_off = 12,
1416 .lrp_off = 15,
1417 .bfs_mask = 0xf,
1418 .rfs_mask = 0x3,
1419 .ftx0cnt_off = 8,
1420};
1421
1422static const struct samsung_i2s_variant_regs i2sv7_regs = {
1423 .bfs_off = 0,
1424 .rfs_off = 4,
1425 .sdf_off = 7,
1426 .txr_off = 9,
1427 .rclksrc_off = 11,
1428 .mss_off = 12,
1429 .cdclkcon_off = 22,
1430 .lrp_off = 15,
1431 .bfs_mask = 0xf,
1432 .rfs_mask = 0x7,
1433 .ftx0cnt_off = 0,
1434};
1435
1436static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1437 .bfs_off = 0,
1438 .rfs_off = 3,
1439 .sdf_off = 6,
1440 .txr_off = 8,
1441 .rclksrc_off = 10,
1442 .mss_off = 11,
1443 .cdclkcon_off = 12,
1444 .lrp_off = 15,
1445 .bfs_mask = 0x7,
1446 .rfs_mask = 0x7,
1447 .ftx0cnt_off = 8,
1448};
1449
7da493e9 1450static const struct samsung_i2s_dai_data i2sv3_dai_type = {
7da493e9 1451 .quirks = QUIRK_NO_MUXPSR,
a5a56871 1452 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1453};
1454
1455static const struct samsung_i2s_dai_data i2sv5_dai_type = {
b0759736
PV		 1456 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1457 QUIRK_SUPPORTS_IDMA,
a5a56871 1458 .i2s_variant_regs = &i2sv3_regs,
7da493e9
PV		 1459};
1460
4ca0c0d4 1461static const struct samsung_i2s_dai_data i2sv6_dai_type = {
4ca0c0d4 1462 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
b0759736 1463 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
a5a56871
PV		 1464 .i2s_variant_regs = &i2sv6_regs,
1465};
1466
1467static const struct samsung_i2s_dai_data i2sv7_dai_type = {
a5a56871
PV		 1468 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1469 QUIRK_SUPPORTS_TDM,
1470 .i2s_variant_regs = &i2sv7_regs,
1471};
1472
1473static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
a5a56871
PV		 1474 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1475 .i2s_variant_regs = &i2sv5_i2s1_regs,
4ca0c0d4
PV		 1476};
1477
eb8ca0fa 1478static const struct platform_device_id samsung_i2s_driver_ids[] = {
7c62eebb
PV		 1479 {
1480 .name = "samsung-i2s",
3f024980 1481 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
7c62eebb
PV		 1482 },
1483 {},
1484};
2af19558 1485MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
7c62eebb 1486
40476f61 1487#ifdef CONFIG_OF
40476f61 1488static const struct of_device_id exynos_i2s_match[] = {
7da493e9
PV		 1489 {
1490 .compatible = "samsung,s3c6410-i2s",
1491 .data = &i2sv3_dai_type,
1492 }, {
1493 .compatible = "samsung,s5pv210-i2s",
1494 .data = &i2sv5_dai_type,
4ca0c0d4
PV		 1495 }, {
1496 .compatible = "samsung,exynos5420-i2s",
1497 .data = &i2sv6_dai_type,
a5a56871
PV		 1498 }, {
1499 .compatible = "samsung,exynos7-i2s",
1500 .data = &i2sv7_dai_type,
1501 }, {
1502 .compatible = "samsung,exynos7-i2s1",
1503 .data = &i2sv5_dai_type_i2s1,
40476f61
PV		 1504 },
1505 {},
1506};
1507MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1508#endif
1509
5b1d3c34
C		 1510static const struct dev_pm_ops samsung_i2s_pm = {
1511 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1512 i2s_runtime_resume, NULL)
1513};
1514
1c7ac018
JB		 1515static struct platform_driver samsung_i2s_driver = {
1516 .probe = samsung_i2s_probe,
fdca21ad 1517 .remove = samsung_i2s_remove,
7c62eebb 1518 .id_table = samsung_i2s_driver_ids,
1c7ac018
JB		 1519 .driver = {
1520 .name = "samsung-i2s",
40476f61 1521 .of_match_table = of_match_ptr(exynos_i2s_match),
5b1d3c34 1522 .pm = &samsung_i2s_pm,
1c7ac018
JB		 1523 },
1524};
1525
e00c3f55 1526module_platform_driver(samsung_i2s_driver);
1c7ac018
JB		 1527
1528/* Module information */
df8ad335 1529MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1c7ac018
JB		 1530MODULE_DESCRIPTION("Samsung I2S Interface");
1531MODULE_ALIAS("platform:samsung-i2s");
1532MODULE_LICENSE("GPL");
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