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Commit | Line | Data |
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dfc9403b KM |
1 | /* |
2 | * Helper routines for R-Car sound ADG. | |
3 | * | |
4 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
2a46db4a | 10 | #include <linux/clk-provider.h> |
dfc9403b KM |
11 | #include "rsnd.h" |
12 | ||
13 | #define CLKA 0 | |
14 | #define CLKB 1 | |
15 | #define CLKC 2 | |
16 | #define CLKI 3 | |
17 | #define CLKMAX 4 | |
18 | ||
2a46db4a KM |
19 | #define CLKOUT 0 |
20 | #define CLKOUT1 1 | |
21 | #define CLKOUT2 2 | |
22 | #define CLKOUT3 3 | |
23 | #define CLKOUTMAX 4 | |
24 | ||
eae6fff4 KM |
25 | #define BRRx_MASK(x) (0x3FF & x) |
26 | ||
1665a9e5 KM |
27 | static struct rsnd_mod_ops adg_ops = { |
28 | .name = "adg", | |
29 | }; | |
30 | ||
dfc9403b KM |
31 | struct rsnd_adg { |
32 | struct clk *clk[CLKMAX]; | |
2a46db4a KM |
33 | struct clk *clkout[CLKOUTMAX]; |
34 | struct clk_onecell_data onecell; | |
1665a9e5 | 35 | struct rsnd_mod mod; |
7dc20319 | 36 | u32 flags; |
b99258a3 KM |
37 | u32 ckr; |
38 | u32 rbga; | |
39 | u32 rbgb; | |
dfc9403b | 40 | |
eae6fff4 KM |
41 | int rbga_rate_for_441khz; /* RBGA */ |
42 | int rbgb_rate_for_48khz; /* RBGB */ | |
dfc9403b KM |
43 | }; |
44 | ||
7dc20319 | 45 | #define LRCLK_ASYNC (1 << 0) |
25165f79 | 46 | #define AUDIO_OUT_48 (1 << 1) |
7dc20319 | 47 | |
dfc9403b | 48 | #define for_each_rsnd_clk(pos, adg, i) \ |
00463c11 KM |
49 | for (i = 0; \ |
50 | (i < CLKMAX) && \ | |
51 | ((pos) = adg->clk[i]); \ | |
52 | i++) | |
2a46db4a KM |
53 | #define for_each_rsnd_clkout(pos, adg, i) \ |
54 | for (i = 0; \ | |
55 | (i < CLKOUTMAX) && \ | |
56 | ((pos) = adg->clkout[i]); \ | |
57 | i++) | |
dfc9403b KM |
58 | #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) |
59 | ||
6cba3fa9 KM |
60 | static const char * const clk_name[] = { |
61 | [CLKA] = "clk_a", | |
62 | [CLKB] = "clk_b", | |
63 | [CLKC] = "clk_c", | |
64 | [CLKI] = "clk_i", | |
65 | }; | |
66 | ||
eae6fff4 KM |
67 | static u32 rsnd_adg_calculate_rbgx(unsigned long div) |
68 | { | |
69 | int i, ratio; | |
70 | ||
71 | if (!div) | |
72 | return 0; | |
73 | ||
74 | for (i = 3; i >= 0; i--) { | |
75 | ratio = 2 << (i * 2); | |
76 | if (0 == (div % ratio)) | |
77 | return (u32)((i << 8) | ((div / ratio) - 1)); | |
78 | } | |
79 | ||
80 | return ~0; | |
81 | } | |
629509c5 | 82 | |
8467dedc | 83 | static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) |
629509c5 | 84 | { |
94458364 KM |
85 | struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); |
86 | int id = rsnd_mod_id(ssi_mod); | |
629509c5 KM |
87 | int ws = id; |
88 | ||
b415b4d3 | 89 | if (rsnd_ssi_is_pin_sharing(io)) { |
629509c5 KM |
90 | switch (id) { |
91 | case 1: | |
92 | case 2: | |
93 | ws = 0; | |
94 | break; | |
95 | case 4: | |
96 | ws = 3; | |
97 | break; | |
98 | case 8: | |
99 | ws = 7; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | return (0x6 + ws) << 8; | |
105 | } | |
106 | ||
0102eed5 KM |
107 | static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, |
108 | struct rsnd_dai_stream *io, | |
109 | unsigned int target_rate, | |
110 | unsigned int *target_val, | |
111 | unsigned int *target_en) | |
112 | { | |
113 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
114 | struct device *dev = rsnd_priv_to_dev(priv); | |
115 | int idx, sel, div, step; | |
116 | unsigned int val, en; | |
117 | unsigned int min, diff; | |
118 | unsigned int sel_rate[] = { | |
119 | clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ | |
120 | clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ | |
121 | clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ | |
122 | adg->rbga_rate_for_441khz, /* 0011: RBGA */ | |
123 | adg->rbgb_rate_for_48khz, /* 0100: RBGB */ | |
124 | }; | |
125 | ||
126 | min = ~0; | |
127 | val = 0; | |
128 | en = 0; | |
129 | for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { | |
130 | idx = 0; | |
131 | step = 2; | |
132 | ||
133 | if (!sel_rate[sel]) | |
134 | continue; | |
135 | ||
136 | for (div = 2; div <= 98304; div += step) { | |
137 | diff = abs(target_rate - sel_rate[sel] / div); | |
138 | if (min > diff) { | |
139 | val = (sel << 8) | idx; | |
140 | min = diff; | |
141 | en = 1 << (sel + 1); /* fixme */ | |
142 | } | |
143 | ||
144 | /* | |
145 | * step of 0_0000 / 0_0001 / 0_1101 | |
146 | * are out of order | |
147 | */ | |
148 | if ((idx > 2) && (idx % 2)) | |
149 | step *= 2; | |
150 | if (idx == 0x1c) { | |
151 | div += step; | |
152 | step *= 2; | |
153 | } | |
154 | idx++; | |
155 | } | |
156 | } | |
157 | ||
158 | if (min == ~0) { | |
159 | dev_err(dev, "no Input clock\n"); | |
160 | return; | |
161 | } | |
162 | ||
163 | *target_val = val; | |
164 | if (target_en) | |
165 | *target_en = en; | |
166 | } | |
167 | ||
168 | static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, | |
169 | struct rsnd_dai_stream *io, | |
170 | unsigned int in_rate, | |
171 | unsigned int out_rate, | |
172 | u32 *in, u32 *out, u32 *en) | |
173 | { | |
174 | struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); | |
175 | unsigned int target_rate; | |
176 | u32 *target_val; | |
177 | u32 _in; | |
178 | u32 _out; | |
179 | u32 _en; | |
180 | ||
181 | /* default = SSI WS */ | |
182 | _in = | |
183 | _out = rsnd_adg_ssi_ws_timing_gen2(io); | |
184 | ||
185 | target_rate = 0; | |
186 | target_val = NULL; | |
187 | _en = 0; | |
188 | if (runtime->rate != in_rate) { | |
189 | target_rate = out_rate; | |
190 | target_val = &_out; | |
191 | } else if (runtime->rate != out_rate) { | |
192 | target_rate = in_rate; | |
193 | target_val = &_in; | |
194 | } | |
195 | ||
196 | if (target_rate) | |
197 | __rsnd_adg_get_timesel_ratio(priv, io, | |
198 | target_rate, | |
199 | target_val, &_en); | |
200 | ||
201 | if (in) | |
202 | *in = _in; | |
203 | if (out) | |
204 | *out = _out; | |
205 | if (en) | |
206 | *en = _en; | |
207 | } | |
208 | ||
94458364 | 209 | int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, |
bff58ea4 KM |
210 | struct rsnd_dai_stream *io) |
211 | { | |
94458364 | 212 | struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); |
1665a9e5 KM |
213 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
214 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
94458364 | 215 | int id = rsnd_mod_id(cmd_mod); |
bff58ea4 KM |
216 | int shift = (id % 2) ? 16 : 0; |
217 | u32 mask, val; | |
218 | ||
09e59075 KM |
219 | rsnd_adg_get_timesel_ratio(priv, io, |
220 | rsnd_src_get_in_rate(priv, io), | |
221 | rsnd_src_get_out_rate(priv, io), | |
222 | NULL, &val, NULL); | |
bff58ea4 KM |
223 | |
224 | val = val << shift; | |
d5aa2482 | 225 | mask = 0x0f1f << shift; |
bff58ea4 | 226 | |
1665a9e5 | 227 | rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); |
bff58ea4 KM |
228 | |
229 | return 0; | |
230 | } | |
231 | ||
0102eed5 KM |
232 | int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, |
233 | struct rsnd_dai_stream *io, | |
234 | unsigned int in_rate, | |
235 | unsigned int out_rate) | |
629509c5 | 236 | { |
f1df1229 | 237 | struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); |
1665a9e5 KM |
238 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
239 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
0102eed5 KM |
240 | u32 in, out; |
241 | u32 mask, en; | |
f1df1229 | 242 | int id = rsnd_mod_id(src_mod); |
629509c5 | 243 | int shift = (id % 2) ? 16 : 0; |
629509c5 | 244 | |
f1df1229 KM |
245 | rsnd_mod_confirm_src(src_mod); |
246 | ||
0102eed5 KM |
247 | rsnd_adg_get_timesel_ratio(priv, io, |
248 | in_rate, out_rate, | |
249 | &in, &out, &en); | |
629509c5 KM |
250 | |
251 | in = in << shift; | |
252 | out = out << shift; | |
d5aa2482 | 253 | mask = 0x0f1f << shift; |
629509c5 KM |
254 | |
255 | switch (id / 2) { | |
256 | case 0: | |
1665a9e5 KM |
257 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in); |
258 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out); | |
629509c5 KM |
259 | break; |
260 | case 1: | |
1665a9e5 KM |
261 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in); |
262 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out); | |
629509c5 KM |
263 | break; |
264 | case 2: | |
1665a9e5 KM |
265 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in); |
266 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out); | |
629509c5 KM |
267 | break; |
268 | case 3: | |
1665a9e5 KM |
269 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in); |
270 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out); | |
629509c5 KM |
271 | break; |
272 | case 4: | |
1665a9e5 KM |
273 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in); |
274 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out); | |
629509c5 KM |
275 | break; |
276 | } | |
277 | ||
0102eed5 KM |
278 | if (en) |
279 | rsnd_mod_bset(adg_mod, DIV_EN, en, en); | |
d2c4b80c | 280 | |
ee2c828d | 281 | return 0; |
629509c5 KM |
282 | } |
283 | ||
f1df1229 | 284 | static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) |
dfc9403b | 285 | { |
f1df1229 | 286 | struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); |
1665a9e5 KM |
287 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
288 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
6cba3fa9 | 289 | struct device *dev = rsnd_priv_to_dev(priv); |
f1df1229 | 290 | int id = rsnd_mod_id(ssi_mod); |
e337853e KM |
291 | int shift = (id % 4) * 8; |
292 | u32 mask = 0xFF << shift; | |
293 | ||
f1df1229 KM |
294 | rsnd_mod_confirm_ssi(ssi_mod); |
295 | ||
e337853e | 296 | val = val << shift; |
dfc9403b KM |
297 | |
298 | /* | |
299 | * SSI 8 is not connected to ADG. | |
300 | * it works with SSI 7 | |
301 | */ | |
302 | if (id == 8) | |
e337853e KM |
303 | return; |
304 | ||
305 | switch (id / 4) { | |
306 | case 0: | |
1665a9e5 | 307 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val); |
e337853e KM |
308 | break; |
309 | case 1: | |
1665a9e5 | 310 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val); |
e337853e KM |
311 | break; |
312 | case 2: | |
1665a9e5 | 313 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val); |
e337853e KM |
314 | break; |
315 | } | |
6cba3fa9 KM |
316 | |
317 | dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); | |
dfc9403b KM |
318 | } |
319 | ||
1dfdc650 | 320 | int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) |
dfc9403b | 321 | { |
dfc9403b | 322 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
dfc9403b | 323 | struct clk *clk; |
e337853e | 324 | int i; |
dfc9403b KM |
325 | int sel_table[] = { |
326 | [CLKA] = 0x1, | |
327 | [CLKB] = 0x2, | |
328 | [CLKC] = 0x3, | |
329 | [CLKI] = 0x0, | |
330 | }; | |
331 | ||
dfc9403b KM |
332 | /* |
333 | * find suitable clock from | |
334 | * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. | |
335 | */ | |
dfc9403b | 336 | for_each_rsnd_clk(clk, adg, i) { |
1dfdc650 KM |
337 | if (rate == clk_get_rate(clk)) |
338 | return sel_table[i]; | |
dfc9403b KM |
339 | } |
340 | ||
341 | /* | |
eae6fff4 | 342 | * find divided clock from BRGA/BRGB |
dfc9403b | 343 | */ |
1dfdc650 KM |
344 | if (rate == adg->rbga_rate_for_441khz) |
345 | return 0x10; | |
dfc9403b | 346 | |
1dfdc650 KM |
347 | if (rate == adg->rbgb_rate_for_48khz) |
348 | return 0x20; | |
dfc9403b KM |
349 | |
350 | return -EIO; | |
1dfdc650 KM |
351 | } |
352 | ||
353 | int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) | |
354 | { | |
355 | rsnd_adg_set_ssi_clk(ssi_mod, 0); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) | |
361 | { | |
362 | struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); | |
363 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
364 | struct device *dev = rsnd_priv_to_dev(priv); | |
365 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
366 | int data; | |
367 | u32 ckr = 0; | |
dfc9403b | 368 | |
1dfdc650 KM |
369 | data = rsnd_adg_clk_query(priv, rate); |
370 | if (data < 0) | |
371 | return data; | |
dfc9403b | 372 | |
94458364 | 373 | rsnd_adg_set_ssi_clk(ssi_mod, data); |
dfc9403b | 374 | |
d0cf7fc9 KM |
375 | if (rsnd_flags_has(adg, LRCLK_ASYNC)) { |
376 | if (rsnd_flags_has(adg, AUDIO_OUT_48)) | |
25165f79 KM |
377 | ckr = 0x80000000; |
378 | } else { | |
7dc20319 KM |
379 | if (0 == (rate % 8000)) |
380 | ckr = 0x80000000; | |
7dc20319 KM |
381 | } |
382 | ||
d5aa2482 | 383 | rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); |
b99258a3 KM |
384 | rsnd_mod_write(adg_mod, BRRA, adg->rbga); |
385 | rsnd_mod_write(adg_mod, BRRB, adg->rbgb); | |
386 | ||
6cba3fa9 KM |
387 | dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", |
388 | (ckr) ? 'B' : 'A', | |
389 | (ckr) ? adg->rbgb_rate_for_48khz : | |
390 | adg->rbga_rate_for_441khz); | |
dfc9403b KM |
391 | |
392 | return 0; | |
393 | } | |
394 | ||
c2d31718 KM |
395 | void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) |
396 | { | |
397 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
398 | struct device *dev = rsnd_priv_to_dev(priv); | |
399 | struct clk *clk; | |
400 | int i, ret; | |
401 | ||
402 | for_each_rsnd_clk(clk, adg, i) { | |
403 | ret = 0; | |
404 | if (enable) | |
405 | ret = clk_prepare_enable(clk); | |
406 | else | |
407 | clk_disable_unprepare(clk); | |
408 | ||
409 | if (ret < 0) | |
410 | dev_warn(dev, "can't use clk %d\n", i); | |
411 | } | |
412 | } | |
413 | ||
248e88c2 KM |
414 | static void rsnd_adg_get_clkin(struct rsnd_priv *priv, |
415 | struct rsnd_adg *adg) | |
416 | { | |
417 | struct device *dev = rsnd_priv_to_dev(priv); | |
418 | struct clk *clk; | |
c2d31718 | 419 | int i; |
248e88c2 KM |
420 | |
421 | for (i = 0; i < CLKMAX; i++) { | |
422 | clk = devm_clk_get(dev, clk_name[i]); | |
423 | adg->clk[i] = IS_ERR(clk) ? NULL : clk; | |
424 | } | |
248e88c2 KM |
425 | } |
426 | ||
2a46db4a KM |
427 | static void rsnd_adg_get_clkout(struct rsnd_priv *priv, |
428 | struct rsnd_adg *adg) | |
dfc9403b KM |
429 | { |
430 | struct clk *clk; | |
eae6fff4 | 431 | struct device *dev = rsnd_priv_to_dev(priv); |
2a46db4a | 432 | struct device_node *np = dev->of_node; |
25165f79 | 433 | struct property *prop; |
eae6fff4 | 434 | u32 ckr, rbgx, rbga, rbgb; |
25165f79 KM |
435 | u32 rate, div; |
436 | #define REQ_SIZE 2 | |
437 | u32 req_rate[REQ_SIZE] = {}; | |
2a46db4a KM |
438 | uint32_t count = 0; |
439 | unsigned long req_48kHz_rate, req_441kHz_rate; | |
25165f79 | 440 | int i, req_size; |
2a46db4a KM |
441 | const char *parent_clk_name = NULL; |
442 | static const char * const clkout_name[] = { | |
443 | [CLKOUT] = "audio_clkout", | |
444 | [CLKOUT1] = "audio_clkout1", | |
445 | [CLKOUT2] = "audio_clkout2", | |
446 | [CLKOUT3] = "audio_clkout3", | |
447 | }; | |
dfc9403b KM |
448 | int brg_table[] = { |
449 | [CLKA] = 0x0, | |
450 | [CLKB] = 0x1, | |
451 | [CLKC] = 0x4, | |
452 | [CLKI] = 0x2, | |
453 | }; | |
454 | ||
e8dffe6c MV |
455 | ckr = 0; |
456 | rbga = 2; /* default 1/6 */ | |
457 | rbgb = 2; /* default 1/6 */ | |
2a46db4a KM |
458 | |
459 | /* | |
460 | * ADG supports BRRA/BRRB output only | |
461 | * this means all clkout0/1/2/3 will be same rate | |
462 | */ | |
75f9e4ad | 463 | prop = of_find_property(np, "clock-frequency", NULL); |
e8dffe6c MV |
464 | if (!prop) |
465 | goto rsnd_adg_get_clkout_end; | |
466 | ||
25165f79 KM |
467 | req_size = prop->length / sizeof(u32); |
468 | ||
469 | of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); | |
2a46db4a KM |
470 | req_48kHz_rate = 0; |
471 | req_441kHz_rate = 0; | |
25165f79 KM |
472 | for (i = 0; i < req_size; i++) { |
473 | if (0 == (req_rate[i] % 44100)) | |
474 | req_441kHz_rate = req_rate[i]; | |
475 | if (0 == (req_rate[i] % 48000)) | |
476 | req_48kHz_rate = req_rate[i]; | |
477 | } | |
2a46db4a | 478 | |
e8dffe6c | 479 | if (req_rate[0] % 48000 == 0) |
d0cf7fc9 | 480 | rsnd_flags_set(adg, AUDIO_OUT_48); |
e8dffe6c | 481 | |
9654f5eb | 482 | if (of_get_property(np, "clkout-lr-asynchronous", NULL)) |
d0cf7fc9 | 483 | rsnd_flags_set(adg, LRCLK_ASYNC); |
9654f5eb | 484 | |
dfc9403b KM |
485 | /* |
486 | * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC | |
487 | * have 44.1kHz or 48kHz base clocks for now. | |
488 | * | |
489 | * SSI itself can divide parent clock by 1/1 - 1/16 | |
dfc9403b KM |
490 | * see |
491 | * rsnd_adg_ssi_clk_try_start() | |
5c6901d9 | 492 | * rsnd_ssi_master_clk_start() |
dfc9403b | 493 | */ |
eae6fff4 KM |
494 | adg->rbga_rate_for_441khz = 0; |
495 | adg->rbgb_rate_for_48khz = 0; | |
dfc9403b KM |
496 | for_each_rsnd_clk(clk, adg, i) { |
497 | rate = clk_get_rate(clk); | |
498 | ||
499 | if (0 == rate) /* not used */ | |
500 | continue; | |
501 | ||
502 | /* RBGA */ | |
eae6fff4 KM |
503 | if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { |
504 | div = 6; | |
2a46db4a KM |
505 | if (req_441kHz_rate) |
506 | div = rate / req_441kHz_rate; | |
eae6fff4 KM |
507 | rbgx = rsnd_adg_calculate_rbgx(div); |
508 | if (BRRx_MASK(rbgx) == rbgx) { | |
509 | rbga = rbgx; | |
510 | adg->rbga_rate_for_441khz = rate / div; | |
511 | ckr |= brg_table[i] << 20; | |
e8a3ce11 | 512 | if (req_441kHz_rate && |
d0cf7fc9 | 513 | !rsnd_flags_has(adg, AUDIO_OUT_48)) |
2a46db4a | 514 | parent_clk_name = __clk_get_name(clk); |
eae6fff4 | 515 | } |
dfc9403b KM |
516 | } |
517 | ||
518 | /* RBGB */ | |
eae6fff4 KM |
519 | if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { |
520 | div = 6; | |
2a46db4a KM |
521 | if (req_48kHz_rate) |
522 | div = rate / req_48kHz_rate; | |
eae6fff4 KM |
523 | rbgx = rsnd_adg_calculate_rbgx(div); |
524 | if (BRRx_MASK(rbgx) == rbgx) { | |
525 | rbgb = rbgx; | |
526 | adg->rbgb_rate_for_48khz = rate / div; | |
527 | ckr |= brg_table[i] << 16; | |
e8a3ce11 | 528 | if (req_48kHz_rate && |
d0cf7fc9 | 529 | rsnd_flags_has(adg, AUDIO_OUT_48)) |
2a46db4a | 530 | parent_clk_name = __clk_get_name(clk); |
2a46db4a KM |
531 | } |
532 | } | |
533 | } | |
534 | ||
535 | /* | |
536 | * ADG supports BRRA/BRRB output only. | |
537 | * this means all clkout0/1/2/3 will be * same rate | |
538 | */ | |
539 | ||
e8dffe6c | 540 | of_property_read_u32(np, "#clock-cells", &count); |
2a46db4a KM |
541 | /* |
542 | * for clkout | |
543 | */ | |
544 | if (!count) { | |
462c30bc | 545 | clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], |
25165f79 | 546 | parent_clk_name, 0, req_rate[0]); |
2a46db4a KM |
547 | if (!IS_ERR(clk)) { |
548 | adg->clkout[CLKOUT] = clk; | |
549 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
550 | } | |
551 | } | |
552 | /* | |
553 | * for clkout0/1/2/3 | |
554 | */ | |
555 | else { | |
556 | for (i = 0; i < CLKOUTMAX; i++) { | |
557 | clk = clk_register_fixed_rate(dev, clkout_name[i], | |
2ebdf684 | 558 | parent_clk_name, 0, |
25165f79 | 559 | req_rate[0]); |
d7f29819 | 560 | if (!IS_ERR(clk)) |
2a46db4a | 561 | adg->clkout[i] = clk; |
dfc9403b | 562 | } |
d7f29819 KM |
563 | adg->onecell.clks = adg->clkout; |
564 | adg->onecell.clk_num = CLKOUTMAX; | |
565 | of_clk_add_provider(np, of_clk_src_onecell_get, | |
566 | &adg->onecell); | |
dfc9403b KM |
567 | } |
568 | ||
e8dffe6c | 569 | rsnd_adg_get_clkout_end: |
b99258a3 KM |
570 | adg->ckr = ckr; |
571 | adg->rbga = rbga; | |
572 | adg->rbgb = rbgb; | |
6cba3fa9 KM |
573 | } |
574 | ||
575 | #ifdef DEBUG | |
576 | static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg) | |
577 | { | |
578 | struct device *dev = rsnd_priv_to_dev(priv); | |
579 | struct clk *clk; | |
580 | int i; | |
581 | ||
582 | for_each_rsnd_clk(clk, adg, i) | |
583 | dev_dbg(dev, "%s : %p : %ld\n", | |
584 | clk_name[i], clk, clk_get_rate(clk)); | |
eae6fff4 | 585 | |
3e58690b | 586 | dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", |
6cba3fa9 KM |
587 | adg->ckr, adg->rbga, adg->rbgb); |
588 | dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz); | |
589 | dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz); | |
590 | ||
591 | /* | |
592 | * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() | |
593 | * by BRGCKR::BRGCKR_31 | |
594 | */ | |
595 | for_each_rsnd_clkout(clk, adg, i) | |
596 | dev_dbg(dev, "clkout %d : %p : %ld\n", i, | |
597 | clk, clk_get_rate(clk)); | |
dfc9403b | 598 | } |
6cba3fa9 KM |
599 | #else |
600 | #define rsnd_adg_clk_dbg_info(priv, adg) | |
601 | #endif | |
dfc9403b | 602 | |
2ea6b074 | 603 | int rsnd_adg_probe(struct rsnd_priv *priv) |
dfc9403b KM |
604 | { |
605 | struct rsnd_adg *adg; | |
606 | struct device *dev = rsnd_priv_to_dev(priv); | |
56d2c61d | 607 | int ret; |
dfc9403b KM |
608 | |
609 | adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); | |
0d7820d0 | 610 | if (!adg) |
dfc9403b | 611 | return -ENOMEM; |
dfc9403b | 612 | |
56d2c61d | 613 | ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, |
5ba17b42 | 614 | NULL, NULL, 0, 0); |
56d2c61d WS |
615 | if (ret) |
616 | return ret; | |
1665a9e5 | 617 | |
248e88c2 | 618 | rsnd_adg_get_clkin(priv, adg); |
2a46db4a | 619 | rsnd_adg_get_clkout(priv, adg); |
6cba3fa9 | 620 | rsnd_adg_clk_dbg_info(priv, adg); |
dfc9403b KM |
621 | |
622 | priv->adg = adg; | |
623 | ||
c2d31718 KM |
624 | rsnd_adg_clk_enable(priv); |
625 | ||
dfc9403b KM |
626 | return 0; |
627 | } | |
68a55024 | 628 | |
2ea6b074 | 629 | void rsnd_adg_remove(struct rsnd_priv *priv) |
68a55024 | 630 | { |
b5aac5a9 KM |
631 | struct device *dev = rsnd_priv_to_dev(priv); |
632 | struct device_node *np = dev->of_node; | |
e3c6de48 KM |
633 | struct rsnd_adg *adg = priv->adg; |
634 | struct clk *clk; | |
635 | int i; | |
636 | ||
637 | for_each_rsnd_clkout(clk, adg, i) | |
638 | if (adg->clkout[i]) | |
639 | clk_unregister_fixed_rate(adg->clkout[i]); | |
b5aac5a9 KM |
640 | |
641 | of_clk_del_provider(np); | |
642 | ||
c2d31718 | 643 | rsnd_adg_clk_disable(priv); |
68a55024 | 644 | } |