[mirror_ubuntu-artful-kernel.git] / sound / soc / sh / rcar / adg.c

/*
 * Helper routines for R-Car sound ADG.
 *
 *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/clk-provider.h>
#include "rsnd.h"

#define CLKA	0
#define CLKB	1
#define CLKC	2
#define CLKI	3
#define CLKMAX	4

#define CLKOUT	0
#define CLKOUT1	1
#define CLKOUT2	2
#define CLKOUT3	3
#define CLKOUTMAX 4

#define BRRx_MASK(x) (0x3FF & x)

static struct rsnd_mod_ops adg_ops = {
	.name = "adg",
};

struct rsnd_adg {
	struct clk *clk[CLKMAX];
	struct clk *clkout[CLKOUTMAX];
	struct clk_onecell_data onecell;
	struct rsnd_mod mod;
	u32 flags;
	u32 ckr;
	u32 rbga;
	u32 rbgb;

	int rbga_rate_for_441khz; /* RBGA */
	int rbgb_rate_for_48khz;  /* RBGB */
};

#define LRCLK_ASYNC	(1 << 0)
#define AUDIO_OUT_48	(1 << 1)
#define adg_mode_flags(adg)	(adg->flags)

#define for_each_rsnd_clk(pos, adg, i)		\
	for (i = 0;				\
	     (i < CLKMAX) &&			\
	     ((pos) = adg->clk[i]);		\
	     i++)
#define for_each_rsnd_clkout(pos, adg, i)	\
	for (i = 0;				\
	     (i < CLKOUTMAX) &&			\
	     ((pos) = adg->clkout[i]);	\
	     i++)
#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)

static u32 rsnd_adg_calculate_rbgx(unsigned long div)
{
	int i, ratio;

	if (!div)
		return 0;

	for (i = 3; i >= 0; i--) {
		ratio = 2 << (i * 2);
		if (0 == (div % ratio))
			return (u32)((i << 8) | ((div / ratio) - 1));
	}

	return ~0;
}

static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
{
	struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
	int id = rsnd_mod_id(ssi_mod);
	int ws = id;

	if (rsnd_ssi_is_pin_sharing(io)) {
		switch (id) {
		case 1:
		case 2:
			ws = 0;
			break;
		case 4:
			ws = 3;
			break;
		case 8:
			ws = 7;
			break;
		}
	}

	return (0x6 + ws) << 8;
}

static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
				       struct rsnd_dai_stream *io,
				       unsigned int target_rate,
				       unsigned int *target_val,
				       unsigned int *target_en)
{
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	int idx, sel, div, step;
	unsigned int val, en;
	unsigned int min, diff;
	unsigned int sel_rate[] = {
		clk_get_rate(adg->clk[CLKA]),	/* 0000: CLKA */
		clk_get_rate(adg->clk[CLKB]),	/* 0001: CLKB */
		clk_get_rate(adg->clk[CLKC]),	/* 0010: CLKC */
		adg->rbga_rate_for_441khz,	/* 0011: RBGA */
		adg->rbgb_rate_for_48khz,	/* 0100: RBGB */
	};

	min = ~0;
	val = 0;
	en = 0;
	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
		idx = 0;
		step = 2;

		if (!sel_rate[sel])
			continue;

		for (div = 2; div <= 98304; div += step) {
			diff = abs(target_rate - sel_rate[sel] / div);
			if (min > diff) {
				val = (sel << 8) | idx;
				min = diff;
				en = 1 << (sel + 1); /* fixme */
			}

			/*
			 * step of 0_0000 / 0_0001 / 0_1101
			 * are out of order
			 */
			if ((idx > 2) && (idx % 2))
				step *= 2;
			if (idx == 0x1c) {
				div += step;
				step *= 2;
			}
			idx++;
		}
	}

	if (min == ~0) {
		dev_err(dev, "no Input clock\n");
		return;
	}

	*target_val = val;
	if (target_en)
		*target_en = en;
}

static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
				       struct rsnd_dai_stream *io,
				       unsigned int in_rate,
				       unsigned int out_rate,
				       u32 *in, u32 *out, u32 *en)
{
	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
	unsigned int target_rate;
	u32 *target_val;
	u32 _in;
	u32 _out;
	u32 _en;

	/* default = SSI WS */
	_in =
	_out = rsnd_adg_ssi_ws_timing_gen2(io);

	target_rate = 0;
	target_val = NULL;
	_en = 0;
	if (runtime->rate != in_rate) {
		target_rate = out_rate;
		target_val  = &_out;
	} else if (runtime->rate != out_rate) {
		target_rate = in_rate;
		target_val  = &_in;
	}

	if (target_rate)
		__rsnd_adg_get_timesel_ratio(priv, io,
					     target_rate,
					     target_val, &_en);

	if (in)
		*in = _in;
	if (out)
		*out = _out;
	if (en)
		*en = _en;
}

int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
				 struct rsnd_dai_stream *io)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
	int id = rsnd_mod_id(cmd_mod);
	int shift = (id % 2) ? 16 : 0;
	u32 mask, val;

	rsnd_adg_get_timesel_ratio(priv, io,
				   rsnd_src_get_in_rate(priv, io),
				   rsnd_src_get_out_rate(priv, io),
				   NULL, &val, NULL);

	val  = val	<< shift;
	mask = 0xffff	<< shift;

	rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);

	return 0;
}

int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
				  struct rsnd_dai_stream *io,
				  unsigned int in_rate,
				  unsigned int out_rate)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
	u32 in, out;
	u32 mask, en;
	int id = rsnd_mod_id(src_mod);
	int shift = (id % 2) ? 16 : 0;

	rsnd_mod_confirm_src(src_mod);

	rsnd_adg_get_timesel_ratio(priv, io,
				   in_rate, out_rate,
				   &in, &out, &en);

	in   = in	<< shift;
	out  = out	<< shift;
	mask = 0xffff	<< shift;

	switch (id / 2) {
	case 0:
		rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
		rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
		break;
	case 1:
		rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
		rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
		break;
	case 2:
		rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
		rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
		break;
	case 3:
		rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
		rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
		break;
	case 4:
		rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
		rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
		break;
	}

	if (en)
		rsnd_mod_bset(adg_mod, DIV_EN, en, en);

	return 0;
}

static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
	int id = rsnd_mod_id(ssi_mod);
	int shift = (id % 4) * 8;
	u32 mask = 0xFF << shift;

	rsnd_mod_confirm_ssi(ssi_mod);

	val = val << shift;

	/*
	 * SSI 8 is not connected to ADG.
	 * it works with SSI 7
	 */
	if (id == 8)
		return;

	switch (id / 4) {
	case 0:
		rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
		break;
	case 1:
		rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
		break;
	case 2:
		rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
		break;
	}
}

int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
{
	rsnd_adg_set_ssi_clk(ssi_mod, 0);

	return 0;
}

int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
	struct clk *clk;
	int i;
	u32 data;
	u32 ckr = 0;
	int sel_table[] = {
		[CLKA] = 0x1,
		[CLKB] = 0x2,
		[CLKC] = 0x3,
		[CLKI] = 0x0,
	};

	dev_dbg(dev, "request clock = %d\n", rate);

	/*
	 * find suitable clock from
	 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
	 */
	data = 0;
	for_each_rsnd_clk(clk, adg, i) {
		if (rate == clk_get_rate(clk)) {
			data = sel_table[i];
			goto found_clock;
		}
	}

	/*
	 * find divided clock from BRGA/BRGB
	 */
	if (rate  == adg->rbga_rate_for_441khz) {
		data = 0x10;
		goto found_clock;
	}

	if (rate == adg->rbgb_rate_for_48khz) {
		data = 0x20;
		goto found_clock;
	}

	return -EIO;

found_clock:

	rsnd_adg_set_ssi_clk(ssi_mod, data);

	if (adg_mode_flags(adg) & LRCLK_ASYNC) {
		if (adg_mode_flags(adg) & AUDIO_OUT_48)
			ckr = 0x80000000;
	} else {
		if (0 == (rate % 8000))
			ckr = 0x80000000;
	}

	rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
	rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
	rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);

	dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
		rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
		data, rate);

	return 0;
}

void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
{
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	struct clk *clk;
	int i, ret;

	for_each_rsnd_clk(clk, adg, i) {
		ret = 0;
		if (enable)
			ret = clk_prepare_enable(clk);
		else
			clk_disable_unprepare(clk);

		if (ret < 0)
			dev_warn(dev, "can't use clk %d\n", i);
	}
}

static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
			       struct rsnd_adg *adg)
{
	struct device *dev = rsnd_priv_to_dev(priv);
	struct clk *clk;
	static const char * const clk_name[] = {
		[CLKA]	= "clk_a",
		[CLKB]	= "clk_b",
		[CLKC]	= "clk_c",
		[CLKI]	= "clk_i",
	};
	int i;

	for (i = 0; i < CLKMAX; i++) {
		clk = devm_clk_get(dev, clk_name[i]);
		adg->clk[i] = IS_ERR(clk) ? NULL : clk;
	}

	for_each_rsnd_clk(clk, adg, i)
		dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
}

static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
				struct rsnd_adg *adg)
{
	struct clk *clk;
	struct device *dev = rsnd_priv_to_dev(priv);
	struct device_node *np = dev->of_node;
	struct property *prop;
	u32 ckr, rbgx, rbga, rbgb;
	u32 rate, div;
#define REQ_SIZE 2
	u32 req_rate[REQ_SIZE] = {};
	uint32_t count = 0;
	unsigned long req_48kHz_rate, req_441kHz_rate;
	int i, req_size;
	const char *parent_clk_name = NULL;
	static const char * const clkout_name[] = {
		[CLKOUT]  = "audio_clkout",
		[CLKOUT1] = "audio_clkout1",
		[CLKOUT2] = "audio_clkout2",
		[CLKOUT3] = "audio_clkout3",
	};
	int brg_table[] = {
		[CLKA] = 0x0,
		[CLKB] = 0x1,
		[CLKC] = 0x4,
		[CLKI] = 0x2,
	};

	ckr = 0;
	rbga = 2; /* default 1/6 */
	rbgb = 2; /* default 1/6 */

	/*
	 * ADG supports BRRA/BRRB output only
	 * this means all clkout0/1/2/3 will be same rate
	 */
	prop = of_find_property(np, "clock-frequency", NULL);
	if (!prop)
		goto rsnd_adg_get_clkout_end;

	req_size = prop->length / sizeof(u32);

	of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
	req_48kHz_rate = 0;
	req_441kHz_rate = 0;
	for (i = 0; i < req_size; i++) {
		if (0 == (req_rate[i] % 44100))
			req_441kHz_rate = req_rate[i];
		if (0 == (req_rate[i] % 48000))
			req_48kHz_rate = req_rate[i];
	}

	if (req_rate[0] % 48000 == 0)
		adg->flags = AUDIO_OUT_48;

	/*
	 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
	 * have 44.1kHz or 48kHz base clocks for now.
	 *
	 * SSI itself can divide parent clock by 1/1 - 1/16
	 * see
	 *	rsnd_adg_ssi_clk_try_start()
	 *	rsnd_ssi_master_clk_start()
	 */
	adg->rbga_rate_for_441khz	= 0;
	adg->rbgb_rate_for_48khz	= 0;
	for_each_rsnd_clk(clk, adg, i) {
		rate = clk_get_rate(clk);

		if (0 == rate) /* not used */
			continue;

		/* RBGA */
		if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
			div = 6;
			if (req_441kHz_rate)
				div = rate / req_441kHz_rate;
			rbgx = rsnd_adg_calculate_rbgx(div);
			if (BRRx_MASK(rbgx) == rbgx) {
				rbga = rbgx;
				adg->rbga_rate_for_441khz = rate / div;
				ckr |= brg_table[i] << 20;
				if (req_441kHz_rate &&
				    !(adg_mode_flags(adg) & AUDIO_OUT_48))
					parent_clk_name = __clk_get_name(clk);
			}
		}

		/* RBGB */
		if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
			div = 6;
			if (req_48kHz_rate)
				div = rate / req_48kHz_rate;
			rbgx = rsnd_adg_calculate_rbgx(div);
			if (BRRx_MASK(rbgx) == rbgx) {
				rbgb = rbgx;
				adg->rbgb_rate_for_48khz = rate / div;
				ckr |= brg_table[i] << 16;
				if (req_48kHz_rate &&
				    (adg_mode_flags(adg) & AUDIO_OUT_48))
					parent_clk_name = __clk_get_name(clk);
			}
		}
	}

	/*
	 * ADG supports BRRA/BRRB output only.
	 * this means all clkout0/1/2/3 will be * same rate
	 */

	of_property_read_u32(np, "#clock-cells", &count);
	/*
	 * for clkout
	 */
	if (!count) {
		clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
					      parent_clk_name, 0, req_rate[0]);
		if (!IS_ERR(clk)) {
			adg->clkout[CLKOUT] = clk;
			of_clk_add_provider(np, of_clk_src_simple_get, clk);
		}
	}
	/*
	 * for clkout0/1/2/3
	 */
	else {
		for (i = 0; i < CLKOUTMAX; i++) {
			clk = clk_register_fixed_rate(dev, clkout_name[i],
						      parent_clk_name, 0,
						      req_rate[0]);
			adg->clkout[i] = ERR_PTR(-ENOENT);
			if (!IS_ERR(clk))
				adg->clkout[i] = clk;
		}
		adg->onecell.clks	= adg->clkout;
		adg->onecell.clk_num	= CLKOUTMAX;
		of_clk_add_provider(np, of_clk_src_onecell_get,
				    &adg->onecell);
	}

rsnd_adg_get_clkout_end:
	adg->ckr = ckr;
	adg->rbga = rbga;
	adg->rbgb = rbgb;

	for_each_rsnd_clkout(clk, adg, i)
		dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
	dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
		ckr, rbga, rbgb);
}

int rsnd_adg_probe(struct rsnd_priv *priv)
{
	struct rsnd_adg *adg;
	struct device *dev = rsnd_priv_to_dev(priv);
	struct device_node *np = dev->of_node;
	int ret;

	adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
	if (!adg) {
		dev_err(dev, "ADG allocate failed\n");
		return -ENOMEM;
	}

	ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
		      NULL, NULL, 0, 0);
	if (ret)
		return ret;

	rsnd_adg_get_clkin(priv, adg);
	rsnd_adg_get_clkout(priv, adg);

	if (of_get_property(np, "clkout-lr-asynchronous", NULL))
		adg->flags = LRCLK_ASYNC;

	priv->adg = adg;

	rsnd_adg_clk_enable(priv);

	return 0;
}

void rsnd_adg_remove(struct rsnd_priv *priv)
{
	struct device *dev = rsnd_priv_to_dev(priv);
	struct device_node *np = dev->of_node;

	of_clk_del_provider(np);

	rsnd_adg_clk_disable(priv);
}
Commit	Line	Data
dfc9403b KM	1	/*
	2	* Helper routines for R-Car sound ADG.
	3	*
	4	* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
2a46db4a	10	#include <linux/clk-provider.h>
dfc9403b KM	11	#include "rsnd.h"
	12
	13	#define CLKA 0
	14	#define CLKB 1
	15	#define CLKC 2
	16	#define CLKI 3
	17	#define CLKMAX 4
	18
2a46db4a KM	19	#define CLKOUT 0
	20	#define CLKOUT1 1
	21	#define CLKOUT2 2
	22	#define CLKOUT3 3
	23	#define CLKOUTMAX 4
	24
eae6fff4 KM	25	#define BRRx_MASK(x) (0x3FF & x)
eae6fff4 KM	26
1665a9e5 KM	27	static struct rsnd_mod_ops adg_ops = {
	28	.name = "adg",
	29	};
	30
dfc9403b KM	31	struct rsnd_adg {
dfc9403b KM	32	struct clk *clk[CLKMAX];
2a46db4a KM	33	struct clk *clkout[CLKOUTMAX];
2a46db4a KM	34	struct clk_onecell_data onecell;
1665a9e5	35	struct rsnd_mod mod;
7dc20319	36	u32 flags;
b99258a3 KM	37	u32 ckr;
	38	u32 rbga;
	39	u32 rbgb;
dfc9403b	40
eae6fff4 KM	41	int rbga_rate_for_441khz; /* RBGA */
eae6fff4 KM	42	int rbgb_rate_for_48khz; /* RBGB */
dfc9403b KM	43	};
dfc9403b KM	44
7dc20319	45	#define LRCLK_ASYNC (1 << 0)
25165f79	46	#define AUDIO_OUT_48 (1 << 1)
7dc20319 KM	47	#define adg_mode_flags(adg) (adg->flags)
7dc20319 KM	48
dfc9403b	49	#define for_each_rsnd_clk(pos, adg, i) \
00463c11 KM	50	for (i = 0; \
	51	(i < CLKMAX) && \
	52	((pos) = adg->clk[i]); \
	53	i++)
2a46db4a KM	54	#define for_each_rsnd_clkout(pos, adg, i) \
	55	for (i = 0; \
	56	(i < CLKOUTMAX) && \
	57	((pos) = adg->clkout[i]); \
	58	i++)
dfc9403b KM	59	#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
dfc9403b KM	60
eae6fff4 KM	61	static u32 rsnd_adg_calculate_rbgx(unsigned long div)
	62	{
	63	int i, ratio;
	64
	65	if (!div)
	66	return 0;
	67
	68	for (i = 3; i >= 0; i--) {
	69	ratio = 2 << (i * 2);
	70	if (0 == (div % ratio))
	71	return (u32)((i << 8) \| ((div / ratio) - 1));
	72	}
	73
	74	return ~0;
	75	}
629509c5	76
8467dedc	77	static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
629509c5	78	{
94458364 KM	79	struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
94458364 KM	80	int id = rsnd_mod_id(ssi_mod);
629509c5 KM	81	int ws = id;
629509c5 KM	82
b415b4d3	83	if (rsnd_ssi_is_pin_sharing(io)) {
629509c5 KM	84	switch (id) {
	85	case 1:
	86	case 2:
	87	ws = 0;
	88	break;
	89	case 4:
	90	ws = 3;
	91	break;
	92	case 8:
	93	ws = 7;
	94	break;
	95	}
	96	}
	97
	98	return (0x6 + ws) << 8;
	99	}
	100
0102eed5 KM	101	static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
	102	struct rsnd_dai_stream *io,
	103	unsigned int target_rate,
	104	unsigned int *target_val,
	105	unsigned int *target_en)
	106	{
	107	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	108	struct device *dev = rsnd_priv_to_dev(priv);
	109	int idx, sel, div, step;
	110	unsigned int val, en;
	111	unsigned int min, diff;
	112	unsigned int sel_rate[] = {
	113	clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
	114	clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
	115	clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
	116	adg->rbga_rate_for_441khz, /* 0011: RBGA */
	117	adg->rbgb_rate_for_48khz, /* 0100: RBGB */
	118	};
	119
	120	min = ~0;
	121	val = 0;
	122	en = 0;
	123	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
	124	idx = 0;
	125	step = 2;
	126
	127	if (!sel_rate[sel])
	128	continue;
	129
	130	for (div = 2; div <= 98304; div += step) {
	131	diff = abs(target_rate - sel_rate[sel] / div);
	132	if (min > diff) {
	133	val = (sel << 8) \| idx;
	134	min = diff;
	135	en = 1 << (sel + 1); /* fixme */
	136	}
	137
	138	/*
	139	* step of 0_0000 / 0_0001 / 0_1101
	140	* are out of order
	141	*/
	142	if ((idx > 2) && (idx % 2))
	143	step *= 2;
	144	if (idx == 0x1c) {
	145	div += step;
	146	step *= 2;
	147	}
	148	idx++;
	149	}
	150	}
	151
	152	if (min == ~0) {
	153	dev_err(dev, "no Input clock\n");
	154	return;
	155	}
	156
	157	*target_val = val;
	158	if (target_en)
	159	*target_en = en;
	160	}
	161
	162	static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
	163	struct rsnd_dai_stream *io,
	164	unsigned int in_rate,
165	unsigned int out_rate,
166	u32 in, u32 out, u32 *en)
167	{
168	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
169	unsigned int target_rate;
170	u32 *target_val;
171	u32 _in;
172	u32 _out;
173	u32 _en;
174
175	/* default = SSI WS */
176	_in =
177	_out = rsnd_adg_ssi_ws_timing_gen2(io);
178
179	target_rate = 0;
180	target_val = NULL;
181	_en = 0;
182	if (runtime->rate != in_rate) {
183	target_rate = out_rate;
184	target_val = &_out;
185	} else if (runtime->rate != out_rate) {
186	target_rate = in_rate;
187	target_val = &_in;
188	}
189
190	if (target_rate)
191	__rsnd_adg_get_timesel_ratio(priv, io,
192	target_rate,
193	target_val, &_en);
194
195	if (in)
196	*in = _in;
197	if (out)
198	*out = _out;
199	if (en)
200	*en = _en;
201	}
202
94458364	203	int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
bff58ea4 KM	204	struct rsnd_dai_stream *io)
bff58ea4 KM	205	{
94458364	206	struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
1665a9e5 KM	207	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
1665a9e5 KM	208	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
94458364	209	int id = rsnd_mod_id(cmd_mod);
bff58ea4 KM	210	int shift = (id % 2) ? 16 : 0;
	211	u32 mask, val;
	212
09e59075 KM	213	rsnd_adg_get_timesel_ratio(priv, io,
	214	rsnd_src_get_in_rate(priv, io),
	215	rsnd_src_get_out_rate(priv, io),
	216	NULL, &val, NULL);
bff58ea4 KM	217
	218	val = val << shift;
	219	mask = 0xffff << shift;
	220
1665a9e5	221	rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
bff58ea4 KM	222
	223	return 0;
	224	}
	225
0102eed5 KM	226	int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
	227	struct rsnd_dai_stream *io,
	228	unsigned int in_rate,
	229	unsigned int out_rate)
629509c5	230	{
f1df1229	231	struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
1665a9e5 KM	232	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
1665a9e5 KM	233	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
0102eed5 KM	234	u32 in, out;
0102eed5 KM	235	u32 mask, en;
f1df1229	236	int id = rsnd_mod_id(src_mod);
629509c5	237	int shift = (id % 2) ? 16 : 0;
629509c5	238
f1df1229 KM	239	rsnd_mod_confirm_src(src_mod);
f1df1229 KM	240
0102eed5 KM	241	rsnd_adg_get_timesel_ratio(priv, io,
	242	in_rate, out_rate,
	243	&in, &out, &en);
629509c5 KM	244
	245	in = in << shift;
	246	out = out << shift;
	247	mask = 0xffff << shift;
	248
	249	switch (id / 2) {
	250	case 0:
1665a9e5 KM	251	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
1665a9e5 KM	252	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
629509c5 KM	253	break;
629509c5 KM	254	case 1:
1665a9e5 KM	255	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
1665a9e5 KM	256	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
629509c5 KM	257	break;
629509c5 KM	258	case 2:
1665a9e5 KM	259	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
1665a9e5 KM	260	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
629509c5 KM	261	break;
629509c5 KM	262	case 3:
1665a9e5 KM	263	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
1665a9e5 KM	264	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
629509c5 KM	265	break;
629509c5 KM	266	case 4:
1665a9e5 KM	267	rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
1665a9e5 KM	268	rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
629509c5 KM	269	break;
	270	}
	271
0102eed5 KM	272	if (en)
0102eed5 KM	273	rsnd_mod_bset(adg_mod, DIV_EN, en, en);
d2c4b80c	274
ee2c828d	275	return 0;
629509c5 KM	276	}
629509c5 KM	277
f1df1229	278	static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
dfc9403b	279	{
f1df1229	280	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
1665a9e5 KM	281	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
1665a9e5 KM	282	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
f1df1229	283	int id = rsnd_mod_id(ssi_mod);
e337853e KM	284	int shift = (id % 4) * 8;
	285	u32 mask = 0xFF << shift;
	286
f1df1229 KM	287	rsnd_mod_confirm_ssi(ssi_mod);
f1df1229 KM	288
e337853e	289	val = val << shift;
dfc9403b KM	290
	291	/*
	292	* SSI 8 is not connected to ADG.
	293	* it works with SSI 7
	294	*/
	295	if (id == 8)
e337853e KM	296	return;
	297
	298	switch (id / 4) {
	299	case 0:
1665a9e5	300	rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
e337853e KM	301	break;
e337853e KM	302	case 1:
1665a9e5	303	rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
e337853e KM	304	break;
e337853e KM	305	case 2:
1665a9e5	306	rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
e337853e KM	307	break;
e337853e KM	308	}
dfc9403b KM	309	}
dfc9403b KM	310
94458364	311	int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
dfc9403b	312	{
94458364	313	rsnd_adg_set_ssi_clk(ssi_mod, 0);
dfc9403b KM	314
	315	return 0;
	316	}
	317
94458364	318	int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
dfc9403b	319	{
94458364	320	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
dfc9403b KM	321	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
dfc9403b KM	322	struct device *dev = rsnd_priv_to_dev(priv);
b99258a3	323	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
dfc9403b	324	struct clk *clk;
e337853e	325	int i;
dfc9403b	326	u32 data;
b99258a3	327	u32 ckr = 0;
dfc9403b KM	328	int sel_table[] = {
	329	[CLKA] = 0x1,
	330	[CLKB] = 0x2,
	331	[CLKC] = 0x3,
	332	[CLKI] = 0x0,
	333	};
	334
	335	dev_dbg(dev, "request clock = %d\n", rate);
	336
	337	/*
	338	* find suitable clock from
	339	* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
	340	*/
	341	data = 0;
	342	for_each_rsnd_clk(clk, adg, i) {
	343	if (rate == clk_get_rate(clk)) {
	344	data = sel_table[i];
	345	goto found_clock;
	346	}
	347	}
	348
	349	/*
eae6fff4	350	* find divided clock from BRGA/BRGB
dfc9403b	351	*/
eae6fff4	352	if (rate == adg->rbga_rate_for_441khz) {
dfc9403b KM	353	data = 0x10;
	354	goto found_clock;
	355	}
	356
eae6fff4	357	if (rate == adg->rbgb_rate_for_48khz) {
dfc9403b KM	358	data = 0x20;
	359	goto found_clock;
	360	}
	361
	362	return -EIO;
	363
	364	found_clock:
	365
94458364	366	rsnd_adg_set_ssi_clk(ssi_mod, data);
dfc9403b	367
25165f79 KM	368	if (adg_mode_flags(adg) & LRCLK_ASYNC) {
	369	if (adg_mode_flags(adg) & AUDIO_OUT_48)
	370	ckr = 0x80000000;
	371	} else {
7dc20319 KM	372	if (0 == (rate % 8000))
7dc20319 KM	373	ckr = 0x80000000;
7dc20319 KM	374	}
7dc20319 KM	375
b99258a3 KM	376	rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr \| ckr);
	377	rsnd_mod_write(adg_mod, BRRA, adg->rbga);
	378	rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
	379
3af6c3ac	380	dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
94458364	381	rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
3af6c3ac	382	data, rate);
dfc9403b KM	383
	384	return 0;
	385	}
	386
c2d31718 KM	387	void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
	388	{
	389	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	390	struct device *dev = rsnd_priv_to_dev(priv);
	391	struct clk *clk;
	392	int i, ret;
	393
	394	for_each_rsnd_clk(clk, adg, i) {
	395	ret = 0;
	396	if (enable)
	397	ret = clk_prepare_enable(clk);
	398	else
	399	clk_disable_unprepare(clk);
	400
	401	if (ret < 0)
	402	dev_warn(dev, "can't use clk %d\n", i);
	403	}
	404	}
	405
248e88c2 KM	406	static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
	407	struct rsnd_adg *adg)
	408	{
	409	struct device *dev = rsnd_priv_to_dev(priv);
	410	struct clk *clk;
	411	static const char * const clk_name[] = {
	412	[CLKA] = "clk_a",
	413	[CLKB] = "clk_b",
	414	[CLKC] = "clk_c",
	415	[CLKI] = "clk_i",
	416	};
c2d31718	417	int i;
248e88c2 KM	418
	419	for (i = 0; i < CLKMAX; i++) {
	420	clk = devm_clk_get(dev, clk_name[i]);
	421	adg->clk[i] = IS_ERR(clk) ? NULL : clk;
	422	}
	423
c2d31718	424	for_each_rsnd_clk(clk, adg, i)
248e88c2 KM	425	dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
	426	}
	427
2a46db4a KM	428	static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
2a46db4a KM	429	struct rsnd_adg *adg)
dfc9403b KM	430	{
dfc9403b KM	431	struct clk *clk;
eae6fff4	432	struct device *dev = rsnd_priv_to_dev(priv);
2a46db4a	433	struct device_node *np = dev->of_node;
25165f79	434	struct property *prop;
eae6fff4	435	u32 ckr, rbgx, rbga, rbgb;
25165f79 KM	436	u32 rate, div;
	437	#define REQ_SIZE 2
	438	u32 req_rate[REQ_SIZE] = {};
2a46db4a KM	439	uint32_t count = 0;
2a46db4a KM	440	unsigned long req_48kHz_rate, req_441kHz_rate;
25165f79	441	int i, req_size;
2a46db4a KM	442	const char *parent_clk_name = NULL;
	443	static const char * const clkout_name[] = {
	444	[CLKOUT] = "audio_clkout",
	445	[CLKOUT1] = "audio_clkout1",
	446	[CLKOUT2] = "audio_clkout2",
	447	[CLKOUT3] = "audio_clkout3",
	448	};
dfc9403b KM	449	int brg_table[] = {
	450	[CLKA] = 0x0,
	451	[CLKB] = 0x1,
	452	[CLKC] = 0x4,
	453	[CLKI] = 0x2,
	454	};
	455
e8dffe6c MV	456	ckr = 0;
	457	rbga = 2; /* default 1/6 */
	458	rbgb = 2; /* default 1/6 */
2a46db4a KM	459
	460	/*
	461	* ADG supports BRRA/BRRB output only
	462	* this means all clkout0/1/2/3 will be same rate
	463	*/
75f9e4ad	464	prop = of_find_property(np, "clock-frequency", NULL);
e8dffe6c MV	465	if (!prop)
	466	goto rsnd_adg_get_clkout_end;
	467
25165f79 KM	468	req_size = prop->length / sizeof(u32);
	469
	470	of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
2a46db4a KM	471	req_48kHz_rate = 0;
2a46db4a KM	472	req_441kHz_rate = 0;
25165f79 KM	473	for (i = 0; i < req_size; i++) {
	474	if (0 == (req_rate[i] % 44100))
	475	req_441kHz_rate = req_rate[i];
	476	if (0 == (req_rate[i] % 48000))
	477	req_48kHz_rate = req_rate[i];
	478	}
2a46db4a	479
e8dffe6c MV	480	if (req_rate[0] % 48000 == 0)
	481	adg->flags = AUDIO_OUT_48;
	482
dfc9403b KM	483	/*
	484	* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
	485	* have 44.1kHz or 48kHz base clocks for now.
	486	*
	487	* SSI itself can divide parent clock by 1/1 - 1/16
dfc9403b KM	488	* see
dfc9403b KM	489	* rsnd_adg_ssi_clk_try_start()
5c6901d9	490	* rsnd_ssi_master_clk_start()
dfc9403b	491	*/
eae6fff4 KM	492	adg->rbga_rate_for_441khz = 0;
eae6fff4 KM	493	adg->rbgb_rate_for_48khz = 0;
dfc9403b KM	494	for_each_rsnd_clk(clk, adg, i) {
	495	rate = clk_get_rate(clk);
	496
	497	if (0 == rate) /* not used */
	498	continue;
	499
	500	/* RBGA */
eae6fff4 KM	501	if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
eae6fff4 KM	502	div = 6;
2a46db4a KM	503	if (req_441kHz_rate)
2a46db4a KM	504	div = rate / req_441kHz_rate;
eae6fff4 KM	505	rbgx = rsnd_adg_calculate_rbgx(div);
	506	if (BRRx_MASK(rbgx) == rbgx) {
	507	rbga = rbgx;
	508	adg->rbga_rate_for_441khz = rate / div;
	509	ckr \|= brg_table[i] << 20;
e8a3ce11 KM	510	if (req_441kHz_rate &&
e8a3ce11 KM	511	!(adg_mode_flags(adg) & AUDIO_OUT_48))
2a46db4a	512	parent_clk_name = __clk_get_name(clk);
eae6fff4	513	}
dfc9403b KM	514	}
	515
	516	/* RBGB */
eae6fff4 KM	517	if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
eae6fff4 KM	518	div = 6;
2a46db4a KM	519	if (req_48kHz_rate)
2a46db4a KM	520	div = rate / req_48kHz_rate;
eae6fff4 KM	521	rbgx = rsnd_adg_calculate_rbgx(div);
	522	if (BRRx_MASK(rbgx) == rbgx) {
	523	rbgb = rbgx;
	524	adg->rbgb_rate_for_48khz = rate / div;
	525	ckr \|= brg_table[i] << 16;
e8a3ce11 KM	526	if (req_48kHz_rate &&
e8a3ce11 KM	527	(adg_mode_flags(adg) & AUDIO_OUT_48))
2a46db4a	528	parent_clk_name = __clk_get_name(clk);
2a46db4a KM	529	}
	530	}
	531	}
	532
	533	/*
	534	* ADG supports BRRA/BRRB output only.
	535	* this means all clkout0/1/2/3 will be * same rate
	536	*/
	537
e8dffe6c	538	of_property_read_u32(np, "#clock-cells", &count);
2a46db4a KM	539	/*
	540	* for clkout
	541	*/
	542	if (!count) {
462c30bc	543	clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
25165f79	544	parent_clk_name, 0, req_rate[0]);
2a46db4a KM	545	if (!IS_ERR(clk)) {
	546	adg->clkout[CLKOUT] = clk;
	547	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	548	}
	549	}
	550	/*
	551	* for clkout0/1/2/3
	552	*/
	553	else {
	554	for (i = 0; i < CLKOUTMAX; i++) {
	555	clk = clk_register_fixed_rate(dev, clkout_name[i],
2ebdf684	556	parent_clk_name, 0,
25165f79	557	req_rate[0]);
d7f29819 KM	558	adg->clkout[i] = ERR_PTR(-ENOENT);
d7f29819 KM	559	if (!IS_ERR(clk))
2a46db4a	560	adg->clkout[i] = clk;
dfc9403b	561	}
d7f29819 KM	562	adg->onecell.clks = adg->clkout;
	563	adg->onecell.clk_num = CLKOUTMAX;
	564	of_clk_add_provider(np, of_clk_src_onecell_get,
	565	&adg->onecell);
dfc9403b KM	566	}
dfc9403b KM	567
e8dffe6c	568	rsnd_adg_get_clkout_end:
b99258a3 KM	569	adg->ckr = ckr;
	570	adg->rbga = rbga;
	571	adg->rbgb = rbgb;
eae6fff4	572
2a46db4a KM	573	for_each_rsnd_clkout(clk, adg, i)
2a46db4a KM	574	dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
3e58690b	575	dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
eae6fff4	576	ckr, rbga, rbgb);
dfc9403b KM	577	}
dfc9403b KM	578
2ea6b074	579	int rsnd_adg_probe(struct rsnd_priv *priv)
dfc9403b KM	580	{
	581	struct rsnd_adg *adg;
	582	struct device *dev = rsnd_priv_to_dev(priv);
7dc20319	583	struct device_node *np = dev->of_node;
56d2c61d	584	int ret;
dfc9403b KM	585
	586	adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
	587	if (!adg) {
	588	dev_err(dev, "ADG allocate failed\n");
	589	return -ENOMEM;
	590	}
	591
56d2c61d	592	ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
5ba17b42	593	NULL, NULL, 0, 0);
56d2c61d WS	594	if (ret)
56d2c61d WS	595	return ret;
1665a9e5	596
248e88c2	597	rsnd_adg_get_clkin(priv, adg);
2a46db4a	598	rsnd_adg_get_clkout(priv, adg);
dfc9403b	599
7dc20319 KM	600	if (of_get_property(np, "clkout-lr-asynchronous", NULL))
	601	adg->flags = LRCLK_ASYNC;
	602
dfc9403b KM	603	priv->adg = adg;
dfc9403b KM	604
c2d31718 KM	605	rsnd_adg_clk_enable(priv);
c2d31718 KM	606
dfc9403b KM	607	return 0;
dfc9403b KM	608	}
68a55024	609
2ea6b074	610	void rsnd_adg_remove(struct rsnd_priv *priv)
68a55024	611	{
b5aac5a9 KM	612	struct device *dev = rsnd_priv_to_dev(priv);
	613	struct device_node *np = dev->of_node;
	614
	615	of_clk_del_provider(np);
	616
c2d31718	617	rsnd_adg_clk_disable(priv);
68a55024	618	}