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ASoC: soc-cache: Add support for LZO register caching
[mirror_ubuntu-zesty-kernel.git] / sound / soc / soc-cache.c
CommitLineData
17a52fd6
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1/*
2 * soc-cache.c -- ASoC register cache helpers
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
7084a42b 14#include <linux/i2c.h>
27ded041 15#include <linux/spi/spi.h>
17a52fd6 16#include <sound/soc.h>
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17#include <linux/lzo.h>
18#include <linux/bitmap.h>
17a52fd6 19
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20static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
21 unsigned int reg)
22{
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23 int ret;
24 unsigned int val;
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25
26 if (reg >= codec->driver->reg_cache_size ||
27 snd_soc_codec_volatile_register(codec, reg)) {
28 if (codec->cache_only)
29 return -1;
30
5aaa062c 31 BUG_ON(!codec->hw_read);
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32 return codec->hw_read(codec, reg);
33 }
34
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35 ret = snd_soc_cache_read(codec, reg, &val);
36 if (ret < 0)
37 return -1;
38 return val;
63b62ab0
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39}
40
41static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
42 unsigned int value)
43{
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44 u8 data[2];
45 int ret;
46
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47 data[0] = (reg << 4) | ((value >> 8) & 0x000f);
48 data[1] = value & 0x00ff;
49
db49c146 50 if (!snd_soc_codec_volatile_register(codec, reg) &&
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51 reg < codec->driver->reg_cache_size) {
52 ret = snd_soc_cache_write(codec, reg, value);
53 if (ret < 0)
54 return -1;
55 }
8c961bcc 56
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57 if (codec->cache_only) {
58 codec->cache_sync = 1;
8c961bcc 59 return 0;
a3032b47 60 }
8c961bcc 61
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62 ret = codec->hw_write(codec->control_data, data, 2);
63 if (ret == 2)
64 return 0;
65 if (ret < 0)
66 return ret;
67 else
68 return -EIO;
69}
70
71#if defined(CONFIG_SPI_MASTER)
72static int snd_soc_4_12_spi_write(void *control_data, const char *data,
73 int len)
74{
75 struct spi_device *spi = control_data;
76 struct spi_transfer t;
77 struct spi_message m;
78 u8 msg[2];
79
80 if (len <= 0)
81 return 0;
82
83 msg[0] = data[1];
84 msg[1] = data[0];
85
86 spi_message_init(&m);
87 memset(&t, 0, (sizeof t));
88
89 t.tx_buf = &msg[0];
90 t.len = len;
91
92 spi_message_add_tail(&t, &m);
93 spi_sync(spi, &m);
94
95 return len;
96}
97#else
98#define snd_soc_4_12_spi_write NULL
99#endif
100
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101static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
102 unsigned int reg)
103{
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104 int ret;
105 unsigned int val;
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106
107 if (reg >= codec->driver->reg_cache_size ||
108 snd_soc_codec_volatile_register(codec, reg)) {
109 if (codec->cache_only)
110 return -1;
111
5aaa062c 112 BUG_ON(!codec->hw_read);
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113 return codec->hw_read(codec, reg);
114 }
115
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116 ret = snd_soc_cache_read(codec, reg, &val);
117 if (ret < 0)
118 return -1;
119 return val;
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120}
121
122static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
123 unsigned int value)
124{
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125 u8 data[2];
126 int ret;
127
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128 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
129 data[1] = value & 0x00ff;
130
db49c146 131 if (!snd_soc_codec_volatile_register(codec, reg) &&
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132 reg < codec->driver->reg_cache_size) {
133 ret = snd_soc_cache_write(codec, reg, value);
134 if (ret < 0)
135 return -1;
136 }
8c961bcc 137
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138 if (codec->cache_only) {
139 codec->cache_sync = 1;
8c961bcc 140 return 0;
a3032b47 141 }
8c961bcc 142
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143 ret = codec->hw_write(codec->control_data, data, 2);
144 if (ret == 2)
145 return 0;
146 if (ret < 0)
147 return ret;
148 else
149 return -EIO;
150}
151
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152#if defined(CONFIG_SPI_MASTER)
153static int snd_soc_7_9_spi_write(void *control_data, const char *data,
154 int len)
155{
156 struct spi_device *spi = control_data;
157 struct spi_transfer t;
158 struct spi_message m;
159 u8 msg[2];
160
161 if (len <= 0)
162 return 0;
163
164 msg[0] = data[0];
165 msg[1] = data[1];
166
167 spi_message_init(&m);
168 memset(&t, 0, (sizeof t));
169
170 t.tx_buf = &msg[0];
171 t.len = len;
172
173 spi_message_add_tail(&t, &m);
174 spi_sync(spi, &m);
175
176 return len;
177}
178#else
179#define snd_soc_7_9_spi_write NULL
180#endif
181
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182static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
183 unsigned int value)
184{
341c9b84 185 u8 data[2];
7a30a3db 186 int ret;
341c9b84 187
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188 reg &= 0xff;
189 data[0] = reg;
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190 data[1] = value & 0xff;
191
005d65fb 192 if (!snd_soc_codec_volatile_register(codec, reg) &&
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193 reg < codec->driver->reg_cache_size) {
194 ret = snd_soc_cache_write(codec, reg, value);
195 if (ret < 0)
196 return -1;
197 }
341c9b84 198
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199 if (codec->cache_only) {
200 codec->cache_sync = 1;
8c961bcc 201 return 0;
a3032b47 202 }
8c961bcc 203
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204 if (codec->hw_write(codec->control_data, data, 2) == 2)
205 return 0;
206 else
207 return -EIO;
208}
209
210static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
211 unsigned int reg)
212{
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213 int ret;
214 unsigned int val;
db49c146 215
f4bee1bb 216 reg &= 0xff;
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DP
217 if (reg >= codec->driver->reg_cache_size ||
218 snd_soc_codec_volatile_register(codec, reg)) {
219 if (codec->cache_only)
220 return -1;
221
5aaa062c 222 BUG_ON(!codec->hw_read);
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DP
223 return codec->hw_read(codec, reg);
224 }
225
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226 ret = snd_soc_cache_read(codec, reg, &val);
227 if (ret < 0)
228 return -1;
229 return val;
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230}
231
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232#if defined(CONFIG_SPI_MASTER)
233static int snd_soc_8_8_spi_write(void *control_data, const char *data,
234 int len)
235{
236 struct spi_device *spi = control_data;
237 struct spi_transfer t;
238 struct spi_message m;
239 u8 msg[2];
240
241 if (len <= 0)
242 return 0;
243
244 msg[0] = data[0];
245 msg[1] = data[1];
246
247 spi_message_init(&m);
248 memset(&t, 0, (sizeof t));
249
250 t.tx_buf = &msg[0];
251 t.len = len;
252
253 spi_message_add_tail(&t, &m);
254 spi_sync(spi, &m);
255
256 return len;
257}
258#else
259#define snd_soc_8_8_spi_write NULL
260#endif
261
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262static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
263 unsigned int value)
264{
afa2f106 265 u8 data[3];
7a30a3db 266 int ret;
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267
268 data[0] = reg;
269 data[1] = (value >> 8) & 0xff;
270 data[2] = value & 0xff;
271
3e13f65e 272 if (!snd_soc_codec_volatile_register(codec, reg) &&
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273 reg < codec->driver->reg_cache_size) {
274 ret = snd_soc_cache_write(codec, reg, value);
275 if (ret < 0)
276 return -1;
277 }
afa2f106 278
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279 if (codec->cache_only) {
280 codec->cache_sync = 1;
8c961bcc 281 return 0;
a3032b47 282 }
8c961bcc 283
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284 if (codec->hw_write(codec->control_data, data, 3) == 3)
285 return 0;
286 else
287 return -EIO;
288}
289
290static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
291 unsigned int reg)
292{
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293 int ret;
294 unsigned int val;
afa2f106 295
f0fba2ad 296 if (reg >= codec->driver->reg_cache_size ||
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297 snd_soc_codec_volatile_register(codec, reg)) {
298 if (codec->cache_only)
391d8a04 299 return -1;
8c961bcc 300
5aaa062c 301 BUG_ON(!codec->hw_read);
afa2f106 302 return codec->hw_read(codec, reg);
8c961bcc 303 }
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304
305 ret = snd_soc_cache_read(codec, reg, &val);
306 if (ret < 0)
307 return -1;
308 return val;
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309}
310
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311#if defined(CONFIG_SPI_MASTER)
312static int snd_soc_8_16_spi_write(void *control_data, const char *data,
313 int len)
314{
315 struct spi_device *spi = control_data;
316 struct spi_transfer t;
317 struct spi_message m;
318 u8 msg[3];
319
320 if (len <= 0)
321 return 0;
322
323 msg[0] = data[0];
324 msg[1] = data[1];
325 msg[2] = data[2];
326
327 spi_message_init(&m);
328 memset(&t, 0, (sizeof t));
329
330 t.tx_buf = &msg[0];
331 t.len = len;
332
333 spi_message_add_tail(&t, &m);
334 spi_sync(spi, &m);
335
336 return len;
337}
338#else
339#define snd_soc_8_16_spi_write NULL
340#endif
341
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342#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
343static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
344 unsigned int r)
345{
346 struct i2c_msg xfer[2];
347 u8 reg = r;
348 u8 data;
349 int ret;
350 struct i2c_client *client = codec->control_data;
351
352 /* Write register */
353 xfer[0].addr = client->addr;
354 xfer[0].flags = 0;
355 xfer[0].len = 1;
356 xfer[0].buf = &reg;
357
358 /* Read data */
359 xfer[1].addr = client->addr;
360 xfer[1].flags = I2C_M_RD;
361 xfer[1].len = 1;
362 xfer[1].buf = &data;
363
364 ret = i2c_transfer(client->adapter, xfer, 2);
365 if (ret != 2) {
366 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
367 return 0;
368 }
369
370 return data;
371}
372#else
373#define snd_soc_8_8_read_i2c NULL
374#endif
375
17244c24 376#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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377static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
378 unsigned int r)
379{
380 struct i2c_msg xfer[2];
381 u8 reg = r;
382 u16 data;
383 int ret;
384 struct i2c_client *client = codec->control_data;
385
386 /* Write register */
387 xfer[0].addr = client->addr;
388 xfer[0].flags = 0;
389 xfer[0].len = 1;
390 xfer[0].buf = &reg;
391
392 /* Read data */
393 xfer[1].addr = client->addr;
394 xfer[1].flags = I2C_M_RD;
395 xfer[1].len = 2;
396 xfer[1].buf = (u8 *)&data;
397
398 ret = i2c_transfer(client->adapter, xfer, 2);
399 if (ret != 2) {
400 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
401 return 0;
402 }
403
404 return (data >> 8) | ((data & 0xff) << 8);
405}
406#else
407#define snd_soc_8_16_read_i2c NULL
408#endif
17a52fd6 409
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410#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
411static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
412 unsigned int r)
413{
414 struct i2c_msg xfer[2];
415 u16 reg = r;
416 u8 data;
417 int ret;
418 struct i2c_client *client = codec->control_data;
419
420 /* Write register */
421 xfer[0].addr = client->addr;
422 xfer[0].flags = 0;
423 xfer[0].len = 2;
424 xfer[0].buf = (u8 *)&reg;
425
426 /* Read data */
427 xfer[1].addr = client->addr;
428 xfer[1].flags = I2C_M_RD;
429 xfer[1].len = 1;
430 xfer[1].buf = &data;
431
432 ret = i2c_transfer(client->adapter, xfer, 2);
433 if (ret != 2) {
434 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
435 return 0;
436 }
437
438 return data;
439}
440#else
441#define snd_soc_16_8_read_i2c NULL
442#endif
443
444static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
445 unsigned int reg)
446{
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447 int ret;
448 unsigned int val;
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449
450 reg &= 0xff;
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DP
451 if (reg >= codec->driver->reg_cache_size ||
452 snd_soc_codec_volatile_register(codec, reg)) {
453 if (codec->cache_only)
454 return -1;
455
5aaa062c 456 BUG_ON(!codec->hw_read);
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DP
457 return codec->hw_read(codec, reg);
458 }
459
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460 ret = snd_soc_cache_read(codec, reg, &val);
461 if (ret < 0)
462 return -1;
463 return val;
994dc424
BS
464}
465
466static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
467 unsigned int value)
468{
994dc424
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469 u8 data[3];
470 int ret;
471
994dc424
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472 data[0] = (reg >> 8) & 0xff;
473 data[1] = reg & 0xff;
474 data[2] = value;
475
476 reg &= 0xff;
db49c146 477 if (!snd_soc_codec_volatile_register(codec, reg) &&
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DP
478 reg < codec->driver->reg_cache_size) {
479 ret = snd_soc_cache_write(codec, reg, value);
480 if (ret < 0)
481 return -1;
482 }
8c961bcc 483
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484 if (codec->cache_only) {
485 codec->cache_sync = 1;
8c961bcc 486 return 0;
a3032b47 487 }
8c961bcc 488
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489 ret = codec->hw_write(codec->control_data, data, 3);
490 if (ret == 3)
491 return 0;
492 if (ret < 0)
493 return ret;
494 else
495 return -EIO;
496}
497
498#if defined(CONFIG_SPI_MASTER)
499static int snd_soc_16_8_spi_write(void *control_data, const char *data,
500 int len)
501{
502 struct spi_device *spi = control_data;
503 struct spi_transfer t;
504 struct spi_message m;
505 u8 msg[3];
506
507 if (len <= 0)
508 return 0;
509
510 msg[0] = data[0];
511 msg[1] = data[1];
512 msg[2] = data[2];
513
514 spi_message_init(&m);
515 memset(&t, 0, (sizeof t));
516
517 t.tx_buf = &msg[0];
518 t.len = len;
519
520 spi_message_add_tail(&t, &m);
521 spi_sync(spi, &m);
522
523 return len;
524}
525#else
526#define snd_soc_16_8_spi_write NULL
527#endif
528
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529#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
530static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
531 unsigned int r)
532{
533 struct i2c_msg xfer[2];
534 u16 reg = cpu_to_be16(r);
535 u16 data;
536 int ret;
537 struct i2c_client *client = codec->control_data;
538
539 /* Write register */
540 xfer[0].addr = client->addr;
541 xfer[0].flags = 0;
542 xfer[0].len = 2;
543 xfer[0].buf = (u8 *)&reg;
544
545 /* Read data */
546 xfer[1].addr = client->addr;
547 xfer[1].flags = I2C_M_RD;
548 xfer[1].len = 2;
549 xfer[1].buf = (u8 *)&data;
550
551 ret = i2c_transfer(client->adapter, xfer, 2);
552 if (ret != 2) {
553 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
554 return 0;
555 }
556
557 return be16_to_cpu(data);
558}
559#else
560#define snd_soc_16_16_read_i2c NULL
561#endif
562
563static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
564 unsigned int reg)
565{
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566 int ret;
567 unsigned int val;
bc6552f4 568
f0fba2ad 569 if (reg >= codec->driver->reg_cache_size ||
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570 snd_soc_codec_volatile_register(codec, reg)) {
571 if (codec->cache_only)
391d8a04 572 return -1;
bc6552f4 573
5aaa062c 574 BUG_ON(!codec->hw_read);
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575 return codec->hw_read(codec, reg);
576 }
577
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578 ret = snd_soc_cache_read(codec, reg, &val);
579 if (ret < 0)
580 return -1;
581
582 return val;
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583}
584
585static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
586 unsigned int value)
587{
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588 u8 data[4];
589 int ret;
590
591 data[0] = (reg >> 8) & 0xff;
592 data[1] = reg & 0xff;
593 data[2] = (value >> 8) & 0xff;
594 data[3] = value & 0xff;
595
db49c146 596 if (!snd_soc_codec_volatile_register(codec, reg) &&
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DP
597 reg < codec->driver->reg_cache_size) {
598 ret = snd_soc_cache_write(codec, reg, value);
599 if (ret < 0)
600 return -1;
601 }
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602
603 if (codec->cache_only) {
604 codec->cache_sync = 1;
605 return 0;
606 }
607
608 ret = codec->hw_write(codec->control_data, data, 4);
609 if (ret == 4)
610 return 0;
611 if (ret < 0)
612 return ret;
613 else
614 return -EIO;
615}
994dc424 616
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617#if defined(CONFIG_SPI_MASTER)
618static int snd_soc_16_16_spi_write(void *control_data, const char *data,
619 int len)
620{
621 struct spi_device *spi = control_data;
622 struct spi_transfer t;
623 struct spi_message m;
624 u8 msg[4];
625
626 if (len <= 0)
627 return 0;
628
629 msg[0] = data[0];
630 msg[1] = data[1];
631 msg[2] = data[2];
632 msg[3] = data[3];
633
634 spi_message_init(&m);
635 memset(&t, 0, (sizeof t));
636
637 t.tx_buf = &msg[0];
638 t.len = len;
639
640 spi_message_add_tail(&t, &m);
641 spi_sync(spi, &m);
642
643 return len;
644}
645#else
646#define snd_soc_16_16_spi_write NULL
647#endif
648
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649static struct {
650 int addr_bits;
651 int data_bits;
afa2f106 652 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
27ded041 653 int (*spi_write)(void *, const char *, int);
17a52fd6 654 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
afa2f106 655 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
17a52fd6 656} io_types[] = {
63b62ab0
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657 {
658 .addr_bits = 4, .data_bits = 12,
659 .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
660 .spi_write = snd_soc_4_12_spi_write,
661 },
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662 {
663 .addr_bits = 7, .data_bits = 9,
664 .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
8998c899 665 .spi_write = snd_soc_7_9_spi_write,
d62ab358
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666 },
667 {
668 .addr_bits = 8, .data_bits = 8,
669 .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
85dfcdff 670 .i2c_read = snd_soc_8_8_read_i2c,
f479fd93 671 .spi_write = snd_soc_8_8_spi_write,
d62ab358
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672 },
673 {
674 .addr_bits = 8, .data_bits = 16,
675 .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
676 .i2c_read = snd_soc_8_16_read_i2c,
f479fd93 677 .spi_write = snd_soc_8_16_spi_write,
d62ab358 678 },
994dc424
BS
679 {
680 .addr_bits = 16, .data_bits = 8,
681 .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
682 .i2c_read = snd_soc_16_8_read_i2c,
683 .spi_write = snd_soc_16_8_spi_write,
684 },
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685 {
686 .addr_bits = 16, .data_bits = 16,
687 .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
688 .i2c_read = snd_soc_16_16_read_i2c,
f479fd93 689 .spi_write = snd_soc_16_16_spi_write,
bc6552f4 690 },
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691};
692
693/**
694 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
695 *
696 * @codec: CODEC to configure.
697 * @type: Type of cache.
698 * @addr_bits: Number of bits of register address data.
699 * @data_bits: Number of bits of data per register.
7084a42b 700 * @control: Control bus used.
17a52fd6
MB
701 *
702 * Register formats are frequently shared between many I2C and SPI
703 * devices. In order to promote code reuse the ASoC core provides
704 * some standard implementations of CODEC read and write operations
705 * which can be set up using this function.
706 *
707 * The caller is responsible for allocating and initialising the
708 * actual cache.
709 *
710 * Note that at present this code cannot be used by CODECs with
711 * volatile registers.
712 */
713int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b
MB
714 int addr_bits, int data_bits,
715 enum snd_soc_control_type control)
17a52fd6
MB
716{
717 int i;
718
17a52fd6
MB
719 for (i = 0; i < ARRAY_SIZE(io_types); i++)
720 if (io_types[i].addr_bits == addr_bits &&
721 io_types[i].data_bits == data_bits)
722 break;
723 if (i == ARRAY_SIZE(io_types)) {
724 printk(KERN_ERR
725 "No I/O functions for %d bit address %d bit data\n",
726 addr_bits, data_bits);
727 return -EINVAL;
728 }
729
f0fba2ad
LG
730 codec->driver->write = io_types[i].write;
731 codec->driver->read = io_types[i].read;
17a52fd6 732
7084a42b
MB
733 switch (control) {
734 case SND_SOC_CUSTOM:
735 break;
736
737 case SND_SOC_I2C:
17244c24 738#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b
MB
739 codec->hw_write = (hw_write_t)i2c_master_send;
740#endif
afa2f106
MB
741 if (io_types[i].i2c_read)
742 codec->hw_read = io_types[i].i2c_read;
a6d14342
MB
743
744 codec->control_data = container_of(codec->dev,
745 struct i2c_client,
746 dev);
7084a42b
MB
747 break;
748
749 case SND_SOC_SPI:
27ded041
MB
750 if (io_types[i].spi_write)
751 codec->hw_write = io_types[i].spi_write;
a6d14342
MB
752
753 codec->control_data = container_of(codec->dev,
754 struct spi_device,
755 dev);
7084a42b
MB
756 break;
757 }
758
17a52fd6
MB
759 return 0;
760}
761EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
7a30a3db 762
cc28fb8e
DP
763struct snd_soc_lzo_ctx {
764 void *wmem;
765 void *dst;
766 const void *src;
767 size_t src_len;
768 size_t dst_len;
769 size_t decompressed_size;
770 unsigned long *sync_bmp;
771 int sync_bmp_nbits;
772};
773
774#define LZO_BLOCK_NUM 8
775static int snd_soc_lzo_block_count(void)
776{
777 return LZO_BLOCK_NUM;
778}
779
780static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
781{
782 lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
783 if (!lzo_ctx->wmem)
784 return -ENOMEM;
785 return 0;
786}
787
788static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
789{
790 size_t compress_size;
791 int ret;
792
793 ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
794 lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
795 if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
796 return -EINVAL;
797 lzo_ctx->dst_len = compress_size;
798 return 0;
799}
800
801static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
802{
803 size_t dst_len;
804 int ret;
805
806 dst_len = lzo_ctx->dst_len;
807 ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
808 lzo_ctx->dst, &dst_len);
809 if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
810 return -EINVAL;
811 return 0;
812}
813
814static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
815 struct snd_soc_lzo_ctx *lzo_ctx)
816{
817 int ret;
818
819 lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
820 lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
821 if (!lzo_ctx->dst) {
822 lzo_ctx->dst_len = 0;
823 return -ENOMEM;
824 }
825
826 ret = snd_soc_lzo_compress(lzo_ctx);
827 if (ret < 0)
828 return ret;
829 return 0;
830}
831
832static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
833 struct snd_soc_lzo_ctx *lzo_ctx)
834{
835 int ret;
836
837 lzo_ctx->dst_len = lzo_ctx->decompressed_size;
838 lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
839 if (!lzo_ctx->dst) {
840 lzo_ctx->dst_len = 0;
841 return -ENOMEM;
842 }
843
844 ret = snd_soc_lzo_decompress(lzo_ctx);
845 if (ret < 0)
846 return ret;
847 return 0;
848}
849
850static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
851 unsigned int reg)
852{
853 struct snd_soc_codec_driver *codec_drv;
854 size_t reg_size;
855
856 codec_drv = codec->driver;
857 reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
858 return (reg * codec_drv->reg_word_size) /
859 DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count());
860}
861
862static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
863 unsigned int reg)
864{
865 struct snd_soc_codec_driver *codec_drv;
866 size_t reg_size;
867
868 codec_drv = codec->driver;
869 reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
870 return reg % (DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count()) /
871 codec_drv->reg_word_size);
872}
873
874static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
875{
876 struct snd_soc_codec_driver *codec_drv;
877 size_t reg_size;
878
879 codec_drv = codec->driver;
880 reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
881 return DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count());
882}
883
884static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
885{
886 struct snd_soc_lzo_ctx **lzo_blocks;
887 unsigned int val;
888 int i;
889
890 lzo_blocks = codec->reg_cache;
891 for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
892 snd_soc_cache_read(codec, i, &val);
893 snd_soc_write(codec, i, val);
894 dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
895 i, val);
896 }
897
898 return 0;
899}
900
901static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
902 unsigned int reg, unsigned int value)
903{
904 struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
905 int ret, blkindex, blkpos;
906 size_t blksize, tmp_dst_len;
907 void *tmp_dst;
908
909 /* index of the compressed lzo block */
910 blkindex = snd_soc_lzo_get_blkindex(codec, reg);
911 /* register index within the decompressed block */
912 blkpos = snd_soc_lzo_get_blkpos(codec, reg);
913 /* size of the compressed block */
914 blksize = snd_soc_lzo_get_blksize(codec);
915 lzo_blocks = codec->reg_cache;
916 lzo_block = lzo_blocks[blkindex];
917
918 /* save the pointer and length of the compressed block */
919 tmp_dst = lzo_block->dst;
920 tmp_dst_len = lzo_block->dst_len;
921
922 /* prepare the source to be the compressed block */
923 lzo_block->src = lzo_block->dst;
924 lzo_block->src_len = lzo_block->dst_len;
925
926 /* decompress the block */
927 ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
928 if (ret < 0) {
929 kfree(lzo_block->dst);
930 goto out;
931 }
932
933 /* write the new value to the cache */
934 switch (codec->driver->reg_word_size) {
935 case 1: {
936 u8 *cache;
937 cache = lzo_block->dst;
938 if (cache[blkpos] == value) {
939 kfree(lzo_block->dst);
940 goto out;
941 }
942 cache[blkpos] = value;
943 }
944 break;
945 case 2: {
946 u16 *cache;
947 cache = lzo_block->dst;
948 if (cache[blkpos] == value) {
949 kfree(lzo_block->dst);
950 goto out;
951 }
952 cache[blkpos] = value;
953 }
954 break;
955 default:
956 BUG();
957 }
958
959 /* prepare the source to be the decompressed block */
960 lzo_block->src = lzo_block->dst;
961 lzo_block->src_len = lzo_block->dst_len;
962
963 /* compress the block */
964 ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
965 if (ret < 0) {
966 kfree(lzo_block->dst);
967 kfree(lzo_block->src);
968 goto out;
969 }
970
971 /* set the bit so we know we have to sync this register */
972 set_bit(reg, lzo_block->sync_bmp);
973 kfree(tmp_dst);
974 kfree(lzo_block->src);
975 return 0;
976out:
977 lzo_block->dst = tmp_dst;
978 lzo_block->dst_len = tmp_dst_len;
979 return ret;
980}
981
982static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
983 unsigned int reg, unsigned int *value)
984{
985 struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
986 int ret, blkindex, blkpos;
987 size_t blksize, tmp_dst_len;
988 void *tmp_dst;
989
990 *value = 0;
991 /* index of the compressed lzo block */
992 blkindex = snd_soc_lzo_get_blkindex(codec, reg);
993 /* register index within the decompressed block */
994 blkpos = snd_soc_lzo_get_blkpos(codec, reg);
995 /* size of the compressed block */
996 blksize = snd_soc_lzo_get_blksize(codec);
997 lzo_blocks = codec->reg_cache;
998 lzo_block = lzo_blocks[blkindex];
999
1000 /* save the pointer and length of the compressed block */
1001 tmp_dst = lzo_block->dst;
1002 tmp_dst_len = lzo_block->dst_len;
1003
1004 /* prepare the source to be the compressed block */
1005 lzo_block->src = lzo_block->dst;
1006 lzo_block->src_len = lzo_block->dst_len;
1007
1008 /* decompress the block */
1009 ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
1010 if (ret >= 0) {
1011 /* fetch the value from the cache */
1012 switch (codec->driver->reg_word_size) {
1013 case 1: {
1014 u8 *cache;
1015 cache = lzo_block->dst;
1016 *value = cache[blkpos];
1017 }
1018 break;
1019 case 2: {
1020 u16 *cache;
1021 cache = lzo_block->dst;
1022 *value = cache[blkpos];
1023 }
1024 break;
1025 default:
1026 BUG();
1027 }
1028 }
1029
1030 kfree(lzo_block->dst);
1031 /* restore the pointer and length of the compressed block */
1032 lzo_block->dst = tmp_dst;
1033 lzo_block->dst_len = tmp_dst_len;
1034 return 0;
1035}
1036
1037static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
1038{
1039 struct snd_soc_lzo_ctx **lzo_blocks;
1040 int i, blkcount;
1041
1042 lzo_blocks = codec->reg_cache;
1043 if (!lzo_blocks)
1044 return 0;
1045
1046 blkcount = snd_soc_lzo_block_count();
1047 /*
1048 * the pointer to the bitmap used for syncing the cache
1049 * is shared amongst all lzo_blocks. Ensure it is freed
1050 * only once.
1051 */
1052 if (lzo_blocks[0])
1053 kfree(lzo_blocks[0]->sync_bmp);
1054 for (i = 0; i < blkcount; ++i) {
1055 if (lzo_blocks[i]) {
1056 kfree(lzo_blocks[i]->wmem);
1057 kfree(lzo_blocks[i]->dst);
1058 }
1059 /* each lzo_block is a pointer returned by kmalloc or NULL */
1060 kfree(lzo_blocks[i]);
1061 }
1062 kfree(lzo_blocks);
1063 codec->reg_cache = NULL;
1064 return 0;
1065}
1066
1067static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
1068{
1069 struct snd_soc_lzo_ctx **lzo_blocks;
1070 size_t reg_size, bmp_size;
1071 struct snd_soc_codec_driver *codec_drv;
1072 int ret, tofree, i, blksize, blkcount;
1073 const char *p, *end;
1074 unsigned long *sync_bmp;
1075
1076 ret = 0;
1077 codec_drv = codec->driver;
1078 reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
1079
1080 /*
1081 * If we have not been given a default register cache
1082 * then allocate a dummy zero-ed out region, compress it
1083 * and remember to free it afterwards.
1084 */
1085 tofree = 0;
1086 if (!codec_drv->reg_cache_default)
1087 tofree = 1;
1088
1089 if (!codec_drv->reg_cache_default) {
1090 codec_drv->reg_cache_default = kzalloc(reg_size,
1091 GFP_KERNEL);
1092 if (!codec_drv->reg_cache_default)
1093 return -ENOMEM;
1094 }
1095
1096 blkcount = snd_soc_lzo_block_count();
1097 codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
1098 GFP_KERNEL);
1099 if (!codec->reg_cache) {
1100 ret = -ENOMEM;
1101 goto err_tofree;
1102 }
1103 lzo_blocks = codec->reg_cache;
1104
1105 /*
1106 * allocate a bitmap to be used when syncing the cache with
1107 * the hardware. Each time a register is modified, the corresponding
1108 * bit is set in the bitmap, so we know that we have to sync
1109 * that register.
1110 */
1111 bmp_size = codec_drv->reg_cache_size;
1112 sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof (long),
1113 GFP_KERNEL);
1114 if (!sync_bmp) {
1115 ret = -ENOMEM;
1116 goto err;
1117 }
1118 bitmap_zero(sync_bmp, reg_size);
1119
1120 /* allocate the lzo blocks and initialize them */
1121 for (i = 0; i < blkcount; ++i) {
1122 lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
1123 GFP_KERNEL);
1124 if (!lzo_blocks[i]) {
1125 kfree(sync_bmp);
1126 ret = -ENOMEM;
1127 goto err;
1128 }
1129 lzo_blocks[i]->sync_bmp = sync_bmp;
1130 lzo_blocks[i]->sync_bmp_nbits = reg_size;
1131 /* alloc the working space for the compressed block */
1132 ret = snd_soc_lzo_prepare(lzo_blocks[i]);
1133 if (ret < 0)
1134 goto err;
1135 }
1136
1137 blksize = snd_soc_lzo_get_blksize(codec);
1138 p = codec_drv->reg_cache_default;
1139 end = codec_drv->reg_cache_default + reg_size;
1140 /* compress the register map and fill the lzo blocks */
1141 for (i = 0; i < blkcount; ++i, p += blksize) {
1142 lzo_blocks[i]->src = p;
1143 if (p + blksize > end)
1144 lzo_blocks[i]->src_len = end - p;
1145 else
1146 lzo_blocks[i]->src_len = blksize;
1147 ret = snd_soc_lzo_compress_cache_block(codec,
1148 lzo_blocks[i]);
1149 if (ret < 0)
1150 goto err;
1151 lzo_blocks[i]->decompressed_size =
1152 lzo_blocks[i]->src_len;
1153 }
1154
1155 if (tofree)
1156 kfree(codec_drv->reg_cache_default);
1157 return 0;
1158err:
1159 snd_soc_cache_exit(codec);
1160err_tofree:
1161 if (tofree)
1162 kfree(codec_drv->reg_cache_default);
1163 return ret;
1164}
1165
7a30a3db
DP
1166static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
1167{
1168 int i;
1169 struct snd_soc_codec_driver *codec_drv;
1170 unsigned int val;
1171
1172 codec_drv = codec->driver;
1173 for (i = 0; i < codec_drv->reg_cache_size; ++i) {
1174 snd_soc_cache_read(codec, i, &val);
1175 if (codec_drv->reg_cache_default) {
1176 switch (codec_drv->reg_word_size) {
1177 case 1: {
1178 const u8 *cache;
1179
1180 cache = codec_drv->reg_cache_default;
1181 if (cache[i] == val)
1182 continue;
1183 }
1184 break;
1185 case 2: {
1186 const u16 *cache;
1187
1188 cache = codec_drv->reg_cache_default;
1189 if (cache[i] == val)
1190 continue;
1191 }
1192 break;
1193 default:
1194 BUG();
1195 }
1196 }
1197 snd_soc_write(codec, i, val);
1198 dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
1199 i, val);
1200 }
1201 return 0;
1202}
1203
1204static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
1205 unsigned int reg, unsigned int value)
1206{
1207 switch (codec->driver->reg_word_size) {
1208 case 1: {
1209 u8 *cache;
1210
1211 cache = codec->reg_cache;
1212 cache[reg] = value;
1213 }
1214 break;
1215 case 2: {
1216 u16 *cache;
1217
1218 cache = codec->reg_cache;
1219 cache[reg] = value;
1220 }
1221 break;
1222 default:
1223 BUG();
1224 }
1225
1226 return 0;
1227}
1228
1229static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
1230 unsigned int reg, unsigned int *value)
1231{
1232 switch (codec->driver->reg_word_size) {
1233 case 1: {
1234 u8 *cache;
1235
1236 cache = codec->reg_cache;
1237 *value = cache[reg];
1238 }
1239 break;
1240 case 2: {
1241 u16 *cache;
1242
1243 cache = codec->reg_cache;
1244 *value = cache[reg];
1245 }
1246 break;
1247 default:
1248 BUG();
1249 }
1250
1251 return 0;
1252}
1253
1254static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
1255{
1256 if (!codec->reg_cache)
1257 return 0;
1258 kfree(codec->reg_cache);
1259 codec->reg_cache = NULL;
1260 return 0;
1261}
1262
1263static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
1264{
1265 struct snd_soc_codec_driver *codec_drv;
1266 size_t reg_size;
1267
1268 codec_drv = codec->driver;
1269 reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
1270
1271 if (codec_drv->reg_cache_default)
1272 codec->reg_cache = kmemdup(codec_drv->reg_cache_default,
1273 reg_size, GFP_KERNEL);
1274 else
1275 codec->reg_cache = kzalloc(reg_size, GFP_KERNEL);
1276 if (!codec->reg_cache)
1277 return -ENOMEM;
1278
1279 return 0;
1280}
1281
1282/* an array of all supported compression types */
1283static const struct snd_soc_cache_ops cache_types[] = {
1284 {
1285 .id = SND_SOC_NO_COMPRESSION,
1286 .init = snd_soc_flat_cache_init,
1287 .exit = snd_soc_flat_cache_exit,
1288 .read = snd_soc_flat_cache_read,
1289 .write = snd_soc_flat_cache_write,
1290 .sync = snd_soc_flat_cache_sync
cc28fb8e
DP
1291 },
1292 {
1293 .id = SND_SOC_LZO_COMPRESSION,
1294 .init = snd_soc_lzo_cache_init,
1295 .exit = snd_soc_lzo_cache_exit,
1296 .read = snd_soc_lzo_cache_read,
1297 .write = snd_soc_lzo_cache_write,
1298 .sync = snd_soc_lzo_cache_sync
7a30a3db
DP
1299 }
1300};
1301
1302int snd_soc_cache_init(struct snd_soc_codec *codec)
1303{
1304 int i;
1305
1306 for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
1307 if (cache_types[i].id == codec->driver->compress_type)
1308 break;
1309 if (i == ARRAY_SIZE(cache_types)) {
1310 dev_err(codec->dev, "Could not match compress type: %d\n",
1311 codec->driver->compress_type);
1312 return -EINVAL;
1313 }
1314
1315 mutex_init(&codec->cache_rw_mutex);
1316 codec->cache_ops = &cache_types[i];
1317
1318 if (codec->cache_ops->init)
1319 return codec->cache_ops->init(codec);
1320 return -EINVAL;
1321}
1322
1323/*
1324 * NOTE: keep in mind that this function might be called
1325 * multiple times.
1326 */
1327int snd_soc_cache_exit(struct snd_soc_codec *codec)
1328{
1329 if (codec->cache_ops && codec->cache_ops->exit)
1330 return codec->cache_ops->exit(codec);
1331 return -EINVAL;
1332}
1333
1334/**
1335 * snd_soc_cache_read: Fetch the value of a given register from the cache.
1336 *
1337 * @codec: CODEC to configure.
1338 * @reg: The register index.
1339 * @value: The value to be returned.
1340 */
1341int snd_soc_cache_read(struct snd_soc_codec *codec,
1342 unsigned int reg, unsigned int *value)
1343{
1344 int ret;
1345
1346 mutex_lock(&codec->cache_rw_mutex);
1347
1348 if (value && codec->cache_ops && codec->cache_ops->read) {
1349 ret = codec->cache_ops->read(codec, reg, value);
1350 mutex_unlock(&codec->cache_rw_mutex);
1351 return ret;
1352 }
1353
1354 mutex_unlock(&codec->cache_rw_mutex);
1355 return -EINVAL;
1356}
1357EXPORT_SYMBOL_GPL(snd_soc_cache_read);
1358
1359/**
1360 * snd_soc_cache_write: Set the value of a given register in the cache.
1361 *
1362 * @codec: CODEC to configure.
1363 * @reg: The register index.
1364 * @value: The new register value.
1365 */
1366int snd_soc_cache_write(struct snd_soc_codec *codec,
1367 unsigned int reg, unsigned int value)
1368{
1369 int ret;
1370
1371 mutex_lock(&codec->cache_rw_mutex);
1372
1373 if (codec->cache_ops && codec->cache_ops->write) {
1374 ret = codec->cache_ops->write(codec, reg, value);
1375 mutex_unlock(&codec->cache_rw_mutex);
1376 return ret;
1377 }
1378
1379 mutex_unlock(&codec->cache_rw_mutex);
1380 return -EINVAL;
1381}
1382EXPORT_SYMBOL_GPL(snd_soc_cache_write);
1383
1384/**
1385 * snd_soc_cache_sync: Sync the register cache with the hardware.
1386 *
1387 * @codec: CODEC to configure.
1388 *
1389 * Any registers that should not be synced should be marked as
1390 * volatile. In general drivers can choose not to use the provided
1391 * syncing functionality if they so require.
1392 */
1393int snd_soc_cache_sync(struct snd_soc_codec *codec)
1394{
1395 int ret;
1396
1397 if (!codec->cache_sync) {
1398 return 0;
1399 }
1400
1401 if (codec->cache_ops && codec->cache_ops->sync) {
1402 ret = codec->cache_ops->sync(codec);
1403 if (!ret)
1404 codec->cache_sync = 0;
1405 return ret;
1406 }
1407
1408 return -EINVAL;
1409}
1410EXPORT_SYMBOL_GPL(snd_soc_cache_sync);