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1 | /* |
2 | * soc-cache.c -- ASoC register cache helpers | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
7084a42b | 14 | #include <linux/i2c.h> |
27ded041 | 15 | #include <linux/spi/spi.h> |
17a52fd6 MB |
16 | #include <sound/soc.h> |
17 | ||
18 | static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec, | |
19 | unsigned int reg) | |
20 | { | |
21 | u16 *cache = codec->reg_cache; | |
22 | if (reg >= codec->reg_cache_size) | |
23 | return -1; | |
24 | return cache[reg]; | |
25 | } | |
26 | ||
27 | static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg, | |
28 | unsigned int value) | |
29 | { | |
30 | u16 *cache = codec->reg_cache; | |
31 | u8 data[2]; | |
32 | int ret; | |
33 | ||
34 | BUG_ON(codec->volatile_register); | |
35 | ||
36 | data[0] = (reg << 1) | ((value >> 8) & 0x0001); | |
37 | data[1] = value & 0x00ff; | |
38 | ||
39 | if (reg < codec->reg_cache_size) | |
40 | cache[reg] = value; | |
41 | ret = codec->hw_write(codec->control_data, data, 2); | |
42 | if (ret == 2) | |
43 | return 0; | |
44 | if (ret < 0) | |
45 | return ret; | |
46 | else | |
47 | return -EIO; | |
48 | } | |
49 | ||
27ded041 MB |
50 | #if defined(CONFIG_SPI_MASTER) |
51 | static int snd_soc_7_9_spi_write(void *control_data, const char *data, | |
52 | int len) | |
53 | { | |
54 | struct spi_device *spi = control_data; | |
55 | struct spi_transfer t; | |
56 | struct spi_message m; | |
57 | u8 msg[2]; | |
58 | ||
59 | if (len <= 0) | |
60 | return 0; | |
61 | ||
62 | msg[0] = data[0]; | |
63 | msg[1] = data[1]; | |
64 | ||
65 | spi_message_init(&m); | |
66 | memset(&t, 0, (sizeof t)); | |
67 | ||
68 | t.tx_buf = &msg[0]; | |
69 | t.len = len; | |
70 | ||
71 | spi_message_add_tail(&t, &m); | |
72 | spi_sync(spi, &m); | |
73 | ||
74 | return len; | |
75 | } | |
76 | #else | |
77 | #define snd_soc_7_9_spi_write NULL | |
78 | #endif | |
79 | ||
341c9b84 JS |
80 | static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg, |
81 | unsigned int value) | |
82 | { | |
83 | u8 *cache = codec->reg_cache; | |
84 | u8 data[2]; | |
85 | ||
86 | BUG_ON(codec->volatile_register); | |
87 | ||
88 | data[0] = reg & 0xff; | |
89 | data[1] = value & 0xff; | |
90 | ||
91 | if (reg < codec->reg_cache_size) | |
92 | cache[reg] = value; | |
93 | ||
94 | if (codec->hw_write(codec->control_data, data, 2) == 2) | |
95 | return 0; | |
96 | else | |
97 | return -EIO; | |
98 | } | |
99 | ||
100 | static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec, | |
101 | unsigned int reg) | |
102 | { | |
103 | u8 *cache = codec->reg_cache; | |
104 | if (reg >= codec->reg_cache_size) | |
105 | return -1; | |
106 | return cache[reg]; | |
107 | } | |
108 | ||
afa2f106 MB |
109 | static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg, |
110 | unsigned int value) | |
111 | { | |
112 | u16 *reg_cache = codec->reg_cache; | |
113 | u8 data[3]; | |
114 | ||
115 | data[0] = reg; | |
116 | data[1] = (value >> 8) & 0xff; | |
117 | data[2] = value & 0xff; | |
118 | ||
119 | if (!snd_soc_codec_volatile_register(codec, reg)) | |
120 | reg_cache[reg] = value; | |
121 | ||
122 | if (codec->hw_write(codec->control_data, data, 3) == 3) | |
123 | return 0; | |
124 | else | |
125 | return -EIO; | |
126 | } | |
127 | ||
128 | static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec, | |
129 | unsigned int reg) | |
130 | { | |
131 | u16 *cache = codec->reg_cache; | |
132 | ||
133 | if (reg >= codec->reg_cache_size || | |
134 | snd_soc_codec_volatile_register(codec, reg)) | |
135 | return codec->hw_read(codec, reg); | |
136 | else | |
137 | return cache[reg]; | |
138 | } | |
139 | ||
17244c24 | 140 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
afa2f106 MB |
141 | static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec, |
142 | unsigned int r) | |
143 | { | |
144 | struct i2c_msg xfer[2]; | |
145 | u8 reg = r; | |
146 | u16 data; | |
147 | int ret; | |
148 | struct i2c_client *client = codec->control_data; | |
149 | ||
150 | /* Write register */ | |
151 | xfer[0].addr = client->addr; | |
152 | xfer[0].flags = 0; | |
153 | xfer[0].len = 1; | |
154 | xfer[0].buf = ® | |
155 | ||
156 | /* Read data */ | |
157 | xfer[1].addr = client->addr; | |
158 | xfer[1].flags = I2C_M_RD; | |
159 | xfer[1].len = 2; | |
160 | xfer[1].buf = (u8 *)&data; | |
161 | ||
162 | ret = i2c_transfer(client->adapter, xfer, 2); | |
163 | if (ret != 2) { | |
164 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | return (data >> 8) | ((data & 0xff) << 8); | |
169 | } | |
170 | #else | |
171 | #define snd_soc_8_16_read_i2c NULL | |
172 | #endif | |
17a52fd6 MB |
173 | |
174 | static struct { | |
175 | int addr_bits; | |
176 | int data_bits; | |
afa2f106 | 177 | int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int); |
27ded041 | 178 | int (*spi_write)(void *, const char *, int); |
17a52fd6 | 179 | unsigned int (*read)(struct snd_soc_codec *, unsigned int); |
afa2f106 | 180 | unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int); |
17a52fd6 | 181 | } io_types[] = { |
d62ab358 MB |
182 | { |
183 | .addr_bits = 7, .data_bits = 9, | |
184 | .write = snd_soc_7_9_write, .read = snd_soc_7_9_read, | |
8998c899 | 185 | .spi_write = snd_soc_7_9_spi_write, |
d62ab358 MB |
186 | }, |
187 | { | |
188 | .addr_bits = 8, .data_bits = 8, | |
189 | .write = snd_soc_8_8_write, .read = snd_soc_8_8_read, | |
190 | }, | |
191 | { | |
192 | .addr_bits = 8, .data_bits = 16, | |
193 | .write = snd_soc_8_16_write, .read = snd_soc_8_16_read, | |
194 | .i2c_read = snd_soc_8_16_read_i2c, | |
195 | }, | |
17a52fd6 MB |
196 | }; |
197 | ||
198 | /** | |
199 | * snd_soc_codec_set_cache_io: Set up standard I/O functions. | |
200 | * | |
201 | * @codec: CODEC to configure. | |
202 | * @type: Type of cache. | |
203 | * @addr_bits: Number of bits of register address data. | |
204 | * @data_bits: Number of bits of data per register. | |
7084a42b | 205 | * @control: Control bus used. |
17a52fd6 MB |
206 | * |
207 | * Register formats are frequently shared between many I2C and SPI | |
208 | * devices. In order to promote code reuse the ASoC core provides | |
209 | * some standard implementations of CODEC read and write operations | |
210 | * which can be set up using this function. | |
211 | * | |
212 | * The caller is responsible for allocating and initialising the | |
213 | * actual cache. | |
214 | * | |
215 | * Note that at present this code cannot be used by CODECs with | |
216 | * volatile registers. | |
217 | */ | |
218 | int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec, | |
7084a42b MB |
219 | int addr_bits, int data_bits, |
220 | enum snd_soc_control_type control) | |
17a52fd6 MB |
221 | { |
222 | int i; | |
223 | ||
17a52fd6 MB |
224 | for (i = 0; i < ARRAY_SIZE(io_types); i++) |
225 | if (io_types[i].addr_bits == addr_bits && | |
226 | io_types[i].data_bits == data_bits) | |
227 | break; | |
228 | if (i == ARRAY_SIZE(io_types)) { | |
229 | printk(KERN_ERR | |
230 | "No I/O functions for %d bit address %d bit data\n", | |
231 | addr_bits, data_bits); | |
232 | return -EINVAL; | |
233 | } | |
234 | ||
235 | codec->write = io_types[i].write; | |
236 | codec->read = io_types[i].read; | |
237 | ||
7084a42b MB |
238 | switch (control) { |
239 | case SND_SOC_CUSTOM: | |
240 | break; | |
241 | ||
242 | case SND_SOC_I2C: | |
17244c24 | 243 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
7084a42b MB |
244 | codec->hw_write = (hw_write_t)i2c_master_send; |
245 | #endif | |
afa2f106 MB |
246 | if (io_types[i].i2c_read) |
247 | codec->hw_read = io_types[i].i2c_read; | |
7084a42b MB |
248 | break; |
249 | ||
250 | case SND_SOC_SPI: | |
27ded041 MB |
251 | if (io_types[i].spi_write) |
252 | codec->hw_write = io_types[i].spi_write; | |
7084a42b MB |
253 | break; |
254 | } | |
255 | ||
17a52fd6 MB |
256 | return 0; |
257 | } | |
258 | EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io); |