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ASoC: SOF: Intel: hda: Avoid checking jack on system suspend
[mirror_ubuntu-jammy-kernel.git] / sound / soc / sof / intel / hda-dsp.c
CommitLineData
e149ca29 1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
747503b1
LG		 2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
851fd873 18#include <linux/module.h>
747503b1
LG		 19#include <sound/hdaudio_ext.h>
20#include <sound/hda_register.h>
63e51fd3 21#include "../sof-audio.h"
747503b1
LG		 22#include "../ops.h"
23#include "hda.h"
534037fd 24#include "hda-ipc.h"
747503b1 25
851fd873
RS		 26static bool hda_enable_trace_D0I3_S0;
27#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
28module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
29MODULE_PARM_DESC(enable_trace_D0I3_S0,
30 "SOF HDA enable trace when the DSP is in D0I3 in S0");
31#endif
32
747503b1
LG		 33/*
34 * DSP Core control.
35 */
36
37int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
38{
39 u32 adspcs;
40 u32 reset;
41 int ret;
42
43 /* set reset bits for cores */
44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
46 HDA_DSP_REG_ADSPCS,
bed5ed64 47 reset, reset);
747503b1
LG		 48
49 /* poll with timeout to check if operation successful */
50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
51 HDA_DSP_REG_ADSPCS, adspcs,
52 ((adspcs & reset) == reset),
53 HDA_DSP_REG_POLL_INTERVAL_US,
54 HDA_DSP_RESET_TIMEOUT_US);
6a414489
PLB		 55 if (ret < 0) {
56 dev_err(sdev->dev,
57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
58 __func__);
59 return ret;
60 }
747503b1
LG		 61
62 /* has core entered reset ? */
63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
64 HDA_DSP_REG_ADSPCS);
65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
67 dev_err(sdev->dev,
68 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
69 core_mask, adspcs);
70 ret = -EIO;
71 }
72
73 return ret;
74}
75
76int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
77{
78 unsigned int crst;
79 u32 adspcs;
80 int ret;
81
82 /* clear reset bits for cores */
83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
84 HDA_DSP_REG_ADSPCS,
85 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
86 0);
87
88 /* poll with timeout to check if operation successful */
89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
91 HDA_DSP_REG_ADSPCS, adspcs,
92 !(adspcs & crst),
93 HDA_DSP_REG_POLL_INTERVAL_US,
94 HDA_DSP_RESET_TIMEOUT_US);
95
6a414489
PLB		 96 if (ret < 0) {
97 dev_err(sdev->dev,
98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
99 __func__);
100 return ret;
101 }
102
747503b1
LG		 103 /* has core left reset ? */
104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
105 HDA_DSP_REG_ADSPCS);
106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
107 dev_err(sdev->dev,
108 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
109 core_mask, adspcs);
110 ret = -EIO;
111 }
112
113 return ret;
114}
115
116int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
117{
118 /* stall core */
119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
120 HDA_DSP_REG_ADSPCS,
121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
123
124 /* set reset state */
125 return hda_dsp_core_reset_enter(sdev, core_mask);
126}
127
128int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
129{
130 int ret;
131
132 /* leave reset state */
133 ret = hda_dsp_core_reset_leave(sdev, core_mask);
134 if (ret < 0)
135 return ret;
136
137 /* run core */
138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
140 HDA_DSP_REG_ADSPCS,
141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
142 0);
143
144 /* is core now running ? */
145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
146 hda_dsp_core_stall_reset(sdev, core_mask);
147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
148 core_mask);
149 ret = -EIO;
150 }
151
152 return ret;
153}
154
155/*
156 * Power Management.
157 */
158
159int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
160{
161 unsigned int cpa;
162 u32 adspcs;
163 int ret;
164
165 /* update bits */
166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
167 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
168 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
169
170 /* poll with timeout to check if operation successful */
171 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
173 HDA_DSP_REG_ADSPCS, adspcs,
174 (adspcs & cpa) == cpa,
175 HDA_DSP_REG_POLL_INTERVAL_US,
176 HDA_DSP_RESET_TIMEOUT_US);
6a414489
PLB		 177 if (ret < 0) {
178 dev_err(sdev->dev,
179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
180 __func__);
181 return ret;
182 }
747503b1
LG		 183
184 /* did core power up ? */
185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
186 HDA_DSP_REG_ADSPCS);
187 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
188 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
189 dev_err(sdev->dev,
190 "error: power up core failed core_mask %xadspcs 0x%x\n",
191 core_mask, adspcs);
192 ret = -EIO;
193 }
194
195 return ret;
196}
197
198int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
199{
200 u32 adspcs;
6a414489 201 int ret;
747503b1
LG		 202
203 /* update bits */
204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
205 HDA_DSP_REG_ADSPCS,
206 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
207
6a414489 208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
747503b1
LG		 209 HDA_DSP_REG_ADSPCS, adspcs,
210 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
211 HDA_DSP_REG_POLL_INTERVAL_US,
212 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
6a414489
PLB		 213 if (ret < 0)
214 dev_err(sdev->dev,
215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
216 __func__);
217
218 return ret;
747503b1
LG		 219}
220
221bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
222 unsigned int core_mask)
223{
224 int val;
225 bool is_enable;
226
227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
228
805a23de
PK		 229 is_enable = (val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
230 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
231 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
232 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
747503b1
LG		 233
234 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
235 is_enable, core_mask);
236
237 return is_enable;
238}
239
240int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
241{
914fab3b
RS		 242 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
243 const struct sof_intel_dsp_desc *chip = hda->desc;
747503b1
LG		 244 int ret;
245
914fab3b
RS		 246 /* restrict core_mask to host managed cores mask */
247 core_mask &= chip->host_managed_cores_mask;
248
249 /* return if core_mask is not valid or cores are already enabled */
250 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
747503b1
LG		 251 return 0;
252
253 /* power up */
254 ret = hda_dsp_core_power_up(sdev, core_mask);
255 if (ret < 0) {
256 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
257 core_mask);
258 return ret;
259 }
260
261 return hda_dsp_core_run(sdev, core_mask);
262}
263
264int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
265 unsigned int core_mask)
266{
914fab3b
RS		 267 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
268 const struct sof_intel_dsp_desc *chip = hda->desc;
747503b1
LG		 269 int ret;
270
914fab3b
RS		 271 /* restrict core_mask to host managed cores mask */
272 core_mask &= chip->host_managed_cores_mask;
273
274 /* return if core_mask is not valid */
275 if (!core_mask)
276 return 0;
277
747503b1
LG		 278 /* place core in reset prior to power down */
279 ret = hda_dsp_core_stall_reset(sdev, core_mask);
280 if (ret < 0) {
281 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
282 core_mask);
283 return ret;
284 }
285
286 /* power down core */
287 ret = hda_dsp_core_power_down(sdev, core_mask);
288 if (ret < 0) {
289 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
290 core_mask, ret);
291 return ret;
292 }
293
294 /* make sure we are in OFF state */
295 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
296 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
297 core_mask, ret);
298 ret = -EIO;
299 }
300
301 return ret;
302}
303
304void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
305{
306 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
307 const struct sof_intel_dsp_desc *chip = hda->desc;
308
309 /* enable IPC DONE and BUSY interrupts */
310 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
311 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
312 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
313
314 /* enable IPC interrupt */
315 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
316 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
317}
318
319void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
320{
321 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
322 const struct sof_intel_dsp_desc *chip = hda->desc;
323
324 /* disable IPC interrupt */
325 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
326 HDA_DSP_ADSPIC_IPC, 0);
327
328 /* disable IPC BUSY and DONE interrupt */
329 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
330 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
331}
332
65c56f5d 333static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
62f8f766
KJ		 334{
335 struct hdac_bus *bus = sof_to_bus(sdev);
65c56f5d 336 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
62f8f766
KJ		 337
338 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
339 if (!retry--)
340 return -ETIMEDOUT;
341 usleep_range(10, 15);
342 }
343
344 return 0;
345}
346
534037fd
KJ		 347static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
348{
349 struct sof_ipc_pm_gate pm_gate;
350 struct sof_ipc_reply reply;
351
352 memset(&pm_gate, 0, sizeof(pm_gate));
353
354 /* configure pm_gate ipc message */
355 pm_gate.hdr.size = sizeof(pm_gate);
356 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
357 pm_gate.flags = flags;
358
359 /* send pm_gate ipc to dsp */
63e51fd3
RS		 360 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
361 &pm_gate, sizeof(pm_gate), &reply,
362 sizeof(reply));
534037fd
KJ		 363}
364
61e285ca 365static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
62f8f766
KJ		 366{
367 struct hdac_bus *bus = sof_to_bus(sdev);
62f8f766 368 int ret;
62f8f766
KJ		 369
370 /* Write to D0I3C after Command-In-Progress bit is cleared */
65c56f5d 371 ret = hda_dsp_wait_d0i3c_done(sdev);
62f8f766 372 if (ret < 0) {
aae7c82d 373 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
62f8f766
KJ		 374 return ret;
375 }
376
377 /* Update D0I3C register */
62f8f766
KJ		 378 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
379
380 /* Wait for cmd in progress to be cleared before exiting the function */
65c56f5d 381 ret = hda_dsp_wait_d0i3c_done(sdev);
62f8f766 382 if (ret < 0) {
aae7c82d 383 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
62f8f766
KJ		 384 return ret;
385 }
386
387 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
388 snd_hdac_chip_readb(bus, VS_D0I3C));
389
61e285ca
RS		 390 return 0;
391}
534037fd 392
61e285ca
RS		 393static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
394 const struct sof_dsp_power_state *target_state)
395{
396 u32 flags = 0;
397 int ret;
398 u8 value = 0;
399
400 /*
401 * Sanity check for illegal state transitions
402 * The only allowed transitions are:
403 * 1. D3 -> D0I0
404 * 2. D0I0 -> D0I3
405 * 3. D0I3 -> D0I0
406 */
407 switch (sdev->dsp_power_state.state) {
408 case SOF_DSP_PM_D0:
409 /* Follow the sequence below for D0 substate transitions */
410 break;
411 case SOF_DSP_PM_D3:
412 /* Follow regular flow for D3 -> D0 transition */
413 return 0;
414 default:
415 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
416 sdev->dsp_power_state.state, target_state->state);
417 return -EINVAL;
418 }
419
420 /* Set flags and register value for D0 target substate */
421 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
422 value = SOF_HDA_VS_D0I3C_I3;
423
851fd873 424 /*
79560b8a
MR		 425 * Trace DMA need to be disabled when the DSP enters
426 * D0I3 for S0Ix suspend, but it can be kept enabled
427 * when the DSP enters D0I3 while the system is in S0
428 * for debug purpose.
851fd873 429 */
79560b8a
MR		 430 if (!sdev->dtrace_is_supported ||
431 !hda_enable_trace_D0I3_S0 ||
851fd873
RS		 432 sdev->system_suspend_target != SOF_SUSPEND_NONE)
433 flags = HDA_PM_NO_DMA_TRACE;
61e285ca
RS		 434 } else {
435 /* prevent power gating in D0I0 */
436 flags = HDA_PM_PPG;
437 }
438
439 /* update D0I3C register */
440 ret = hda_dsp_update_d0i3c_register(sdev, value);
534037fd 441 if (ret < 0)
61e285ca
RS		 442 return ret;
443
444 /*
445 * Notify the DSP of the state change.
446 * If this IPC fails, revert the D0I3C register update in order
447 * to prevent partial state change.
448 */
449 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
450 if (ret < 0) {
534037fd
KJ		 451 dev_err(sdev->dev,
452 "error: PM_GATE ipc error %d\n", ret);
61e285ca
RS		 453 goto revert;
454 }
455
456 return ret;
457
458revert:
459 /* fallback to the previous register value */
460 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
461
462 /*
463 * This can fail but return the IPC error to signal that
464 * the state change failed.
465 */
466 hda_dsp_update_d0i3c_register(sdev, value);
534037fd
KJ		 467
468 return ret;
62f8f766
KJ		 469}
470
66de6beb
RS		 471/* helper to log DSP state */
472static void hda_dsp_state_log(struct snd_sof_dev *sdev)
473{
474 switch (sdev->dsp_power_state.state) {
475 case SOF_DSP_PM_D0:
476 switch (sdev->dsp_power_state.substate) {
477 case SOF_HDA_DSP_PM_D0I0:
478 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
479 break;
480 case SOF_HDA_DSP_PM_D0I3:
481 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
482 break;
483 default:
484 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
485 sdev->dsp_power_state.substate);
486 break;
487 }
488 break;
489 case SOF_DSP_PM_D1:
490 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
491 break;
492 case SOF_DSP_PM_D2:
493 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
494 break;
495 case SOF_DSP_PM_D3_HOT:
496 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n");
497 break;
498 case SOF_DSP_PM_D3:
499 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
500 break;
501 case SOF_DSP_PM_D3_COLD:
502 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n");
503 break;
504 default:
505 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
506 sdev->dsp_power_state.state);
507 break;
508 }
509}
510
61e285ca
RS		 511/*
512 * All DSP power state transitions are initiated by the driver.
513 * If the requested state change fails, the error is simply returned.
514 * Further state transitions are attempted only when the set_power_save() op
515 * is called again either because of a new IPC sent to the DSP or
516 * during system suspend/resume.
517 */
518int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
519 const struct sof_dsp_power_state *target_state)
520{
521 int ret = 0;
522
851fd873
RS		 523 /*
524 * When the DSP is already in D0I3 and the target state is D0I3,
525 * it could be the case that the DSP is in D0I3 during S0
526 * and the system is suspending to S0Ix. Therefore,
527 * hda_dsp_set_D0_state() must be called to disable trace DMA
528 * by sending the PM_GATE IPC to the FW.
529 */
530 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
531 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
532 goto set_state;
533
534 /*
535 * For all other cases, return without doing anything if
536 * the DSP is already in the target state.
537 */
61e285ca
RS		 538 if (target_state->state == sdev->dsp_power_state.state &&
539 target_state->substate == sdev->dsp_power_state.substate)
540 return 0;
541
851fd873 542set_state:
61e285ca
RS		 543 switch (target_state->state) {
544 case SOF_DSP_PM_D0:
545 ret = hda_dsp_set_D0_state(sdev, target_state);
546 break;
547 case SOF_DSP_PM_D3:
548 /* The only allowed transition is: D0I0 -> D3 */
549 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
550 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
551 break;
552
553 dev_err(sdev->dev,
554 "error: transition from %d to %d not allowed\n",
555 sdev->dsp_power_state.state, target_state->state);
556 return -EINVAL;
557 default:
558 dev_err(sdev->dev, "error: target state unsupported %d\n",
559 target_state->state);
560 return -EINVAL;
561 }
562 if (ret < 0) {
563 dev_err(sdev->dev,
564 "failed to set requested target DSP state %d substate %d\n",
565 target_state->state, target_state->substate);
566 return ret;
567 }
568
569 sdev->dsp_power_state = *target_state;
66de6beb 570 hda_dsp_state_log(sdev);
61e285ca
RS		 571 return ret;
572}
573
574/*
575 * Audio DSP states may transform as below:-
576 *
207bf12f
RS		 577 * Opportunistic D0I3 in S0
578 * Runtime +---------------------+ Delayed D0i3 work timeout
61e285ca 579 * suspend | +--------------------+
207bf12f 580 * +------------+ D0I0(active) | |
61e285ca 581 * | | <---------------+ |
207bf12f
RS		 582 * | +--------> | New IPC | |
583 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
584 * | |resume | | | | | |
585 * | | | | | | | |
586 * | | System| | | | | |
587 * | | resume| | S3/S0IX | | | |
588 * | | | | suspend | | S0IX | |
61e285ca
RS		 589 * | | | | | |suspend | |
590 * | | | | | | | |
591 * | | | | | | | |
592 * +-v---+-----------+--v-------+ | | +------+----v----+
593 * | | | +-----------> |
207bf12f
RS		 594 * | D3 (suspended) | | | D0I3 |
595 * | | +--------------+ |
596 * | | System resume | |
597 * +----------------------------+ +----------------+
61e285ca 598 *
207bf12f
RS		 599 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
600 * ignored the suspend trigger. Otherwise the DSP
601 * is in D3.
61e285ca
RS		 602 */
603
1c38c922 604static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
747503b1
LG		 605{
606 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
607 const struct sof_intel_dsp_desc *chip = hda->desc;
608#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
609 struct hdac_bus *bus = sof_to_bus(sdev);
610#endif
611 int ret;
612
3eadff56
PLB		 613 hda_sdw_int_enable(sdev, false);
614
747503b1
LG		 615 /* disable IPC interrupts */
616 hda_dsp_ipc_int_disable(sdev);
617
618#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
fd15f2f5 619 if (runtime_suspend)
31ba0c07 620 hda_codec_jack_wake_enable(sdev, true);
fd15f2f5 621
747503b1
LG		 622 /* power down all hda link */
623 snd_hdac_ext_bus_link_power_down_all(bus);
624#endif
625
626 /* power down DSP */
64b96917 627 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
747503b1
LG		 628 if (ret < 0) {
629 dev_err(sdev->dev,
630 "error: failed to power down core during suspend\n");
631 return ret;
632 }
633
747503b1 634 /* disable ppcap interrupt */
24b6ff68
ZY		 635 hda_dsp_ctrl_ppcap_enable(sdev, false);
636 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
747503b1 637
9a50ee58
ZY		 638 /* disable hda bus irq and streams */
639 hda_dsp_ctrl_stop_chip(sdev);
747503b1
LG		 640
641 /* disable LP retention mode */
642 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
643 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
644
645 /* reset controller */
646 ret = hda_dsp_ctrl_link_reset(sdev, true);
647 if (ret < 0) {
648 dev_err(sdev->dev,
649 "error: failed to reset controller during suspend\n");
650 return ret;
651 }
652
816938b2
KV		 653 /* display codec can powered off after link reset */
654 hda_codec_i915_display_power(sdev, false);
655
747503b1
LG		 656 return 0;
657}
658
fd15f2f5 659static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
747503b1
LG		 660{
661#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
662 struct hdac_bus *bus = sof_to_bus(sdev);
663 struct hdac_ext_link *hlink = NULL;
664#endif
665 int ret;
666
816938b2
KV		 667 /* display codec must be powered before link reset */
668 hda_codec_i915_display_power(sdev, true);
669
747503b1
LG		 670 /*
671 * clear TCSEL to clear playback on some HD Audio
672 * codecs. PCI TCSEL is defined in the Intel manuals.
673 */
674 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
675
747503b1
LG		 676 /* reset and start hda controller */
677 ret = hda_dsp_ctrl_init_chip(sdev, true);
678 if (ret < 0) {
679 dev_err(sdev->dev,
680 "error: failed to start controller after resume\n");
681 return ret;
682 }
683
fd15f2f5
RW		 684#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
685 /* check jack status */
31ba0c07
KHF		 686 if (runtime_resume) {
687 hda_codec_jack_wake_enable(sdev, false);
ef4d764c
KHF		 688 if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
689 hda_codec_jack_check(sdev);
31ba0c07 690 }
6aa232e1
RW		 691
692 /* turn off the links that were off before suspend */
693 list_for_each_entry(hlink, &bus->hlink_list, list) {
694 if (!hlink->ref_count)
695 snd_hdac_ext_bus_link_power_down(hlink);
696 }
697
698 /* check dma status and clean up CORB/RIRB buffers */
699 if (!bus->cmd_dma_state)
700 snd_hdac_bus_stop_cmd_io(bus);
24b6ff68 701#endif
747503b1
LG		 702
703 /* enable ppcap interrupt */
704 hda_dsp_ctrl_ppcap_enable(sdev, true);
705 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
747503b1 706
747503b1
LG		 707 return 0;
708}
709
710int hda_dsp_resume(struct snd_sof_dev *sdev)
711{
16299326 712 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
66e40876 713 struct pci_dev *pci = to_pci_dev(sdev->dev);
61e285ca
RS		 714 const struct sof_dsp_power_state target_state = {
715 .state = SOF_DSP_PM_D0,
716 .substate = SOF_HDA_DSP_PM_D0I0,
717 };
195f1019
MR		 718#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
719 struct hdac_bus *bus = sof_to_bus(sdev);
720 struct hdac_ext_link *hlink = NULL;
721#endif
61e285ca
RS		 722 int ret;
723
724 /* resume from D0I3 */
725 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
816938b2
KV		 726 hda_codec_i915_display_power(sdev, true);
727
195f1019
MR		 728#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
729 /* power up links that were active before suspend */
730 list_for_each_entry(hlink, &bus->hlink_list, list) {
731 if (hlink->ref_count) {
732 ret = snd_hdac_ext_bus_link_power_up(hlink);
733 if (ret < 0) {
734 dev_dbg(sdev->dev,
735 "error %x in %s: failed to power up links",
736 ret, __func__);
737 return ret;
738 }
739 }
740 }
741
742 /* set up CORB/RIRB buffers if was on before suspend */
743 if (bus->cmd_dma_state)
744 snd_hdac_bus_init_cmd_io(bus);
745#endif
746
61e285ca 747 /* Set DSP power state */
787c5214 748 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
61e285ca
RS		 749 if (ret < 0) {
750 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
751 target_state.state, target_state.substate);
752 return ret;
753 }
66e40876 754
16299326
KJ		 755 /* restore L1SEN bit */
756 if (hda->l1_support_changed)
757 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
758 HDA_VS_INTEL_EM2,
759 HDA_VS_INTEL_EM2_L1SEN, 0);
760
66e40876
KJ		 761 /* restore and disable the system wakeup */
762 pci_restore_state(pci);
763 disable_irq_wake(pci->irq);
764 return 0;
765 }
766
747503b1 767 /* init hda controller. DSP cores will be powered up during fw boot */
61e285ca
RS		 768 ret = hda_resume(sdev, false);
769 if (ret < 0)
770 return ret;
771
787c5214 772 return snd_sof_dsp_set_power_state(sdev, &target_state);
747503b1
LG		 773}
774
775int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
776{
61e285ca
RS		 777 const struct sof_dsp_power_state target_state = {
778 .state = SOF_DSP_PM_D0,
779 };
780 int ret;
781
747503b1 782 /* init hda controller. DSP cores will be powered up during fw boot */
61e285ca
RS		 783 ret = hda_resume(sdev, true);
784 if (ret < 0)
785 return ret;
786
787c5214 787 return snd_sof_dsp_set_power_state(sdev, &target_state);
747503b1
LG		 788}
789
87a6fe80
KV		 790int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
791{
792 struct hdac_bus *hbus = sof_to_bus(sdev);
793
794 if (hbus->codec_powered) {
795 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
796 (unsigned int)hbus->codec_powered);
797 return -EBUSY;
798 }
799
800 return 0;
801}
802
1c38c922 803int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
747503b1 804{
61e285ca
RS		 805 const struct sof_dsp_power_state target_state = {
806 .state = SOF_DSP_PM_D3,
807 };
808 int ret;
809
747503b1 810 /* stop hda controller and power dsp off */
61e285ca
RS		 811 ret = hda_suspend(sdev, true);
812 if (ret < 0)
813 return ret;
814
787c5214 815 return snd_sof_dsp_set_power_state(sdev, &target_state);
747503b1
LG		 816}
817
61e285ca 818int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
747503b1 819{
16299326 820 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
747503b1 821 struct hdac_bus *bus = sof_to_bus(sdev);
66e40876 822 struct pci_dev *pci = to_pci_dev(sdev->dev);
61e285ca
RS		 823 const struct sof_dsp_power_state target_dsp_state = {
824 .state = target_state,
825 .substate = target_state == SOF_DSP_PM_D0 ?
826 SOF_HDA_DSP_PM_D0I3 : 0,
827 };
747503b1
LG		 828 int ret;
829
63e51fd3
RS		 830 /* cancel any attempt for DSP D0I3 */
831 cancel_delayed_work_sync(&hda->d0i3_work);
832
61e285ca 833 if (target_state == SOF_DSP_PM_D0) {
816938b2
KV		 834 /* we can't keep a wakeref to display driver at suspend */
835 hda_codec_i915_display_power(sdev, false);
836
61e285ca 837 /* Set DSP power state */
787c5214 838 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
61e285ca
RS		 839 if (ret < 0) {
840 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
841 target_dsp_state.state,
842 target_dsp_state.substate);
843 return ret;
844 }
845
16299326
KJ		 846 /* enable L1SEN to make sure the system can enter S0Ix */
847 hda->l1_support_changed =
848 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
849 HDA_VS_INTEL_EM2,
850 HDA_VS_INTEL_EM2_L1SEN,
851 HDA_VS_INTEL_EM2_L1SEN);
852
195f1019
MR		 853#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
854 /* stop the CORB/RIRB DMA if it is On */
855 if (bus->cmd_dma_state)
856 snd_hdac_bus_stop_cmd_io(bus);
857
858 /* no link can be powered in s0ix state */
859 ret = snd_hdac_ext_bus_link_power_down_all(bus);
860 if (ret < 0) {
861 dev_dbg(sdev->dev,
862 "error %d in %s: failed to power down links",
863 ret, __func__);
864 return ret;
865 }
866#endif
867
66e40876
KJ		 868 /* enable the system waking up via IPC IRQ */
869 enable_irq_wake(pci->irq);
870 pci_save_state(pci);
871 return 0;
872 }
873
747503b1 874 /* stop hda controller and power dsp off */
1c38c922 875 ret = hda_suspend(sdev, false);
747503b1
LG		 876 if (ret < 0) {
877 dev_err(bus->dev, "error: suspending dsp\n");
878 return ret;
879 }
880
787c5214 881 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
747503b1 882}
ed3baacd 883
7077a07a 884int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
ed3baacd 885{
7077a07a 886#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
a3ebccb5 887 struct hdac_bus *bus = sof_to_bus(sdev);
7077a07a 888 struct snd_soc_pcm_runtime *rtd;
a3ebccb5 889 struct hdac_ext_stream *stream;
7077a07a 890 struct hdac_ext_link *link;
a3ebccb5 891 struct hdac_stream *s;
7077a07a
RS		 892 const char *name;
893 int stream_tag;
7077a07a 894
ed3baacd
RS		 895 /* set internal flag for BE */
896 list_for_each_entry(s, &bus->stream_list, list) {
897 stream = stream_to_hdac_ext_stream(s);
a3ebccb5 898
7077a07a 899 /*
934bf822
RW		 900 * clear stream. This should already be taken care for running
901 * streams when the SUSPEND trigger is called. But paused
902 * streams do not get suspended, so this needs to be done
903 * explicitly during suspend.
7077a07a
RS		 904 */
905 if (stream->link_substream) {
1205300a 906 rtd = asoc_substream_to_rtd(stream->link_substream);
be3e8de7 907 name = asoc_rtd_to_codec(rtd, 0)->component->name;
7077a07a
RS		 908 link = snd_hdac_ext_bus_get_link(bus, name);
909 if (!link)
910 return -EINVAL;
810dbea3
RW		 911
912 stream->link_prepared = 0;
913
914 if (hdac_stream(stream)->direction ==
915 SNDRV_PCM_STREAM_CAPTURE)
916 continue;
917
7077a07a
RS		 918 stream_tag = hdac_stream(stream)->stream_tag;
919 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
7077a07a 920 }
ed3baacd 921 }
a3ebccb5 922#endif
7077a07a 923 return 0;
ed3baacd 924}
63e51fd3
RS		 925
926void hda_dsp_d0i3_work(struct work_struct *work)
927{
928 struct sof_intel_hda_dev *hdev = container_of(work,
929 struct sof_intel_hda_dev,
930 d0i3_work.work);
931 struct hdac_bus *bus = &hdev->hbus.core;
932 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
933 struct sof_dsp_power_state target_state;
934 int ret;
935
936 target_state.state = SOF_DSP_PM_D0;
937
938 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
939 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
940 target_state.substate = SOF_HDA_DSP_PM_D0I3;
941 else
942 target_state.substate = SOF_HDA_DSP_PM_D0I0;
943
944 /* remain in D0I0 */
945 if (target_state.substate == SOF_HDA_DSP_PM_D0I0)
946 return;
947
948 /* This can fail but error cannot be propagated */
787c5214 949 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
63e51fd3
RS		 950 if (ret < 0)
951 dev_err_ratelimited(sdev->dev,
952 "error: failed to set DSP state %d substate %d\n",
953 target_state.state, target_state.substate);
954}
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