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ASoC: SOF: fix runtime pm usage mismatch after probe errors
[mirror_ubuntu-kernels.git] / sound / soc / sof / sof-priv.h
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e149ca29 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
c16211d6
LG		 2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOUND_SOC_SOF_PRIV_H
12#define __SOUND_SOC_SOF_PRIV_H
13
14#include <linux/device.h>
c16211d6 15#include <sound/hdaudio.h>
c16211d6 16#include <sound/sof.h>
c16211d6
LG		 17#include <sound/sof/info.h>
18#include <sound/sof/pm.h>
c16211d6 19#include <sound/sof/trace.h>
c16211d6 20#include <uapi/sound/sof/fw.h>
e984f3ef 21#include <sound/sof/ext_manifest.h>
c16211d6
LG		 22
23/* debug flags */
2ab4c50f 24#define SOF_DBG_ENABLE_TRACE BIT(0)
fbfa22ec
RS		 25#define SOF_DBG_RETAIN_CTX BIT(1) /* prevent DSP D3 on FW exception */
26
27#define SOF_DBG_DUMP_REGS BIT(0)
28#define SOF_DBG_DUMP_MBOX BIT(1)
29#define SOF_DBG_DUMP_TEXT BIT(2)
30#define SOF_DBG_DUMP_PCI BIT(3)
8f7ef6fc
RS		 31#define SOF_DBG_DUMP_FORCE_ERR_LEVEL BIT(4) /* used to dump dsp status with error log level */
32
2ab4c50f
PLB		 33
34/* global debug state set by SOF_DBG_ flags */
35extern int sof_core_debug;
c16211d6
LG		 36
37/* max BARs mmaped devices can use */
38#define SND_SOF_BARS 8
39
40/* time in ms for runtime suspend delay */
41#define SND_SOF_SUSPEND_DELAY_MS 2000
42
43/* DMA buffer size for trace */
44#define DMA_BUF_SIZE_FOR_TRACE (PAGE_SIZE * 16)
45
c16211d6
LG		 46#define SOF_IPC_DSP_REPLY 0
47#define SOF_IPC_HOST_REPLY 1
48
49/* convenience constructor for DAI driver streams */
50#define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
51 {.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
52 .rates = srates, .formats = sfmt}
53
54#define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
55 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
56
091c12e1
RS		 57#define ENABLE_DEBUGFS_CACHEBUF \
58 (IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) || \
59 IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST))
60
0dcdf842
GL		 61/* So far the primary core on all DSPs has ID 0 */
62#define SOF_DSP_PRIMARY_CORE 0
63
700d1677
RS		 64/* DSP power state */
65enum sof_dsp_power_states {
66 SOF_DSP_PM_D0,
67 SOF_DSP_PM_D1,
68 SOF_DSP_PM_D2,
69 SOF_DSP_PM_D3_HOT,
70 SOF_DSP_PM_D3,
71 SOF_DSP_PM_D3_COLD,
72};
73
61e285ca
RS		 74struct sof_dsp_power_state {
75 u32 state;
76 u32 substate; /* platform-specific */
4c19030c
KJ		 77};
78
043ae13b
RS		 79/* System suspend target state */
80enum sof_system_suspend_state {
81 SOF_SUSPEND_NONE = 0,
82 SOF_SUSPEND_S0IX,
83 SOF_SUSPEND_S3,
84};
85
c16211d6
LG		 86struct snd_sof_dev;
87struct snd_sof_ipc_msg;
88struct snd_sof_ipc;
89struct snd_sof_debugfs_map;
90struct snd_soc_tplg_ops;
91struct snd_soc_component;
92struct snd_sof_pdata;
93
94/*
95 * SOF DSP HW abstraction operations.
96 * Used to abstract DSP HW architecture and any IO busses between host CPU
97 * and DSP device(s).
98 */
99struct snd_sof_dsp_ops {
100
7edb3051 101 /* probe/remove/shutdown */
c16211d6
LG		 102 int (*probe)(struct snd_sof_dev *sof_dev); /* mandatory */
103 int (*remove)(struct snd_sof_dev *sof_dev); /* optional */
7edb3051 104 int (*shutdown)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6
LG		 105
106 /* DSP core boot / reset */
107 int (*run)(struct snd_sof_dev *sof_dev); /* mandatory */
a70eb708 108 int (*stall)(struct snd_sof_dev *sof_dev, unsigned int core_mask); /* optional */
c16211d6
LG		 109 int (*reset)(struct snd_sof_dev *sof_dev); /* optional */
110 int (*core_power_up)(struct snd_sof_dev *sof_dev,
111 unsigned int core_mask); /* optional */
112 int (*core_power_down)(struct snd_sof_dev *sof_dev,
113 unsigned int core_mask); /* optional */
114
115 /*
116 * Register IO: only used by respective drivers themselves,
117 * TODO: consider removing these operations and calling respective
118 * implementations directly
119 */
120 void (*write)(struct snd_sof_dev *sof_dev, void __iomem *addr,
121 u32 value); /* optional */
122 u32 (*read)(struct snd_sof_dev *sof_dev,
123 void __iomem *addr); /* optional */
124 void (*write64)(struct snd_sof_dev *sof_dev, void __iomem *addr,
125 u64 value); /* optional */
126 u64 (*read64)(struct snd_sof_dev *sof_dev,
127 void __iomem *addr); /* optional */
128
129 /* memcpy IO */
130 void (*block_read)(struct snd_sof_dev *sof_dev, u32 bar,
131 u32 offset, void *dest,
132 size_t size); /* mandatory */
133 void (*block_write)(struct snd_sof_dev *sof_dev, u32 bar,
134 u32 offset, void *src,
135 size_t size); /* mandatory */
136
137 /* doorbell */
138 irqreturn_t (*irq_handler)(int irq, void *context); /* optional */
139 irqreturn_t (*irq_thread)(int irq, void *context); /* optional */
140
141 /* ipc */
142 int (*send_msg)(struct snd_sof_dev *sof_dev,
143 struct snd_sof_ipc_msg *msg); /* mandatory */
144
145 /* FW loading */
146 int (*load_firmware)(struct snd_sof_dev *sof_dev); /* mandatory */
147 int (*load_module)(struct snd_sof_dev *sof_dev,
148 struct snd_sof_mod_hdr *hdr); /* optional */
149 /*
150 * FW ready checks for ABI compatibility and creates
151 * memory windows at first boot
152 */
8692d498 153 int (*fw_ready)(struct snd_sof_dev *sdev, u32 msg_id); /* mandatory */
c16211d6
LG		 154
155 /* connect pcm substream to a host stream */
156 int (*pcm_open)(struct snd_sof_dev *sdev,
157 struct snd_pcm_substream *substream); /* optional */
158 /* disconnect pcm substream to a host stream */
159 int (*pcm_close)(struct snd_sof_dev *sdev,
160 struct snd_pcm_substream *substream); /* optional */
161
162 /* host stream hw params */
163 int (*pcm_hw_params)(struct snd_sof_dev *sdev,
164 struct snd_pcm_substream *substream,
165 struct snd_pcm_hw_params *params,
166 struct sof_ipc_stream_params *ipc_params); /* optional */
167
93146bc2
RS		 168 /* host stream hw_free */
169 int (*pcm_hw_free)(struct snd_sof_dev *sdev,
170 struct snd_pcm_substream *substream); /* optional */
171
c16211d6
LG		 172 /* host stream trigger */
173 int (*pcm_trigger)(struct snd_sof_dev *sdev,
174 struct snd_pcm_substream *substream,
175 int cmd); /* optional */
176
177 /* host stream pointer */
178 snd_pcm_uframes_t (*pcm_pointer)(struct snd_sof_dev *sdev,
179 struct snd_pcm_substream *substream); /* optional */
180
e145e9af
CR		 181#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
182 /* Except for probe_pointer, all probe ops are mandatory */
183 int (*probe_assign)(struct snd_sof_dev *sdev,
184 struct snd_compr_stream *cstream,
185 struct snd_soc_dai *dai); /* mandatory */
186 int (*probe_free)(struct snd_sof_dev *sdev,
187 struct snd_compr_stream *cstream,
188 struct snd_soc_dai *dai); /* mandatory */
189 int (*probe_set_params)(struct snd_sof_dev *sdev,
190 struct snd_compr_stream *cstream,
191 struct snd_compr_params *params,
192 struct snd_soc_dai *dai); /* mandatory */
193 int (*probe_trigger)(struct snd_sof_dev *sdev,
194 struct snd_compr_stream *cstream, int cmd,
195 struct snd_soc_dai *dai); /* mandatory */
196 int (*probe_pointer)(struct snd_sof_dev *sdev,
197 struct snd_compr_stream *cstream,
198 struct snd_compr_tstamp *tstamp,
199 struct snd_soc_dai *dai); /* optional */
200#endif
201
c16211d6
LG		 202 /* host read DSP stream data */
203 void (*ipc_msg_data)(struct snd_sof_dev *sdev,
204 struct snd_pcm_substream *substream,
205 void *p, size_t sz); /* mandatory */
206
207 /* host configure DSP HW parameters */
208 int (*ipc_pcm_params)(struct snd_sof_dev *sdev,
209 struct snd_pcm_substream *substream,
210 const struct sof_ipc_pcm_params_reply *reply); /* mandatory */
211
212 /* pre/post firmware run */
213 int (*pre_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
214 int (*post_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
215
e984f3ef
FO		 216 /* parse platform specific extended manifest, optional */
217 int (*parse_platform_ext_manifest)(struct snd_sof_dev *sof_dev,
218 const struct sof_ext_man_elem_header *hdr);
219
c16211d6 220 /* DSP PM */
61e285ca
RS		 221 int (*suspend)(struct snd_sof_dev *sof_dev,
222 u32 target_state); /* optional */
c16211d6 223 int (*resume)(struct snd_sof_dev *sof_dev); /* optional */
1c38c922 224 int (*runtime_suspend)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6 225 int (*runtime_resume)(struct snd_sof_dev *sof_dev); /* optional */
62fde977 226 int (*runtime_idle)(struct snd_sof_dev *sof_dev); /* optional */
7077a07a 227 int (*set_hw_params_upon_resume)(struct snd_sof_dev *sdev); /* optional */
e8f112d8 228 int (*set_power_state)(struct snd_sof_dev *sdev,
61e285ca 229 const struct sof_dsp_power_state *target_state); /* optional */
c16211d6
LG		 230
231 /* DSP clocking */
232 int (*set_clk)(struct snd_sof_dev *sof_dev, u32 freq); /* optional */
233
234 /* debug */
235 const struct snd_sof_debugfs_map *debug_map; /* optional */
236 int debug_map_count; /* optional */
237 void (*dbg_dump)(struct snd_sof_dev *sof_dev,
238 u32 flags); /* optional */
5e4a27fd 239 void (*ipc_dump)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6
LG		 240
241 /* host DMA trace initialization */
242 int (*trace_init)(struct snd_sof_dev *sdev,
243 u32 *stream_tag); /* optional */
244 int (*trace_release)(struct snd_sof_dev *sdev); /* optional */
245 int (*trace_trigger)(struct snd_sof_dev *sdev,
246 int cmd); /* optional */
247
ce8234a6
DB		 248 /* misc */
249 int (*get_bar_index)(struct snd_sof_dev *sdev,
250 u32 type); /* optional */
bb9c93f5 251 int (*get_mailbox_offset)(struct snd_sof_dev *sdev);/* mandatory for common loader code */
e17422cd
DB		 252 int (*get_window_offset)(struct snd_sof_dev *sdev,
253 u32 id);/* mandatory for common loader code */
bb9c93f5 254
285880a2
DB		 255 /* machine driver ops */
256 int (*machine_register)(struct snd_sof_dev *sdev,
257 void *pdata); /* optional */
258 void (*machine_unregister)(struct snd_sof_dev *sdev,
259 void *pdata); /* optional */
260 void (*machine_select)(struct snd_sof_dev *sdev); /* optional */
261 void (*set_mach_params)(const struct snd_soc_acpi_mach *mach,
262 struct device *dev); /* optional */
263
c16211d6
LG		 264 /* DAI ops */
265 struct snd_soc_dai_driver *drv;
266 int num_drv;
27e322fa
PLB		 267
268 /* ALSA HW info flags, will be stored in snd_pcm_runtime.hw.info */
269 u32 hw_info;
0f501c7c
PLB		 270
271 const struct sof_arch_ops *arch_ops;
c16211d6
LG		 272};
273
274/* DSP architecture specific callbacks for oops and stack dumps */
275struct sof_arch_ops {
276 void (*dsp_oops)(struct snd_sof_dev *sdev, void *oops);
277 void (*dsp_stack)(struct snd_sof_dev *sdev, void *oops,
278 u32 *stack, u32 stack_words);
279};
280
0f501c7c 281#define sof_arch_ops(sdev) ((sdev)->pdata->desc->ops->arch_ops)
c16211d6
LG		 282
283/* DSP device HW descriptor mapping between bus ID and ops */
284struct sof_ops_table {
285 const struct sof_dev_desc *desc;
286 const struct snd_sof_dsp_ops *ops;
287};
288
289enum sof_dfsentry_type {
290 SOF_DFSENTRY_TYPE_IOMEM = 0,
291 SOF_DFSENTRY_TYPE_BUF,
292};
293
294enum sof_debugfs_access_type {
295 SOF_DEBUGFS_ACCESS_ALWAYS = 0,
296 SOF_DEBUGFS_ACCESS_D0_ONLY,
297};
298
299/* FS entry for debug files that can expose DSP memories, registers */
300struct snd_sof_dfsentry {
c16211d6 301 size_t size;
5b10b629 302 size_t buf_data_size; /* length of buffered data for file read operation */
c16211d6
LG		 303 enum sof_dfsentry_type type;
304 /*
305 * access_type specifies if the
306 * memory -> DSP resource (memory, register etc) is always accessible
307 * or if it is accessible only when the DSP is in D0.
308 */
309 enum sof_debugfs_access_type access_type;
091c12e1 310#if ENABLE_DEBUGFS_CACHEBUF
c16211d6
LG		 311 char *cache_buf; /* buffer to cache the contents of debugfs memory */
312#endif
313 struct snd_sof_dev *sdev;
314 struct list_head list; /* list in sdev dfsentry list */
315 union {
316 void __iomem *io_mem;
317 void *buf;
318 };
319};
320
321/* Debug mapping for any DSP memory or registers that can used for debug */
322struct snd_sof_debugfs_map {
323 const char *name;
324 u32 bar;
325 u32 offset;
326 u32 size;
327 /*
328 * access_type specifies if the memory is always accessible
329 * or if it is accessible only when the DSP is in D0.
330 */
331 enum sof_debugfs_access_type access_type;
332};
333
334/* mailbox descriptor, used for host <-> DSP IPC */
335struct snd_sof_mailbox {
336 u32 offset;
337 size_t size;
338};
339
340/* IPC message descriptor for host <-> DSP IO */
341struct snd_sof_ipc_msg {
342 /* message data */
343 u32 header;
344 void *msg_data;
345 void *reply_data;
346 size_t msg_size;
347 size_t reply_size;
348 int reply_error;
349
350 wait_queue_head_t waitq;
351 bool ipc_complete;
352};
353
6ca5cecb
RS		 354enum snd_sof_fw_state {
355 SOF_FW_BOOT_NOT_STARTED = 0,
356 SOF_FW_BOOT_PREPARE,
357 SOF_FW_BOOT_IN_PROGRESS,
358 SOF_FW_BOOT_FAILED,
359 SOF_FW_BOOT_READY_FAILED, /* firmware booted but fw_ready op failed */
360 SOF_FW_BOOT_COMPLETE,
361};
362
c16211d6
LG		 363/*
364 * SOF Device Level.
365 */
366struct snd_sof_dev {
367 struct device *dev;
368 spinlock_t ipc_lock; /* lock for IPC users */
369 spinlock_t hw_lock; /* lock for HW IO access */
370
371 /*
372 * ASoC components. plat_drv fields are set dynamically so
373 * can't use const
374 */
375 struct snd_soc_component_driver plat_drv;
376
61e285ca
RS		 377 /* current DSP power state */
378 struct sof_dsp_power_state dsp_power_state;
8b66d7c5
KJ		 379 /* mutex to protect the dsp_power_state access */
380 struct mutex power_state_access;
043ae13b
RS		 381
382 /* Intended power target of system suspend */
383 enum sof_system_suspend_state system_suspend_target;
4c19030c 384
c16211d6
LG		 385 /* DSP firmware boot */
386 wait_queue_head_t boot_wait;
6ca5cecb 387 enum snd_sof_fw_state fw_state;
f738d815 388 bool first_boot;
c16211d6
LG		 389
390 /* work queue in case the probe is implemented in two steps */
391 struct work_struct probe_work;
271d9373 392 bool probe_completed;
c16211d6
LG		 393
394 /* DSP HW differentiation */
395 struct snd_sof_pdata *pdata;
396
397 /* IPC */
398 struct snd_sof_ipc *ipc;
399 struct snd_sof_mailbox dsp_box; /* DSP initiated IPC */
400 struct snd_sof_mailbox host_box; /* Host initiated IPC */
401 struct snd_sof_mailbox stream_box; /* Stream position update */
e17b7389 402 struct snd_sof_mailbox debug_box; /* Debug info updates */
c16211d6 403 struct snd_sof_ipc_msg *msg;
c16211d6
LG		 404 int ipc_irq;
405 u32 next_comp_id; /* monotonic - reset during S3 */
406
407 /* memory bases for mmaped DSPs - set by dsp_init() */
408 void __iomem *bar[SND_SOF_BARS]; /* DSP base address */
409 int mmio_bar;
410 int mailbox_bar;
411 size_t dsp_oops_offset;
412
413 /* debug */
414 struct dentry *debugfs_root;
415 struct list_head dfsentry_list;
416
417 /* firmware loader */
418 struct snd_dma_buffer dmab;
419 struct snd_dma_buffer dmab_bdl;
420 struct sof_ipc_fw_ready fw_ready;
421 struct sof_ipc_fw_version fw_version;
59283959 422 struct sof_ipc_cc_version *cc_version;
c16211d6
LG		 423
424 /* topology */
425 struct snd_soc_tplg_ops *tplg_ops;
426 struct list_head pcm_list;
427 struct list_head kcontrol_list;
428 struct list_head widget_list;
429 struct list_head dai_list;
430 struct list_head route_list;
431 struct snd_soc_component *component;
432 u32 enabled_cores_mask; /* keep track of enabled cores */
433
434 /* FW configuration */
c16211d6
LG		 435 struct sof_ipc_window *info_window;
436
437 /* IPC timeouts in ms */
438 int ipc_timeout;
439 int boot_timeout;
440
e145e9af
CR		 441#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
442 unsigned int extractor_stream_tag;
443#endif
444
c16211d6
LG		 445 /* DMA for Trace */
446 struct snd_dma_buffer dmatb;
447 struct snd_dma_buffer dmatp;
448 int dma_trace_pages;
449 wait_queue_head_t trace_sleep;
450 u32 host_offset;
f738d815
GL		 451 bool dtrace_is_supported; /* set with Kconfig or module parameter */
452 bool dtrace_is_enabled;
453 bool dtrace_error;
454 bool dtrace_draining;
ec9025e5 455
672ff5e3 456 bool msi_enabled;
c16211d6
LG		 457
458 void *private; /* core does not touch this */
459};
460
461/*
462 * Device Level.
463 */
464
465int snd_sof_device_probe(struct device *dev, struct snd_sof_pdata *plat_data);
466int snd_sof_device_remove(struct device *dev);
7edb3051 467int snd_sof_device_shutdown(struct device *dev);
271d9373 468bool snd_sof_device_probe_completed(struct device *dev);
c16211d6
LG		 469
470int snd_sof_runtime_suspend(struct device *dev);
471int snd_sof_runtime_resume(struct device *dev);
62fde977 472int snd_sof_runtime_idle(struct device *dev);
c16211d6
LG		 473int snd_sof_resume(struct device *dev);
474int snd_sof_suspend(struct device *dev);
3541aef1 475int snd_sof_dsp_power_down_notify(struct snd_sof_dev *sdev);
0b50b3b1
KJ		 476int snd_sof_prepare(struct device *dev);
477void snd_sof_complete(struct device *dev);
c16211d6
LG		 478
479void snd_sof_new_platform_drv(struct snd_sof_dev *sdev);
480
3e625794 481int snd_sof_create_page_table(struct device *dev,
c16211d6
LG		 482 struct snd_dma_buffer *dmab,
483 unsigned char *page_table, size_t size);
484
485/*
486 * Firmware loading.
487 */
488int snd_sof_load_firmware(struct snd_sof_dev *sdev);
489int snd_sof_load_firmware_raw(struct snd_sof_dev *sdev);
490int snd_sof_load_firmware_memcpy(struct snd_sof_dev *sdev);
491int snd_sof_run_firmware(struct snd_sof_dev *sdev);
492int snd_sof_parse_module_memcpy(struct snd_sof_dev *sdev,
493 struct snd_sof_mod_hdr *module);
494void snd_sof_fw_unload(struct snd_sof_dev *sdev);
495int snd_sof_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 bar, u32 offset);
496
497/*
498 * IPC low level APIs.
499 */
500struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev);
501void snd_sof_ipc_free(struct snd_sof_dev *sdev);
d7a1ed26 502void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id);
c16211d6
LG		 503void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev);
504int snd_sof_ipc_stream_pcm_params(struct snd_sof_dev *sdev,
505 struct sof_ipc_pcm_params *params);
506int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox,
507 size_t dspbox_size, u32 hostbox,
508 size_t hostbox_size);
509int snd_sof_ipc_valid(struct snd_sof_dev *sdev);
510int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header,
511 void *msg_data, size_t msg_bytes, void *reply_data,
512 size_t reply_bytes);
63e51fd3
RS		 513int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, u32 header,
514 void *msg_data, size_t msg_bytes,
515 void *reply_data, size_t reply_bytes);
c16211d6
LG		 516
517/*
518 * Trace/debug
519 */
520int snd_sof_init_trace(struct snd_sof_dev *sdev);
521void snd_sof_release_trace(struct snd_sof_dev *sdev);
522void snd_sof_free_trace(struct snd_sof_dev *sdev);
523int snd_sof_dbg_init(struct snd_sof_dev *sdev);
524void snd_sof_free_debug(struct snd_sof_dev *sdev);
525int snd_sof_debugfs_io_item(struct snd_sof_dev *sdev,
526 void __iomem *base, size_t size,
527 const char *name,
528 enum sof_debugfs_access_type access_type);
529int snd_sof_debugfs_buf_item(struct snd_sof_dev *sdev,
530 void *base, size_t size,
5c9714f6 531 const char *name, mode_t mode);
c16211d6
LG		 532int snd_sof_trace_update_pos(struct snd_sof_dev *sdev,
533 struct sof_ipc_dma_trace_posn *posn);
534void snd_sof_trace_notify_for_error(struct snd_sof_dev *sdev);
535void snd_sof_get_status(struct snd_sof_dev *sdev, u32 panic_code,
536 u32 tracep_code, void *oops,
537 struct sof_ipc_panic_info *panic_info,
538 void *stack, size_t stack_words);
539int snd_sof_init_trace_ipc(struct snd_sof_dev *sdev);
9a06508b 540void snd_sof_handle_fw_exception(struct snd_sof_dev *sdev);
5b10b629 541int snd_sof_dbg_memory_info_init(struct snd_sof_dev *sdev);
c16211d6
LG		 542
543/*
544 * Platform specific ops.
545 */
39118ce5 546extern struct snd_compress_ops sof_compressed_ops;
c16211d6 547
c16211d6
LG		 548/*
549 * DSP Architectures.
550 */
551static inline void sof_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack,
552 u32 stack_words)
553{
c16211d6
LG		 554 sof_arch_ops(sdev)->dsp_stack(sdev, oops, stack, stack_words);
555}
556
557static inline void sof_oops(struct snd_sof_dev *sdev, void *oops)
558{
559 if (sof_arch_ops(sdev)->dsp_oops)
560 sof_arch_ops(sdev)->dsp_oops(sdev, oops);
561}
562
563extern const struct sof_arch_ops sof_xtensa_arch_ops;
564
565/*
566 * Utilities
567 */
568void sof_io_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value);
569void sof_io_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value);
570u32 sof_io_read(struct snd_sof_dev *sdev, void __iomem *addr);
571u64 sof_io_read64(struct snd_sof_dev *sdev, void __iomem *addr);
572void sof_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
573 void *message, size_t bytes);
574void sof_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
575 void *message, size_t bytes);
576void sof_block_write(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *src,
577 size_t size);
578void sof_block_read(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *dest,
579 size_t size);
580
83ee7ab1
DB		 581int sof_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
582
c16211d6
LG		 583void intel_ipc_msg_data(struct snd_sof_dev *sdev,
584 struct snd_pcm_substream *substream,
585 void *p, size_t sz);
586int intel_ipc_pcm_params(struct snd_sof_dev *sdev,
587 struct snd_pcm_substream *substream,
588 const struct sof_ipc_pcm_params_reply *reply);
589
590int intel_pcm_open(struct snd_sof_dev *sdev,
591 struct snd_pcm_substream *substream);
592int intel_pcm_close(struct snd_sof_dev *sdev,
593 struct snd_pcm_substream *substream);
594
285880a2
DB		 595int sof_machine_check(struct snd_sof_dev *sdev);
596
776100a4
PLB		 597#define sof_dev_dbg_or_err(dev, is_err, fmt, ...) \
598 do { \
599 if (is_err) \
600 dev_err(dev, "error: " fmt, __VA_ARGS__); \
601 else \
602 dev_dbg(dev, fmt, __VA_ARGS__); \
603 } while (0)
604
c16211d6 605#endif
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