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ASoC: SOF: Intel: hda: add namespace for hda-codec functionality
[mirror_ubuntu-kernels.git] / sound / soc / sof / sof-priv.h
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c16211d6
LG		 1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOUND_SOC_SOF_PRIV_H
12#define __SOUND_SOC_SOF_PRIV_H
13
14#include <linux/device.h>
c16211d6 15#include <sound/hdaudio.h>
c16211d6 16#include <sound/sof.h>
c16211d6
LG		 17#include <sound/sof/info.h>
18#include <sound/sof/pm.h>
c16211d6 19#include <sound/sof/trace.h>
c16211d6
LG		 20#include <uapi/sound/sof/fw.h>
21
22/* debug flags */
2ab4c50f
PLB		 23#define SOF_DBG_ENABLE_TRACE BIT(0)
24#define SOF_DBG_REGS BIT(1)
25#define SOF_DBG_MBOX BIT(2)
26#define SOF_DBG_TEXT BIT(3)
27#define SOF_DBG_PCI BIT(4)
9a06508b 28#define SOF_DBG_RETAIN_CTX BIT(5) /* prevent DSP D3 on FW exception */
2ab4c50f
PLB		 29
30/* global debug state set by SOF_DBG_ flags */
31extern int sof_core_debug;
c16211d6
LG		 32
33/* max BARs mmaped devices can use */
34#define SND_SOF_BARS 8
35
36/* time in ms for runtime suspend delay */
37#define SND_SOF_SUSPEND_DELAY_MS 2000
38
39/* DMA buffer size for trace */
40#define DMA_BUF_SIZE_FOR_TRACE (PAGE_SIZE * 16)
41
c16211d6
LG		 42#define SOF_IPC_DSP_REPLY 0
43#define SOF_IPC_HOST_REPLY 1
44
45/* convenience constructor for DAI driver streams */
46#define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
47 {.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
48 .rates = srates, .formats = sfmt}
49
50#define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
51 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
52
091c12e1
RS		 53#define ENABLE_DEBUGFS_CACHEBUF \
54 (IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) || \
55 IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST))
56
4c19030c
KJ		 57/* DSP D0ix sub-state */
58enum sof_d0_substate {
59 SOF_DSP_D0I0 = 0, /* DSP default D0 substate */
60 SOF_DSP_D0I3, /* DSP D0i3(low power) substate*/
61};
62
c16211d6
LG		 63struct snd_sof_dev;
64struct snd_sof_ipc_msg;
65struct snd_sof_ipc;
66struct snd_sof_debugfs_map;
67struct snd_soc_tplg_ops;
68struct snd_soc_component;
69struct snd_sof_pdata;
70
71/*
72 * SOF DSP HW abstraction operations.
73 * Used to abstract DSP HW architecture and any IO busses between host CPU
74 * and DSP device(s).
75 */
76struct snd_sof_dsp_ops {
77
78 /* probe and remove */
79 int (*probe)(struct snd_sof_dev *sof_dev); /* mandatory */
80 int (*remove)(struct snd_sof_dev *sof_dev); /* optional */
81
82 /* DSP core boot / reset */
83 int (*run)(struct snd_sof_dev *sof_dev); /* mandatory */
84 int (*stall)(struct snd_sof_dev *sof_dev); /* optional */
85 int (*reset)(struct snd_sof_dev *sof_dev); /* optional */
86 int (*core_power_up)(struct snd_sof_dev *sof_dev,
87 unsigned int core_mask); /* optional */
88 int (*core_power_down)(struct snd_sof_dev *sof_dev,
89 unsigned int core_mask); /* optional */
90
91 /*
92 * Register IO: only used by respective drivers themselves,
93 * TODO: consider removing these operations and calling respective
94 * implementations directly
95 */
96 void (*write)(struct snd_sof_dev *sof_dev, void __iomem *addr,
97 u32 value); /* optional */
98 u32 (*read)(struct snd_sof_dev *sof_dev,
99 void __iomem *addr); /* optional */
100 void (*write64)(struct snd_sof_dev *sof_dev, void __iomem *addr,
101 u64 value); /* optional */
102 u64 (*read64)(struct snd_sof_dev *sof_dev,
103 void __iomem *addr); /* optional */
104
105 /* memcpy IO */
106 void (*block_read)(struct snd_sof_dev *sof_dev, u32 bar,
107 u32 offset, void *dest,
108 size_t size); /* mandatory */
109 void (*block_write)(struct snd_sof_dev *sof_dev, u32 bar,
110 u32 offset, void *src,
111 size_t size); /* mandatory */
112
113 /* doorbell */
114 irqreturn_t (*irq_handler)(int irq, void *context); /* optional */
115 irqreturn_t (*irq_thread)(int irq, void *context); /* optional */
116
117 /* ipc */
118 int (*send_msg)(struct snd_sof_dev *sof_dev,
119 struct snd_sof_ipc_msg *msg); /* mandatory */
120
121 /* FW loading */
122 int (*load_firmware)(struct snd_sof_dev *sof_dev); /* mandatory */
123 int (*load_module)(struct snd_sof_dev *sof_dev,
124 struct snd_sof_mod_hdr *hdr); /* optional */
125 /*
126 * FW ready checks for ABI compatibility and creates
127 * memory windows at first boot
128 */
8692d498 129 int (*fw_ready)(struct snd_sof_dev *sdev, u32 msg_id); /* mandatory */
c16211d6
LG		 130
131 /* connect pcm substream to a host stream */
132 int (*pcm_open)(struct snd_sof_dev *sdev,
133 struct snd_pcm_substream *substream); /* optional */
134 /* disconnect pcm substream to a host stream */
135 int (*pcm_close)(struct snd_sof_dev *sdev,
136 struct snd_pcm_substream *substream); /* optional */
137
138 /* host stream hw params */
139 int (*pcm_hw_params)(struct snd_sof_dev *sdev,
140 struct snd_pcm_substream *substream,
141 struct snd_pcm_hw_params *params,
142 struct sof_ipc_stream_params *ipc_params); /* optional */
143
93146bc2
RS		 144 /* host stream hw_free */
145 int (*pcm_hw_free)(struct snd_sof_dev *sdev,
146 struct snd_pcm_substream *substream); /* optional */
147
c16211d6
LG		 148 /* host stream trigger */
149 int (*pcm_trigger)(struct snd_sof_dev *sdev,
150 struct snd_pcm_substream *substream,
151 int cmd); /* optional */
152
153 /* host stream pointer */
154 snd_pcm_uframes_t (*pcm_pointer)(struct snd_sof_dev *sdev,
155 struct snd_pcm_substream *substream); /* optional */
156
157 /* host read DSP stream data */
158 void (*ipc_msg_data)(struct snd_sof_dev *sdev,
159 struct snd_pcm_substream *substream,
160 void *p, size_t sz); /* mandatory */
161
162 /* host configure DSP HW parameters */
163 int (*ipc_pcm_params)(struct snd_sof_dev *sdev,
164 struct snd_pcm_substream *substream,
165 const struct sof_ipc_pcm_params_reply *reply); /* mandatory */
166
167 /* pre/post firmware run */
168 int (*pre_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
169 int (*post_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
170
171 /* DSP PM */
1c38c922 172 int (*suspend)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6 173 int (*resume)(struct snd_sof_dev *sof_dev); /* optional */
1c38c922 174 int (*runtime_suspend)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6 175 int (*runtime_resume)(struct snd_sof_dev *sof_dev); /* optional */
62fde977 176 int (*runtime_idle)(struct snd_sof_dev *sof_dev); /* optional */
7077a07a 177 int (*set_hw_params_upon_resume)(struct snd_sof_dev *sdev); /* optional */
e8f112d8
KJ		 178 int (*set_power_state)(struct snd_sof_dev *sdev,
179 enum sof_d0_substate d0_substate); /* optional */
c16211d6
LG		 180
181 /* DSP clocking */
182 int (*set_clk)(struct snd_sof_dev *sof_dev, u32 freq); /* optional */
183
184 /* debug */
185 const struct snd_sof_debugfs_map *debug_map; /* optional */
186 int debug_map_count; /* optional */
187 void (*dbg_dump)(struct snd_sof_dev *sof_dev,
188 u32 flags); /* optional */
5e4a27fd 189 void (*ipc_dump)(struct snd_sof_dev *sof_dev); /* optional */
c16211d6
LG		 190
191 /* host DMA trace initialization */
192 int (*trace_init)(struct snd_sof_dev *sdev,
193 u32 *stream_tag); /* optional */
194 int (*trace_release)(struct snd_sof_dev *sdev); /* optional */
195 int (*trace_trigger)(struct snd_sof_dev *sdev,
196 int cmd); /* optional */
197
ce8234a6
DB		 198 /* misc */
199 int (*get_bar_index)(struct snd_sof_dev *sdev,
200 u32 type); /* optional */
bb9c93f5 201 int (*get_mailbox_offset)(struct snd_sof_dev *sdev);/* mandatory for common loader code */
e17422cd
DB		 202 int (*get_window_offset)(struct snd_sof_dev *sdev,
203 u32 id);/* mandatory for common loader code */
bb9c93f5 204
285880a2
DB		 205 /* machine driver ops */
206 int (*machine_register)(struct snd_sof_dev *sdev,
207 void *pdata); /* optional */
208 void (*machine_unregister)(struct snd_sof_dev *sdev,
209 void *pdata); /* optional */
210 void (*machine_select)(struct snd_sof_dev *sdev); /* optional */
211 void (*set_mach_params)(const struct snd_soc_acpi_mach *mach,
212 struct device *dev); /* optional */
213
c16211d6
LG		 214 /* DAI ops */
215 struct snd_soc_dai_driver *drv;
216 int num_drv;
27e322fa
PLB		 217
218 /* ALSA HW info flags, will be stored in snd_pcm_runtime.hw.info */
219 u32 hw_info;
c16211d6
LG		 220};
221
222/* DSP architecture specific callbacks for oops and stack dumps */
223struct sof_arch_ops {
224 void (*dsp_oops)(struct snd_sof_dev *sdev, void *oops);
225 void (*dsp_stack)(struct snd_sof_dev *sdev, void *oops,
226 u32 *stack, u32 stack_words);
227};
228
229#define sof_arch_ops(sdev) ((sdev)->pdata->desc->arch_ops)
230
231/* DSP device HW descriptor mapping between bus ID and ops */
232struct sof_ops_table {
233 const struct sof_dev_desc *desc;
234 const struct snd_sof_dsp_ops *ops;
235};
236
237enum sof_dfsentry_type {
238 SOF_DFSENTRY_TYPE_IOMEM = 0,
239 SOF_DFSENTRY_TYPE_BUF,
240};
241
242enum sof_debugfs_access_type {
243 SOF_DEBUGFS_ACCESS_ALWAYS = 0,
244 SOF_DEBUGFS_ACCESS_D0_ONLY,
245};
246
247/* FS entry for debug files that can expose DSP memories, registers */
248struct snd_sof_dfsentry {
c16211d6
LG		 249 size_t size;
250 enum sof_dfsentry_type type;
251 /*
252 * access_type specifies if the
253 * memory -> DSP resource (memory, register etc) is always accessible
254 * or if it is accessible only when the DSP is in D0.
255 */
256 enum sof_debugfs_access_type access_type;
091c12e1 257#if ENABLE_DEBUGFS_CACHEBUF
c16211d6
LG		 258 char *cache_buf; /* buffer to cache the contents of debugfs memory */
259#endif
260 struct snd_sof_dev *sdev;
261 struct list_head list; /* list in sdev dfsentry list */
262 union {
263 void __iomem *io_mem;
264 void *buf;
265 };
266};
267
268/* Debug mapping for any DSP memory or registers that can used for debug */
269struct snd_sof_debugfs_map {
270 const char *name;
271 u32 bar;
272 u32 offset;
273 u32 size;
274 /*
275 * access_type specifies if the memory is always accessible
276 * or if it is accessible only when the DSP is in D0.
277 */
278 enum sof_debugfs_access_type access_type;
279};
280
281/* mailbox descriptor, used for host <-> DSP IPC */
282struct snd_sof_mailbox {
283 u32 offset;
284 size_t size;
285};
286
287/* IPC message descriptor for host <-> DSP IO */
288struct snd_sof_ipc_msg {
289 /* message data */
290 u32 header;
291 void *msg_data;
292 void *reply_data;
293 size_t msg_size;
294 size_t reply_size;
295 int reply_error;
296
297 wait_queue_head_t waitq;
298 bool ipc_complete;
299};
300
6ca5cecb
RS		 301enum snd_sof_fw_state {
302 SOF_FW_BOOT_NOT_STARTED = 0,
303 SOF_FW_BOOT_PREPARE,
304 SOF_FW_BOOT_IN_PROGRESS,
305 SOF_FW_BOOT_FAILED,
306 SOF_FW_BOOT_READY_FAILED, /* firmware booted but fw_ready op failed */
307 SOF_FW_BOOT_COMPLETE,
308};
309
c16211d6
LG		 310/*
311 * SOF Device Level.
312 */
313struct snd_sof_dev {
314 struct device *dev;
315 spinlock_t ipc_lock; /* lock for IPC users */
316 spinlock_t hw_lock; /* lock for HW IO access */
317
318 /*
319 * ASoC components. plat_drv fields are set dynamically so
320 * can't use const
321 */
322 struct snd_soc_component_driver plat_drv;
323
4c19030c
KJ		 324 /* power states related */
325 enum sof_d0_substate d0_substate;
7367d309
KJ		 326 /* flag to track if the intended power target of suspend is S0ix */
327 bool s0_suspend;
4c19030c 328
c16211d6
LG		 329 /* DSP firmware boot */
330 wait_queue_head_t boot_wait;
6ca5cecb 331 enum snd_sof_fw_state fw_state;
c16211d6
LG		 332 u32 first_boot;
333
334 /* work queue in case the probe is implemented in two steps */
335 struct work_struct probe_work;
336
337 /* DSP HW differentiation */
338 struct snd_sof_pdata *pdata;
339
340 /* IPC */
341 struct snd_sof_ipc *ipc;
342 struct snd_sof_mailbox dsp_box; /* DSP initiated IPC */
343 struct snd_sof_mailbox host_box; /* Host initiated IPC */
344 struct snd_sof_mailbox stream_box; /* Stream position update */
345 struct snd_sof_ipc_msg *msg;
c16211d6
LG		 346 int ipc_irq;
347 u32 next_comp_id; /* monotonic - reset during S3 */
348
349 /* memory bases for mmaped DSPs - set by dsp_init() */
350 void __iomem *bar[SND_SOF_BARS]; /* DSP base address */
351 int mmio_bar;
352 int mailbox_bar;
353 size_t dsp_oops_offset;
354
355 /* debug */
356 struct dentry *debugfs_root;
357 struct list_head dfsentry_list;
358
359 /* firmware loader */
360 struct snd_dma_buffer dmab;
361 struct snd_dma_buffer dmab_bdl;
362 struct sof_ipc_fw_ready fw_ready;
363 struct sof_ipc_fw_version fw_version;
59283959 364 struct sof_ipc_cc_version *cc_version;
c16211d6
LG		 365
366 /* topology */
367 struct snd_soc_tplg_ops *tplg_ops;
368 struct list_head pcm_list;
369 struct list_head kcontrol_list;
370 struct list_head widget_list;
371 struct list_head dai_list;
372 struct list_head route_list;
373 struct snd_soc_component *component;
374 u32 enabled_cores_mask; /* keep track of enabled cores */
375
376 /* FW configuration */
377 struct sof_ipc_dma_buffer_data *info_buffer;
378 struct sof_ipc_window *info_window;
379
380 /* IPC timeouts in ms */
381 int ipc_timeout;
382 int boot_timeout;
383
384 /* Wait queue for code loading */
385 wait_queue_head_t waitq;
386 int code_loading;
387
388 /* DMA for Trace */
389 struct snd_dma_buffer dmatb;
390 struct snd_dma_buffer dmatp;
391 int dma_trace_pages;
392 wait_queue_head_t trace_sleep;
393 u32 host_offset;
2ab4c50f 394 u32 dtrace_is_supported; /* set with Kconfig or module parameter */
c16211d6
LG		 395 u32 dtrace_is_enabled;
396 u32 dtrace_error;
ec9025e5
KV		 397 u32 dtrace_draining;
398
672ff5e3 399 bool msi_enabled;
c16211d6
LG		 400
401 void *private; /* core does not touch this */
402};
403
404/*
405 * Device Level.
406 */
407
408int snd_sof_device_probe(struct device *dev, struct snd_sof_pdata *plat_data);
409int snd_sof_device_remove(struct device *dev);
410
411int snd_sof_runtime_suspend(struct device *dev);
412int snd_sof_runtime_resume(struct device *dev);
62fde977 413int snd_sof_runtime_idle(struct device *dev);
c16211d6
LG		 414int snd_sof_resume(struct device *dev);
415int snd_sof_suspend(struct device *dev);
0b50b3b1
KJ		 416int snd_sof_prepare(struct device *dev);
417void snd_sof_complete(struct device *dev);
60125286
KJ		 418int snd_sof_set_d0_substate(struct snd_sof_dev *sdev,
419 enum sof_d0_substate d0_substate);
c16211d6
LG		 420
421void snd_sof_new_platform_drv(struct snd_sof_dev *sdev);
422
3e625794 423int snd_sof_create_page_table(struct device *dev,
c16211d6
LG		 424 struct snd_dma_buffer *dmab,
425 unsigned char *page_table, size_t size);
426
427/*
428 * Firmware loading.
429 */
430int snd_sof_load_firmware(struct snd_sof_dev *sdev);
431int snd_sof_load_firmware_raw(struct snd_sof_dev *sdev);
432int snd_sof_load_firmware_memcpy(struct snd_sof_dev *sdev);
433int snd_sof_run_firmware(struct snd_sof_dev *sdev);
434int snd_sof_parse_module_memcpy(struct snd_sof_dev *sdev,
435 struct snd_sof_mod_hdr *module);
436void snd_sof_fw_unload(struct snd_sof_dev *sdev);
437int snd_sof_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 bar, u32 offset);
438
439/*
440 * IPC low level APIs.
441 */
442struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev);
443void snd_sof_ipc_free(struct snd_sof_dev *sdev);
444int snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id);
445void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev);
446int snd_sof_ipc_stream_pcm_params(struct snd_sof_dev *sdev,
447 struct sof_ipc_pcm_params *params);
448int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox,
449 size_t dspbox_size, u32 hostbox,
450 size_t hostbox_size);
451int snd_sof_ipc_valid(struct snd_sof_dev *sdev);
452int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header,
453 void *msg_data, size_t msg_bytes, void *reply_data,
454 size_t reply_bytes);
c16211d6
LG		 455
456/*
457 * Trace/debug
458 */
459int snd_sof_init_trace(struct snd_sof_dev *sdev);
460void snd_sof_release_trace(struct snd_sof_dev *sdev);
461void snd_sof_free_trace(struct snd_sof_dev *sdev);
462int snd_sof_dbg_init(struct snd_sof_dev *sdev);
463void snd_sof_free_debug(struct snd_sof_dev *sdev);
464int snd_sof_debugfs_io_item(struct snd_sof_dev *sdev,
465 void __iomem *base, size_t size,
466 const char *name,
467 enum sof_debugfs_access_type access_type);
468int snd_sof_debugfs_buf_item(struct snd_sof_dev *sdev,
469 void *base, size_t size,
5c9714f6 470 const char *name, mode_t mode);
c16211d6
LG		 471int snd_sof_trace_update_pos(struct snd_sof_dev *sdev,
472 struct sof_ipc_dma_trace_posn *posn);
473void snd_sof_trace_notify_for_error(struct snd_sof_dev *sdev);
474void snd_sof_get_status(struct snd_sof_dev *sdev, u32 panic_code,
475 u32 tracep_code, void *oops,
476 struct sof_ipc_panic_info *panic_info,
477 void *stack, size_t stack_words);
478int snd_sof_init_trace_ipc(struct snd_sof_dev *sdev);
9a06508b 479void snd_sof_handle_fw_exception(struct snd_sof_dev *sdev);
c16211d6
LG		 480
481/*
482 * Platform specific ops.
483 */
484extern struct snd_compr_ops sof_compressed_ops;
485
c16211d6
LG		 486/*
487 * DSP Architectures.
488 */
489static inline void sof_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack,
490 u32 stack_words)
491{
c16211d6
LG		 492 sof_arch_ops(sdev)->dsp_stack(sdev, oops, stack, stack_words);
493}
494
495static inline void sof_oops(struct snd_sof_dev *sdev, void *oops)
496{
497 if (sof_arch_ops(sdev)->dsp_oops)
498 sof_arch_ops(sdev)->dsp_oops(sdev, oops);
499}
500
501extern const struct sof_arch_ops sof_xtensa_arch_ops;
502
503/*
504 * Utilities
505 */
506void sof_io_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value);
507void sof_io_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value);
508u32 sof_io_read(struct snd_sof_dev *sdev, void __iomem *addr);
509u64 sof_io_read64(struct snd_sof_dev *sdev, void __iomem *addr);
510void sof_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
511 void *message, size_t bytes);
512void sof_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
513 void *message, size_t bytes);
514void sof_block_write(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *src,
515 size_t size);
516void sof_block_read(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *dest,
517 size_t size);
518
83ee7ab1
DB		 519int sof_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
520
c16211d6
LG		 521void intel_ipc_msg_data(struct snd_sof_dev *sdev,
522 struct snd_pcm_substream *substream,
523 void *p, size_t sz);
524int intel_ipc_pcm_params(struct snd_sof_dev *sdev,
525 struct snd_pcm_substream *substream,
526 const struct sof_ipc_pcm_params_reply *reply);
527
528int intel_pcm_open(struct snd_sof_dev *sdev,
529 struct snd_pcm_substream *substream);
530int intel_pcm_close(struct snd_sof_dev *sdev,
531 struct snd_pcm_substream *substream);
532
285880a2
DB		 533int sof_machine_check(struct snd_sof_dev *sdev);
534
c16211d6 535#endif
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