]>
Commit | Line | Data |
---|---|---|
e657c18a PLB |
1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
2 | // | |
3 | // This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | // redistributing this file, you may do so under either license. | |
5 | // | |
6 | // Copyright(c) 2018 Intel Corporation. All rights reserved. | |
7 | // | |
8 | // Author: Pan Xiuli <xiuli.pan@linux.intel.com> | |
9 | // | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <sound/sof.h> | |
13 | #include <sound/sof/xtensa.h> | |
14 | #include "../sof-priv.h" | |
15 | ||
16 | struct xtensa_exception_cause { | |
17 | u32 id; | |
18 | const char *msg; | |
19 | const char *description; | |
20 | }; | |
21 | ||
22 | /* | |
23 | * From 4.4.1.5 table 4-64 Exception Causes of Xtensa | |
24 | * Instruction Set Architecture (ISA) Reference Manual | |
25 | */ | |
26 | static const struct xtensa_exception_cause xtensa_exception_causes[] = { | |
27 | {0, "IllegalInstructionCause", "Illegal instruction"}, | |
28 | {1, "SyscallCause", "SYSCALL instruction"}, | |
29 | {2, "InstructionFetchErrorCause", | |
30 | "Processor internal physical address or data error during instruction fetch"}, | |
31 | {3, "LoadStoreErrorCause", | |
32 | "Processor internal physical address or data error during load or store"}, | |
33 | {4, "Level1InterruptCause", | |
34 | "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"}, | |
35 | {5, "AllocaCause", | |
36 | "MOVSP instruction, if caller’s registers are not in the register file"}, | |
37 | {6, "IntegerDivideByZeroCause", | |
38 | "QUOS, QUOU, REMS, or REMU divisor operand is zero"}, | |
39 | {8, "PrivilegedCause", | |
40 | "Attempt to execute a privileged operation when CRING ? 0"}, | |
41 | {9, "LoadStoreAlignmentCause", "Load or store to an unaligned address"}, | |
42 | {12, "InstrPIFDataErrorCause", | |
43 | "PIF data error during instruction fetch"}, | |
44 | {13, "LoadStorePIFDataErrorCause", | |
45 | "Synchronous PIF data error during LoadStore access"}, | |
46 | {14, "InstrPIFAddrErrorCause", | |
47 | "PIF address error during instruction fetch"}, | |
48 | {15, "LoadStorePIFAddrErrorCause", | |
49 | "Synchronous PIF address error during LoadStore access"}, | |
50 | {16, "InstTLBMissCause", "Error during Instruction TLB refill"}, | |
51 | {17, "InstTLBMultiHitCause", | |
52 | "Multiple instruction TLB entries matched"}, | |
53 | {18, "InstFetchPrivilegeCause", | |
54 | "An instruction fetch referenced a virtual address at a ring level less than CRING"}, | |
55 | {20, "InstFetchProhibitedCause", | |
56 | "An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch"}, | |
57 | {24, "LoadStoreTLBMissCause", | |
58 | "Error during TLB refill for a load or store"}, | |
59 | {25, "LoadStoreTLBMultiHitCause", | |
60 | "Multiple TLB entries matched for a load or store"}, | |
61 | {26, "LoadStorePrivilegeCause", | |
62 | "A load or store referenced a virtual address at a ring level less than CRING"}, | |
63 | {28, "LoadProhibitedCause", | |
64 | "A load referenced a page mapped with an attribute that does not permit loads"}, | |
65 | {32, "Coprocessor0Disabled", | |
66 | "Coprocessor 0 instruction when cp0 disabled"}, | |
67 | {33, "Coprocessor1Disabled", | |
68 | "Coprocessor 1 instruction when cp1 disabled"}, | |
69 | {34, "Coprocessor2Disabled", | |
70 | "Coprocessor 2 instruction when cp2 disabled"}, | |
71 | {35, "Coprocessor3Disabled", | |
72 | "Coprocessor 3 instruction when cp3 disabled"}, | |
73 | {36, "Coprocessor4Disabled", | |
74 | "Coprocessor 4 instruction when cp4 disabled"}, | |
75 | {37, "Coprocessor5Disabled", | |
76 | "Coprocessor 5 instruction when cp5 disabled"}, | |
77 | {38, "Coprocessor6Disabled", | |
78 | "Coprocessor 6 instruction when cp6 disabled"}, | |
79 | {39, "Coprocessor7Disabled", | |
80 | "Coprocessor 7 instruction when cp7 disabled"}, | |
81 | }; | |
82 | ||
83 | /* only need xtensa atm */ | |
84 | static void xtensa_dsp_oops(struct snd_sof_dev *sdev, void *oops) | |
85 | { | |
86 | struct sof_ipc_dsp_oops_xtensa *xoops = oops; | |
87 | int i; | |
88 | ||
89 | dev_err(sdev->dev, "error: DSP Firmware Oops\n"); | |
90 | for (i = 0; i < ARRAY_SIZE(xtensa_exception_causes); i++) { | |
91 | if (xtensa_exception_causes[i].id == xoops->exccause) { | |
92 | dev_err(sdev->dev, "error: Exception Cause: %s, %s\n", | |
93 | xtensa_exception_causes[i].msg, | |
94 | xtensa_exception_causes[i].description); | |
95 | } | |
96 | } | |
97 | dev_err(sdev->dev, "EXCCAUSE 0x%8.8x EXCVADDR 0x%8.8x PS 0x%8.8x SAR 0x%8.8x\n", | |
98 | xoops->exccause, xoops->excvaddr, xoops->ps, xoops->sar); | |
99 | dev_err(sdev->dev, "EPC1 0x%8.8x EPC2 0x%8.8x EPC3 0x%8.8x EPC4 0x%8.8x", | |
100 | xoops->epc1, xoops->epc2, xoops->epc3, xoops->epc4); | |
101 | dev_err(sdev->dev, "EPC5 0x%8.8x EPC6 0x%8.8x EPC7 0x%8.8x DEPC 0x%8.8x", | |
102 | xoops->epc5, xoops->epc6, xoops->epc7, xoops->depc); | |
103 | dev_err(sdev->dev, "EPS2 0x%8.8x EPS3 0x%8.8x EPS4 0x%8.8x EPS5 0x%8.8x", | |
104 | xoops->eps2, xoops->eps3, xoops->eps4, xoops->eps5); | |
105 | dev_err(sdev->dev, "EPS6 0x%8.8x EPS7 0x%8.8x INTENABL 0x%8.8x INTERRU 0x%8.8x", | |
106 | xoops->eps6, xoops->eps7, xoops->intenable, xoops->interrupt); | |
107 | } | |
108 | ||
109 | static void xtensa_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack, | |
110 | u32 stack_words) | |
111 | { | |
112 | struct sof_ipc_dsp_oops_xtensa *xoops = oops; | |
14104eb6 | 113 | u32 stack_ptr = xoops->plat_hdr.stackptr; |
e657c18a PLB |
114 | /* 4 * 8chars + 3 ws + 1 terminating NUL */ |
115 | unsigned char buf[4 * 8 + 3 + 1]; | |
116 | int i; | |
117 | ||
118 | dev_err(sdev->dev, "stack dump from 0x%8.8x\n", stack_ptr); | |
119 | ||
120 | /* | |
121 | * example output: | |
122 | * 0x0049fbb0: 8000f2d0 0049fc00 6f6c6c61 00632e63 | |
123 | */ | |
124 | for (i = 0; i < stack_words; i += 4) { | |
125 | hex_dump_to_buffer(stack + i * 4, 16, 16, 4, | |
126 | buf, sizeof(buf), false); | |
127 | dev_err(sdev->dev, "0x%08x: %s\n", stack_ptr + i, buf); | |
128 | } | |
129 | } | |
130 | ||
131 | const struct sof_arch_ops sof_xtensa_arch_ops = { | |
132 | .dsp_oops = xtensa_dsp_oops, | |
133 | .dsp_stack = xtensa_stack, | |
134 | }; | |
135 | EXPORT_SYMBOL(sof_xtensa_arch_ops); | |
136 | ||
137 | MODULE_DESCRIPTION("SOF Xtensa DSP support"); | |
138 | MODULE_LICENSE("Dual BSD/GPL"); |