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71f78e22 | 1 | /* |
ef280d39 | 2 | * tegra20_i2s.c - Tegra20 I2S driver |
71f78e22 SW |
3 | * |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
518de86b | 5 | * Copyright (C) 2010,2012 - NVIDIA, Inc. |
71f78e22 SW |
6 | * |
7 | * Based on code copyright/by: | |
8 | * | |
9 | * Copyright (c) 2009-2010, NVIDIA Corporation. | |
10 | * Scott Peterson <speterson@nvidia.com> | |
11 | * | |
12 | * Copyright (C) 2010 Google, Inc. | |
13 | * Iliyan Malchev <malchev@google.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * version 2 as published by the Free Software Foundation. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
27 | * 02110-1301 USA | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/clk.h> | |
71f78e22 | 32 | #include <linux/device.h> |
7613c508 SW |
33 | #include <linux/io.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/of.h> | |
71f78e22 | 36 | #include <linux/platform_device.h> |
82ef0ae4 | 37 | #include <linux/pm_runtime.h> |
c1607416 | 38 | #include <linux/regmap.h> |
71f78e22 | 39 | #include <linux/slab.h> |
71f78e22 SW |
40 | #include <sound/core.h> |
41 | #include <sound/pcm.h> | |
42 | #include <sound/pcm_params.h> | |
43 | #include <sound/soc.h> | |
44 | ||
ef280d39 | 45 | #include "tegra20_i2s.h" |
71f78e22 | 46 | |
896637ac | 47 | #define DRV_NAME "tegra20-i2s" |
71f78e22 | 48 | |
896637ac | 49 | static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val) |
71f78e22 | 50 | { |
c1607416 | 51 | regmap_write(i2s->regmap, reg, val); |
71f78e22 SW |
52 | } |
53 | ||
896637ac | 54 | static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg) |
71f78e22 | 55 | { |
c1607416 SW |
56 | u32 val; |
57 | regmap_read(i2s->regmap, reg, &val); | |
58 | return val; | |
71f78e22 SW |
59 | } |
60 | ||
82ef0ae4 SW |
61 | static int tegra20_i2s_runtime_suspend(struct device *dev) |
62 | { | |
63 | struct tegra20_i2s *i2s = dev_get_drvdata(dev); | |
64 | ||
65 | clk_disable(i2s->clk_i2s); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | static int tegra20_i2s_runtime_resume(struct device *dev) | |
71 | { | |
72 | struct tegra20_i2s *i2s = dev_get_drvdata(dev); | |
73 | int ret; | |
74 | ||
75 | ret = clk_enable(i2s->clk_i2s); | |
76 | if (ret) { | |
77 | dev_err(dev, "clk_enable failed: %d\n", ret); | |
78 | return ret; | |
79 | } | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
896637ac | 84 | static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai, |
71f78e22 SW |
85 | unsigned int fmt) |
86 | { | |
896637ac | 87 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
88 | |
89 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
90 | case SND_SOC_DAIFMT_NB_NF: | |
91 | break; | |
92 | default: | |
93 | return -EINVAL; | |
94 | } | |
95 | ||
896637ac | 96 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
97 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
98 | case SND_SOC_DAIFMT_CBS_CFS: | |
896637ac | 99 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE; |
71f78e22 SW |
100 | break; |
101 | case SND_SOC_DAIFMT_CBM_CFM: | |
102 | break; | |
103 | default: | |
104 | return -EINVAL; | |
105 | } | |
106 | ||
896637ac SW |
107 | i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | |
108 | TEGRA20_I2S_CTRL_LRCK_MASK); | |
71f78e22 SW |
109 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
110 | case SND_SOC_DAIFMT_DSP_A: | |
896637ac SW |
111 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
112 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
113 | break; |
114 | case SND_SOC_DAIFMT_DSP_B: | |
896637ac SW |
115 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP; |
116 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW; | |
71f78e22 SW |
117 | break; |
118 | case SND_SOC_DAIFMT_I2S: | |
896637ac SW |
119 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S; |
120 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
121 | break; |
122 | case SND_SOC_DAIFMT_RIGHT_J: | |
896637ac SW |
123 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM; |
124 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
125 | break; |
126 | case SND_SOC_DAIFMT_LEFT_J: | |
896637ac SW |
127 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM; |
128 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW; | |
71f78e22 SW |
129 | break; |
130 | default: | |
131 | return -EINVAL; | |
132 | } | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
896637ac SW |
137 | static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, |
138 | struct snd_pcm_hw_params *params, | |
139 | struct snd_soc_dai *dai) | |
71f78e22 | 140 | { |
7deb2b45 | 141 | struct device *dev = substream->pcm->card->dev; |
896637ac | 142 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
143 | u32 reg; |
144 | int ret, sample_size, srate, i2sclock, bitcnt; | |
145 | ||
896637ac | 146 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK; |
71f78e22 SW |
147 | switch (params_format(params)) { |
148 | case SNDRV_PCM_FORMAT_S16_LE: | |
896637ac | 149 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16; |
71f78e22 SW |
150 | sample_size = 16; |
151 | break; | |
152 | case SNDRV_PCM_FORMAT_S24_LE: | |
896637ac | 153 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24; |
71f78e22 SW |
154 | sample_size = 24; |
155 | break; | |
156 | case SNDRV_PCM_FORMAT_S32_LE: | |
896637ac | 157 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32; |
71f78e22 SW |
158 | sample_size = 32; |
159 | break; | |
160 | default: | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
164 | srate = params_rate(params); | |
165 | ||
166 | /* Final "* 2" required by Tegra hardware */ | |
167 | i2sclock = srate * params_channels(params) * sample_size * 2; | |
168 | ||
169 | ret = clk_set_rate(i2s->clk_i2s, i2sclock); | |
170 | if (ret) { | |
171 | dev_err(dev, "Can't set I2S clock rate: %d\n", ret); | |
172 | return ret; | |
173 | } | |
174 | ||
175 | bitcnt = (i2sclock / (2 * srate)) - 1; | |
896637ac | 176 | if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) |
71f78e22 | 177 | return -EINVAL; |
896637ac | 178 | reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; |
71f78e22 SW |
179 | |
180 | if (i2sclock % (2 * srate)) | |
896637ac | 181 | reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; |
71f78e22 | 182 | |
896637ac | 183 | tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg); |
71f78e22 | 184 | |
896637ac SW |
185 | tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR, |
186 | TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | | |
187 | TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); | |
71f78e22 SW |
188 | |
189 | return 0; | |
190 | } | |
191 | ||
896637ac | 192 | static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s) |
71f78e22 | 193 | { |
896637ac SW |
194 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
195 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
196 | } |
197 | ||
896637ac | 198 | static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s) |
71f78e22 | 199 | { |
896637ac SW |
200 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE; |
201 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
202 | } |
203 | ||
896637ac | 204 | static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s) |
71f78e22 | 205 | { |
896637ac SW |
206 | i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
207 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
208 | } |
209 | ||
896637ac | 210 | static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s) |
71f78e22 | 211 | { |
896637ac SW |
212 | i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE; |
213 | tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl); | |
71f78e22 SW |
214 | } |
215 | ||
896637ac SW |
216 | static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
217 | struct snd_soc_dai *dai) | |
71f78e22 | 218 | { |
896637ac | 219 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
220 | |
221 | switch (cmd) { | |
222 | case SNDRV_PCM_TRIGGER_START: | |
223 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
224 | case SNDRV_PCM_TRIGGER_RESUME: | |
71f78e22 | 225 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
896637ac | 226 | tegra20_i2s_start_playback(i2s); |
71f78e22 | 227 | else |
896637ac | 228 | tegra20_i2s_start_capture(i2s); |
71f78e22 SW |
229 | break; |
230 | case SNDRV_PCM_TRIGGER_STOP: | |
231 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
232 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
233 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
896637ac | 234 | tegra20_i2s_stop_playback(i2s); |
71f78e22 | 235 | else |
896637ac | 236 | tegra20_i2s_stop_capture(i2s); |
71f78e22 SW |
237 | break; |
238 | default: | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
896637ac | 245 | static int tegra20_i2s_probe(struct snd_soc_dai *dai) |
71f78e22 | 246 | { |
896637ac | 247 | struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); |
71f78e22 SW |
248 | |
249 | dai->capture_dma_data = &i2s->capture_dma_data; | |
250 | dai->playback_dma_data = &i2s->playback_dma_data; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
896637ac SW |
255 | static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = { |
256 | .set_fmt = tegra20_i2s_set_fmt, | |
257 | .hw_params = tegra20_i2s_hw_params, | |
258 | .trigger = tegra20_i2s_trigger, | |
71f78e22 SW |
259 | }; |
260 | ||
896637ac SW |
261 | static const struct snd_soc_dai_driver tegra20_i2s_dai_template = { |
262 | .probe = tegra20_i2s_probe, | |
d4a2eca7 | 263 | .playback = { |
9515c101 | 264 | .stream_name = "Playback", |
d4a2eca7 SW |
265 | .channels_min = 2, |
266 | .channels_max = 2, | |
267 | .rates = SNDRV_PCM_RATE_8000_96000, | |
268 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 269 | }, |
d4a2eca7 | 270 | .capture = { |
9515c101 | 271 | .stream_name = "Capture", |
d4a2eca7 SW |
272 | .channels_min = 2, |
273 | .channels_max = 2, | |
274 | .rates = SNDRV_PCM_RATE_8000_96000, | |
275 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
71f78e22 | 276 | }, |
896637ac | 277 | .ops = &tegra20_i2s_dai_ops, |
d4a2eca7 | 278 | .symmetric_rates = 1, |
71f78e22 SW |
279 | }; |
280 | ||
c1607416 SW |
281 | static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg) |
282 | { | |
283 | switch (reg) { | |
284 | case TEGRA20_I2S_CTRL: | |
285 | case TEGRA20_I2S_STATUS: | |
286 | case TEGRA20_I2S_TIMING: | |
287 | case TEGRA20_I2S_FIFO_SCR: | |
288 | case TEGRA20_I2S_PCM_CTRL: | |
289 | case TEGRA20_I2S_NW_CTRL: | |
290 | case TEGRA20_I2S_TDM_CTRL: | |
291 | case TEGRA20_I2S_TDM_TX_RX_CTRL: | |
292 | case TEGRA20_I2S_FIFO1: | |
293 | case TEGRA20_I2S_FIFO2: | |
294 | return true; | |
295 | default: | |
296 | return false; | |
297 | }; | |
298 | } | |
299 | ||
300 | static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg) | |
301 | { | |
302 | switch (reg) { | |
303 | case TEGRA20_I2S_STATUS: | |
304 | case TEGRA20_I2S_FIFO_SCR: | |
305 | case TEGRA20_I2S_FIFO1: | |
306 | case TEGRA20_I2S_FIFO2: | |
307 | return true; | |
308 | default: | |
309 | return false; | |
310 | }; | |
311 | } | |
312 | ||
313 | static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg) | |
314 | { | |
315 | switch (reg) { | |
316 | case TEGRA20_I2S_FIFO1: | |
317 | case TEGRA20_I2S_FIFO2: | |
318 | return true; | |
319 | default: | |
320 | return false; | |
321 | }; | |
322 | } | |
323 | ||
324 | static const struct regmap_config tegra20_i2s_regmap_config = { | |
325 | .reg_bits = 32, | |
326 | .reg_stride = 4, | |
327 | .val_bits = 32, | |
328 | .max_register = TEGRA20_I2S_FIFO2, | |
329 | .writeable_reg = tegra20_i2s_wr_rd_reg, | |
330 | .readable_reg = tegra20_i2s_wr_rd_reg, | |
331 | .volatile_reg = tegra20_i2s_volatile_reg, | |
332 | .precious_reg = tegra20_i2s_precious_reg, | |
333 | .cache_type = REGCACHE_RBTREE, | |
334 | }; | |
335 | ||
896637ac | 336 | static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev) |
71f78e22 | 337 | { |
896637ac | 338 | struct tegra20_i2s *i2s; |
71f78e22 | 339 | struct resource *mem, *memregion, *dmareq; |
bf55499e SW |
340 | u32 of_dma[2]; |
341 | u32 dma_ch; | |
c1607416 | 342 | void __iomem *regs; |
71f78e22 SW |
343 | int ret; |
344 | ||
896637ac | 345 | i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL); |
71f78e22 | 346 | if (!i2s) { |
896637ac | 347 | dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n"); |
71f78e22 | 348 | ret = -ENOMEM; |
bea0ed08 | 349 | goto err; |
71f78e22 SW |
350 | } |
351 | dev_set_drvdata(&pdev->dev, i2s); | |
352 | ||
896637ac | 353 | i2s->dai = tegra20_i2s_dai_template; |
d4a2eca7 SW |
354 | i2s->dai.name = dev_name(&pdev->dev); |
355 | ||
b5f9cfed | 356 | i2s->clk_i2s = clk_get(&pdev->dev, NULL); |
422650e6 | 357 | if (IS_ERR(i2s->clk_i2s)) { |
713dce4e | 358 | dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); |
71f78e22 | 359 | ret = PTR_ERR(i2s->clk_i2s); |
bea0ed08 | 360 | goto err; |
71f78e22 SW |
361 | } |
362 | ||
363 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
364 | if (!mem) { | |
365 | dev_err(&pdev->dev, "No memory resource\n"); | |
366 | ret = -ENODEV; | |
367 | goto err_clk_put; | |
368 | } | |
369 | ||
370 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
371 | if (!dmareq) { | |
bf55499e SW |
372 | if (of_property_read_u32_array(pdev->dev.of_node, |
373 | "nvidia,dma-request-selector", | |
374 | of_dma, 2) < 0) { | |
375 | dev_err(&pdev->dev, "No DMA resource\n"); | |
376 | ret = -ENODEV; | |
377 | goto err_clk_put; | |
378 | } | |
379 | dma_ch = of_dma[1]; | |
380 | } else { | |
381 | dma_ch = dmareq->start; | |
71f78e22 SW |
382 | } |
383 | ||
bea0ed08 SW |
384 | memregion = devm_request_mem_region(&pdev->dev, mem->start, |
385 | resource_size(mem), DRV_NAME); | |
71f78e22 SW |
386 | if (!memregion) { |
387 | dev_err(&pdev->dev, "Memory region already claimed\n"); | |
388 | ret = -EBUSY; | |
389 | goto err_clk_put; | |
390 | } | |
391 | ||
c1607416 SW |
392 | regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
393 | if (!regs) { | |
71f78e22 SW |
394 | dev_err(&pdev->dev, "ioremap failed\n"); |
395 | ret = -ENOMEM; | |
bea0ed08 | 396 | goto err_clk_put; |
71f78e22 SW |
397 | } |
398 | ||
c1607416 SW |
399 | i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
400 | &tegra20_i2s_regmap_config); | |
401 | if (IS_ERR(i2s->regmap)) { | |
402 | dev_err(&pdev->dev, "regmap init failed\n"); | |
403 | ret = PTR_ERR(i2s->regmap); | |
404 | goto err_clk_put; | |
405 | } | |
406 | ||
896637ac | 407 | i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; |
71f78e22 SW |
408 | i2s->capture_dma_data.wrap = 4; |
409 | i2s->capture_dma_data.width = 32; | |
bf55499e | 410 | i2s->capture_dma_data.req_sel = dma_ch; |
71f78e22 | 411 | |
896637ac | 412 | i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; |
71f78e22 SW |
413 | i2s->playback_dma_data.wrap = 4; |
414 | i2s->playback_dma_data.width = 32; | |
bf55499e | 415 | i2s->playback_dma_data.req_sel = dma_ch; |
71f78e22 | 416 | |
896637ac | 417 | i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED; |
71f78e22 | 418 | |
82ef0ae4 SW |
419 | pm_runtime_enable(&pdev->dev); |
420 | if (!pm_runtime_enabled(&pdev->dev)) { | |
421 | ret = tegra20_i2s_runtime_resume(&pdev->dev); | |
422 | if (ret) | |
423 | goto err_pm_disable; | |
424 | } | |
425 | ||
d4a2eca7 | 426 | ret = snd_soc_register_dai(&pdev->dev, &i2s->dai); |
71f78e22 SW |
427 | if (ret) { |
428 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
429 | ret = -ENOMEM; | |
82ef0ae4 | 430 | goto err_suspend; |
71f78e22 SW |
431 | } |
432 | ||
518de86b SW |
433 | ret = tegra_pcm_platform_register(&pdev->dev); |
434 | if (ret) { | |
435 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
436 | goto err_unregister_dai; | |
437 | } | |
438 | ||
71f78e22 SW |
439 | return 0; |
440 | ||
518de86b SW |
441 | err_unregister_dai: |
442 | snd_soc_unregister_dai(&pdev->dev); | |
82ef0ae4 SW |
443 | err_suspend: |
444 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
445 | tegra20_i2s_runtime_suspend(&pdev->dev); | |
446 | err_pm_disable: | |
447 | pm_runtime_disable(&pdev->dev); | |
71f78e22 SW |
448 | err_clk_put: |
449 | clk_put(i2s->clk_i2s); | |
bea0ed08 | 450 | err: |
71f78e22 SW |
451 | return ret; |
452 | } | |
453 | ||
896637ac | 454 | static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev) |
71f78e22 | 455 | { |
896637ac | 456 | struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev); |
71f78e22 | 457 | |
82ef0ae4 SW |
458 | pm_runtime_disable(&pdev->dev); |
459 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
460 | tegra20_i2s_runtime_suspend(&pdev->dev); | |
461 | ||
518de86b | 462 | tegra_pcm_platform_unregister(&pdev->dev); |
71f78e22 SW |
463 | snd_soc_unregister_dai(&pdev->dev); |
464 | ||
71f78e22 SW |
465 | clk_put(i2s->clk_i2s); |
466 | ||
71f78e22 SW |
467 | return 0; |
468 | } | |
469 | ||
896637ac | 470 | static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = { |
bf55499e SW |
471 | { .compatible = "nvidia,tegra20-i2s", }, |
472 | {}, | |
473 | }; | |
474 | ||
82ef0ae4 SW |
475 | static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst = { |
476 | SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend, | |
477 | tegra20_i2s_runtime_resume, NULL) | |
478 | }; | |
479 | ||
896637ac | 480 | static struct platform_driver tegra20_i2s_driver = { |
71f78e22 SW |
481 | .driver = { |
482 | .name = DRV_NAME, | |
483 | .owner = THIS_MODULE, | |
896637ac | 484 | .of_match_table = tegra20_i2s_of_match, |
82ef0ae4 | 485 | .pm = &tegra20_i2s_pm_ops, |
71f78e22 | 486 | }, |
896637ac SW |
487 | .probe = tegra20_i2s_platform_probe, |
488 | .remove = __devexit_p(tegra20_i2s_platform_remove), | |
71f78e22 | 489 | }; |
896637ac | 490 | module_platform_driver(tegra20_i2s_driver); |
71f78e22 SW |
491 | |
492 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
896637ac | 493 | MODULE_DESCRIPTION("Tegra20 I2S ASoC driver"); |
71f78e22 | 494 | MODULE_LICENSE("GPL"); |
8eb34207 | 495 | MODULE_ALIAS("platform:" DRV_NAME); |
896637ac | 496 | MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match); |