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Commit | Line | Data |
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774fec33 | 1 | /* |
ef280d39 | 2 | * tegra20_spdif.c - Tegra20 SPDIF driver |
774fec33 SW |
3 | * |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
518de86b | 5 | * Copyright (C) 2011-2012 - NVIDIA, Inc. |
774fec33 SW |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clk.h> | |
774fec33 | 24 | #include <linux/device.h> |
7613c508 SW |
25 | #include <linux/io.h> |
26 | #include <linux/module.h> | |
774fec33 | 27 | #include <linux/platform_device.h> |
82ef0ae4 | 28 | #include <linux/pm_runtime.h> |
5939ae74 | 29 | #include <linux/regmap.h> |
774fec33 | 30 | #include <linux/slab.h> |
774fec33 SW |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
3489d506 | 35 | #include <sound/dmaengine_pcm.h> |
774fec33 | 36 | |
ef280d39 | 37 | #include "tegra20_spdif.h" |
774fec33 | 38 | |
896637ac | 39 | #define DRV_NAME "tegra20-spdif" |
774fec33 | 40 | |
82ef0ae4 SW |
41 | static int tegra20_spdif_runtime_suspend(struct device *dev) |
42 | { | |
43 | struct tegra20_spdif *spdif = dev_get_drvdata(dev); | |
44 | ||
65d2bdd3 | 45 | clk_disable_unprepare(spdif->clk_spdif_out); |
82ef0ae4 SW |
46 | |
47 | return 0; | |
48 | } | |
49 | ||
50 | static int tegra20_spdif_runtime_resume(struct device *dev) | |
51 | { | |
52 | struct tegra20_spdif *spdif = dev_get_drvdata(dev); | |
53 | int ret; | |
54 | ||
65d2bdd3 | 55 | ret = clk_prepare_enable(spdif->clk_spdif_out); |
82ef0ae4 SW |
56 | if (ret) { |
57 | dev_err(dev, "clk_enable failed: %d\n", ret); | |
58 | return ret; | |
59 | } | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
896637ac | 64 | static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream, |
774fec33 SW |
65 | struct snd_pcm_hw_params *params, |
66 | struct snd_soc_dai *dai) | |
67 | { | |
c92a40e3 | 68 | struct device *dev = dai->dev; |
896637ac | 69 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); |
0f163546 | 70 | unsigned int mask, val; |
4b8713fd | 71 | int ret, spdifclock; |
774fec33 | 72 | |
0f163546 SW |
73 | mask = TEGRA20_SPDIF_CTRL_PACK | |
74 | TEGRA20_SPDIF_CTRL_BIT_MODE_MASK; | |
774fec33 SW |
75 | switch (params_format(params)) { |
76 | case SNDRV_PCM_FORMAT_S16_LE: | |
0f163546 SW |
77 | val = TEGRA20_SPDIF_CTRL_PACK | |
78 | TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT; | |
774fec33 SW |
79 | break; |
80 | default: | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
0f163546 SW |
84 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val); |
85 | ||
774fec33 SW |
86 | switch (params_rate(params)) { |
87 | case 32000: | |
88 | spdifclock = 4096000; | |
89 | break; | |
90 | case 44100: | |
91 | spdifclock = 5644800; | |
92 | break; | |
93 | case 48000: | |
94 | spdifclock = 6144000; | |
95 | break; | |
96 | case 88200: | |
97 | spdifclock = 11289600; | |
98 | break; | |
99 | case 96000: | |
100 | spdifclock = 12288000; | |
101 | break; | |
102 | case 176400: | |
103 | spdifclock = 22579200; | |
104 | break; | |
105 | case 192000: | |
106 | spdifclock = 24576000; | |
107 | break; | |
108 | default: | |
109 | return -EINVAL; | |
110 | } | |
111 | ||
112 | ret = clk_set_rate(spdif->clk_spdif_out, spdifclock); | |
113 | if (ret) { | |
114 | dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret); | |
115 | return ret; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
896637ac | 121 | static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif) |
774fec33 | 122 | { |
0f163546 SW |
123 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, |
124 | TEGRA20_SPDIF_CTRL_TX_EN, | |
125 | TEGRA20_SPDIF_CTRL_TX_EN); | |
774fec33 SW |
126 | } |
127 | ||
896637ac | 128 | static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif) |
774fec33 | 129 | { |
0f163546 SW |
130 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, |
131 | TEGRA20_SPDIF_CTRL_TX_EN, 0); | |
774fec33 SW |
132 | } |
133 | ||
896637ac | 134 | static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd, |
774fec33 SW |
135 | struct snd_soc_dai *dai) |
136 | { | |
896637ac | 137 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); |
774fec33 SW |
138 | |
139 | switch (cmd) { | |
140 | case SNDRV_PCM_TRIGGER_START: | |
141 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
142 | case SNDRV_PCM_TRIGGER_RESUME: | |
896637ac | 143 | tegra20_spdif_start_playback(spdif); |
774fec33 SW |
144 | break; |
145 | case SNDRV_PCM_TRIGGER_STOP: | |
146 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
147 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
896637ac | 148 | tegra20_spdif_stop_playback(spdif); |
774fec33 SW |
149 | break; |
150 | default: | |
151 | return -EINVAL; | |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
896637ac | 157 | static int tegra20_spdif_probe(struct snd_soc_dai *dai) |
774fec33 | 158 | { |
896637ac | 159 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); |
774fec33 SW |
160 | |
161 | dai->capture_dma_data = NULL; | |
162 | dai->playback_dma_data = &spdif->playback_dma_data; | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
896637ac SW |
167 | static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = { |
168 | .hw_params = tegra20_spdif_hw_params, | |
169 | .trigger = tegra20_spdif_trigger, | |
774fec33 SW |
170 | }; |
171 | ||
896637ac | 172 | static struct snd_soc_dai_driver tegra20_spdif_dai = { |
774fec33 | 173 | .name = DRV_NAME, |
896637ac | 174 | .probe = tegra20_spdif_probe, |
774fec33 | 175 | .playback = { |
9515c101 | 176 | .stream_name = "Playback", |
774fec33 SW |
177 | .channels_min = 2, |
178 | .channels_max = 2, | |
179 | .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | | |
180 | SNDRV_PCM_RATE_48000, | |
181 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
182 | }, | |
896637ac | 183 | .ops = &tegra20_spdif_dai_ops, |
774fec33 SW |
184 | }; |
185 | ||
094e1a3d KM |
186 | static const struct snd_soc_component_driver tegra20_spdif_component = { |
187 | .name = DRV_NAME, | |
188 | }; | |
189 | ||
5939ae74 SW |
190 | static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg) |
191 | { | |
192 | switch (reg) { | |
193 | case TEGRA20_SPDIF_CTRL: | |
194 | case TEGRA20_SPDIF_STATUS: | |
195 | case TEGRA20_SPDIF_STROBE_CTRL: | |
196 | case TEGRA20_SPDIF_DATA_FIFO_CSR: | |
197 | case TEGRA20_SPDIF_DATA_OUT: | |
198 | case TEGRA20_SPDIF_DATA_IN: | |
199 | case TEGRA20_SPDIF_CH_STA_RX_A: | |
200 | case TEGRA20_SPDIF_CH_STA_RX_B: | |
201 | case TEGRA20_SPDIF_CH_STA_RX_C: | |
202 | case TEGRA20_SPDIF_CH_STA_RX_D: | |
203 | case TEGRA20_SPDIF_CH_STA_RX_E: | |
204 | case TEGRA20_SPDIF_CH_STA_RX_F: | |
205 | case TEGRA20_SPDIF_CH_STA_TX_A: | |
206 | case TEGRA20_SPDIF_CH_STA_TX_B: | |
207 | case TEGRA20_SPDIF_CH_STA_TX_C: | |
208 | case TEGRA20_SPDIF_CH_STA_TX_D: | |
209 | case TEGRA20_SPDIF_CH_STA_TX_E: | |
210 | case TEGRA20_SPDIF_CH_STA_TX_F: | |
211 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
212 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
213 | return true; | |
214 | default: | |
215 | return false; | |
1d198f26 | 216 | } |
5939ae74 SW |
217 | } |
218 | ||
219 | static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg) | |
220 | { | |
221 | switch (reg) { | |
222 | case TEGRA20_SPDIF_STATUS: | |
223 | case TEGRA20_SPDIF_DATA_FIFO_CSR: | |
224 | case TEGRA20_SPDIF_DATA_OUT: | |
225 | case TEGRA20_SPDIF_DATA_IN: | |
226 | case TEGRA20_SPDIF_CH_STA_RX_A: | |
227 | case TEGRA20_SPDIF_CH_STA_RX_B: | |
228 | case TEGRA20_SPDIF_CH_STA_RX_C: | |
229 | case TEGRA20_SPDIF_CH_STA_RX_D: | |
230 | case TEGRA20_SPDIF_CH_STA_RX_E: | |
231 | case TEGRA20_SPDIF_CH_STA_RX_F: | |
232 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
233 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
234 | return true; | |
235 | default: | |
236 | return false; | |
1d198f26 | 237 | } |
5939ae74 SW |
238 | } |
239 | ||
240 | static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg) | |
241 | { | |
242 | switch (reg) { | |
243 | case TEGRA20_SPDIF_DATA_OUT: | |
244 | case TEGRA20_SPDIF_DATA_IN: | |
245 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
246 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
247 | return true; | |
248 | default: | |
249 | return false; | |
1d198f26 | 250 | } |
5939ae74 SW |
251 | } |
252 | ||
253 | static const struct regmap_config tegra20_spdif_regmap_config = { | |
254 | .reg_bits = 32, | |
255 | .reg_stride = 4, | |
256 | .val_bits = 32, | |
257 | .max_register = TEGRA20_SPDIF_USR_DAT_TX_A, | |
258 | .writeable_reg = tegra20_spdif_wr_rd_reg, | |
259 | .readable_reg = tegra20_spdif_wr_rd_reg, | |
260 | .volatile_reg = tegra20_spdif_volatile_reg, | |
261 | .precious_reg = tegra20_spdif_precious_reg, | |
262 | .cache_type = REGCACHE_RBTREE, | |
263 | }; | |
264 | ||
4652a0d0 | 265 | static int tegra20_spdif_platform_probe(struct platform_device *pdev) |
774fec33 | 266 | { |
896637ac | 267 | struct tegra20_spdif *spdif; |
774fec33 | 268 | struct resource *mem, *memregion, *dmareq; |
5939ae74 | 269 | void __iomem *regs; |
774fec33 SW |
270 | int ret; |
271 | ||
17933db2 SW |
272 | spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif), |
273 | GFP_KERNEL); | |
774fec33 | 274 | if (!spdif) { |
896637ac | 275 | dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n"); |
774fec33 | 276 | ret = -ENOMEM; |
17933db2 | 277 | goto err; |
774fec33 SW |
278 | } |
279 | dev_set_drvdata(&pdev->dev, spdif); | |
280 | ||
281 | spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out"); | |
282 | if (IS_ERR(spdif->clk_spdif_out)) { | |
283 | pr_err("Can't retrieve spdif clock\n"); | |
284 | ret = PTR_ERR(spdif->clk_spdif_out); | |
17933db2 | 285 | goto err; |
774fec33 SW |
286 | } |
287 | ||
288 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
289 | if (!mem) { | |
290 | dev_err(&pdev->dev, "No memory resource\n"); | |
291 | ret = -ENODEV; | |
292 | goto err_clk_put; | |
293 | } | |
294 | ||
295 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
296 | if (!dmareq) { | |
297 | dev_err(&pdev->dev, "No DMA resource\n"); | |
298 | ret = -ENODEV; | |
299 | goto err_clk_put; | |
300 | } | |
301 | ||
17933db2 SW |
302 | memregion = devm_request_mem_region(&pdev->dev, mem->start, |
303 | resource_size(mem), DRV_NAME); | |
774fec33 SW |
304 | if (!memregion) { |
305 | dev_err(&pdev->dev, "Memory region already claimed\n"); | |
306 | ret = -EBUSY; | |
307 | goto err_clk_put; | |
308 | } | |
309 | ||
5939ae74 SW |
310 | regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
311 | if (!regs) { | |
774fec33 SW |
312 | dev_err(&pdev->dev, "ioremap failed\n"); |
313 | ret = -ENOMEM; | |
17933db2 | 314 | goto err_clk_put; |
774fec33 SW |
315 | } |
316 | ||
5939ae74 SW |
317 | spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
318 | &tegra20_spdif_regmap_config); | |
319 | if (IS_ERR(spdif->regmap)) { | |
320 | dev_err(&pdev->dev, "regmap init failed\n"); | |
321 | ret = PTR_ERR(spdif->regmap); | |
322 | goto err_clk_put; | |
323 | } | |
324 | ||
896637ac | 325 | spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT; |
647ab784 RZ |
326 | spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
327 | spdif->playback_dma_data.maxburst = 4; | |
3489d506 | 328 | spdif->playback_dma_data.slave_id = dmareq->start; |
774fec33 | 329 | |
82ef0ae4 SW |
330 | pm_runtime_enable(&pdev->dev); |
331 | if (!pm_runtime_enabled(&pdev->dev)) { | |
332 | ret = tegra20_spdif_runtime_resume(&pdev->dev); | |
333 | if (ret) | |
334 | goto err_pm_disable; | |
335 | } | |
336 | ||
094e1a3d KM |
337 | ret = snd_soc_register_component(&pdev->dev, &tegra20_spdif_component, |
338 | &tegra20_spdif_dai, 1); | |
774fec33 SW |
339 | if (ret) { |
340 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
341 | ret = -ENOMEM; | |
82ef0ae4 | 342 | goto err_suspend; |
774fec33 SW |
343 | } |
344 | ||
518de86b SW |
345 | ret = tegra_pcm_platform_register(&pdev->dev); |
346 | if (ret) { | |
347 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
094e1a3d | 348 | goto err_unregister_component; |
518de86b SW |
349 | } |
350 | ||
774fec33 SW |
351 | return 0; |
352 | ||
094e1a3d KM |
353 | err_unregister_component: |
354 | snd_soc_unregister_component(&pdev->dev); | |
82ef0ae4 SW |
355 | err_suspend: |
356 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
357 | tegra20_spdif_runtime_suspend(&pdev->dev); | |
358 | err_pm_disable: | |
359 | pm_runtime_disable(&pdev->dev); | |
774fec33 SW |
360 | err_clk_put: |
361 | clk_put(spdif->clk_spdif_out); | |
17933db2 | 362 | err: |
774fec33 SW |
363 | return ret; |
364 | } | |
365 | ||
4652a0d0 | 366 | static int tegra20_spdif_platform_remove(struct platform_device *pdev) |
774fec33 | 367 | { |
896637ac | 368 | struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev); |
774fec33 | 369 | |
82ef0ae4 SW |
370 | pm_runtime_disable(&pdev->dev); |
371 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
372 | tegra20_spdif_runtime_suspend(&pdev->dev); | |
373 | ||
518de86b | 374 | tegra_pcm_platform_unregister(&pdev->dev); |
094e1a3d | 375 | snd_soc_unregister_component(&pdev->dev); |
774fec33 | 376 | |
774fec33 SW |
377 | clk_put(spdif->clk_spdif_out); |
378 | ||
774fec33 SW |
379 | return 0; |
380 | } | |
381 | ||
f6e65744 | 382 | static const struct dev_pm_ops tegra20_spdif_pm_ops = { |
82ef0ae4 SW |
383 | SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend, |
384 | tegra20_spdif_runtime_resume, NULL) | |
385 | }; | |
386 | ||
896637ac | 387 | static struct platform_driver tegra20_spdif_driver = { |
774fec33 SW |
388 | .driver = { |
389 | .name = DRV_NAME, | |
390 | .owner = THIS_MODULE, | |
82ef0ae4 | 391 | .pm = &tegra20_spdif_pm_ops, |
774fec33 | 392 | }, |
896637ac | 393 | .probe = tegra20_spdif_platform_probe, |
4652a0d0 | 394 | .remove = tegra20_spdif_platform_remove, |
774fec33 SW |
395 | }; |
396 | ||
896637ac | 397 | module_platform_driver(tegra20_spdif_driver); |
774fec33 SW |
398 | |
399 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
896637ac | 400 | MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver"); |
774fec33 SW |
401 | MODULE_LICENSE("GPL"); |
402 | MODULE_ALIAS("platform:" DRV_NAME); |