[mirror_ubuntu-bionic-kernel.git] / sound / soc / tegra / tegra30_i2s.c

/*
 * tegra30_i2s.c - Tegra30 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "tegra30_ahub.h"
#include "tegra30_i2s.h"

#define DRV_NAME "tegra30-i2s"

static int tegra30_i2s_runtime_suspend(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);

	regcache_cache_only(i2s->regmap, true);

	clk_disable_unprepare(i2s->clk_i2s);

	return 0;
}

static int tegra30_i2s_runtime_resume(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->clk_i2s);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	regcache_cache_only(i2s->regmap, false);

	return 0;
}

static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
				unsigned int fmt)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int mask = 0, val = 0;

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
		TEGRA30_I2S_CTRL_LRCK_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_A:
		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
		val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
		break;
	case SND_SOC_DAIFMT_I2S:
		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
		break;
	default:
		return -EINVAL;
	}

	pm_runtime_get_sync(dai->dev);
	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
	pm_runtime_put(dai->dev);

	return 0;
}

static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct device *dev = dai->dev;
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int mask, val, reg;
	int ret, sample_size, srate, i2sclock, bitcnt;
	struct tegra30_ahub_cif_conf cif_conf;

	if (params_channels(params) != 2)
		return -EINVAL;

	mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
		sample_size = 16;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);

	srate = params_rate(params);

	/* Final "* 2" required by Tegra hardware */
	i2sclock = srate * params_channels(params) * sample_size * 2;

	bitcnt = (i2sclock / (2 * srate)) - 1;
	if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
		return -EINVAL;

	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	if (ret) {
		dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
		return ret;
	}

	val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;

	if (i2sclock % (2 * srate))
		val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;

	regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);

	cif_conf.threshold = 0;
	cif_conf.audio_channels = 2;
	cif_conf.client_channels = 2;
	cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
	cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
	cif_conf.expand = 0;
	cif_conf.stereo_conv = 0;
	cif_conf.replicate = 0;
	cif_conf.truncate = 0;
	cif_conf.mono_conv = 0;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
		reg = TEGRA30_I2S_CIF_RX_CTRL;
	} else {
		cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
		reg = TEGRA30_I2S_CIF_TX_CTRL;
	}

	i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);

	val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
	      (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
	regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);

	return 0;
}

static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
{
	tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
			   TEGRA30_I2S_CTRL_XFER_EN_TX,
			   TEGRA30_I2S_CTRL_XFER_EN_TX);
}

static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
{
	tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
			   TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
}

static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
{
	tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
			   TEGRA30_I2S_CTRL_XFER_EN_RX,
			   TEGRA30_I2S_CTRL_XFER_EN_RX);
}

static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
{
	tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
			   TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
}

static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra30_i2s_start_playback(i2s);
		else
			tegra30_i2s_start_capture(i2s);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			tegra30_i2s_stop_playback(i2s);
		else
			tegra30_i2s_stop_capture(i2s);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra30_i2s_probe(struct snd_soc_dai *dai)
{
	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
	.set_fmt	= tegra30_i2s_set_fmt,
	.hw_params	= tegra30_i2s_hw_params,
	.trigger	= tegra30_i2s_trigger,
};

static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
	.probe = tegra30_i2s_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra30_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver tegra30_i2s_component = {
	.name		= DRV_NAME,
};

static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA30_I2S_CTRL:
	case TEGRA30_I2S_TIMING:
	case TEGRA30_I2S_OFFSET:
	case TEGRA30_I2S_CH_CTRL:
	case TEGRA30_I2S_SLOT_CTRL:
	case TEGRA30_I2S_CIF_RX_CTRL:
	case TEGRA30_I2S_CIF_TX_CTRL:
	case TEGRA30_I2S_FLOWCTL:
	case TEGRA30_I2S_TX_STEP:
	case TEGRA30_I2S_FLOW_STATUS:
	case TEGRA30_I2S_FLOW_TOTAL:
	case TEGRA30_I2S_FLOW_OVER:
	case TEGRA30_I2S_FLOW_UNDER:
	case TEGRA30_I2S_LCOEF_1_4_0:
	case TEGRA30_I2S_LCOEF_1_4_1:
	case TEGRA30_I2S_LCOEF_1_4_2:
	case TEGRA30_I2S_LCOEF_1_4_3:
	case TEGRA30_I2S_LCOEF_1_4_4:
	case TEGRA30_I2S_LCOEF_1_4_5:
	case TEGRA30_I2S_LCOEF_2_4_0:
	case TEGRA30_I2S_LCOEF_2_4_1:
	case TEGRA30_I2S_LCOEF_2_4_2:
		return true;
	default:
		return false;
	}
}

static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA30_I2S_FLOW_STATUS:
	case TEGRA30_I2S_FLOW_TOTAL:
	case TEGRA30_I2S_FLOW_OVER:
	case TEGRA30_I2S_FLOW_UNDER:
		return true;
	default:
		return false;
	}
}

static const struct regmap_config tegra30_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA30_I2S_LCOEF_2_4_2,
	.writeable_reg = tegra30_i2s_wr_rd_reg,
	.readable_reg = tegra30_i2s_wr_rd_reg,
	.volatile_reg = tegra30_i2s_volatile_reg,
	.cache_type = REGCACHE_FLAT,
};

static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
	.set_audio_cif = tegra30_ahub_set_cif,
};

static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
	.set_audio_cif = tegra124_ahub_set_cif,
};

static const struct of_device_id tegra30_i2s_of_match[] = {
	{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
	{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
	{},
};

static int tegra30_i2s_platform_probe(struct platform_device *pdev)
{
	struct tegra30_i2s *i2s;
	const struct of_device_id *match;
	u32 cif_ids[2];
	struct resource *mem;
	void __iomem *regs;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, i2s);

	match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
	if (!match) {
		dev_err(&pdev->dev, "Error: No device match found\n");
		ret = -ENODEV;
		goto err;
	}
	i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;

	i2s->dai = tegra30_i2s_dai_template;
	i2s->dai.name = dev_name(&pdev->dev);

	ret = of_property_read_u32_array(pdev->dev.of_node,
					 "nvidia,ahub-cif-ids", cif_ids,
					 ARRAY_SIZE(cif_ids));
	if (ret < 0)
		goto err;

	i2s->playback_i2s_cif = cif_ids[0];
	i2s->capture_i2s_cif = cif_ids[1];

	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2s->clk_i2s)) {
		dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
		ret = PTR_ERR(i2s->clk_i2s);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(regs)) {
		ret = PTR_ERR(regs);
		goto err_clk_put;
	}

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra30_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(i2s->regmap);
		goto err_clk_put;
	}
	regcache_cache_only(i2s->regmap, true);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra30_i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;
	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
					    i2s->playback_dma_chan,
					    sizeof(i2s->playback_dma_chan),
					    &i2s->playback_dma_data.addr);
	if (ret) {
		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
		goto err_suspend;
	}
	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
					     i2s->playback_fifo_cif);
	if (ret) {
		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
		goto err_free_tx_fifo;
	}

	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;
	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
					    i2s->capture_dma_chan,
					    sizeof(i2s->capture_dma_chan),
					    &i2s->capture_dma_data.addr);
	if (ret) {
		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
		goto err_unroute_tx_fifo;
	}
	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
					     i2s->capture_i2s_cif);
	if (ret) {
		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
		goto err_free_rx_fifo;
	}

	ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
				   &i2s->dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_unroute_rx_fifo;
	}

	ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
				&i2s->dma_config, i2s->playback_dma_chan,
				i2s->capture_dma_chan);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_component;
	}

	return 0;

err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
err_unroute_rx_fifo:
	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
err_free_rx_fifo:
	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
err_unroute_tx_fifo:
	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
err_free_tx_fifo:
	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra30_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(i2s->clk_i2s);
err:
	return ret;
}

static int tegra30_i2s_platform_remove(struct platform_device *pdev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra30_i2s_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_component(&pdev->dev);

	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);

	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);

	clk_put(i2s->clk_i2s);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra30_i2s_suspend(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);

	regcache_mark_dirty(i2s->regmap);

	return 0;
}

static int tegra30_i2s_resume(struct device *dev)
{
	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	int ret;

	ret = pm_runtime_get_sync(dev);
	if (ret < 0)
		return ret;
	ret = regcache_sync(i2s->regmap);
	pm_runtime_put(dev);

	return ret;
}
#endif

static const struct dev_pm_ops tegra30_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
			   tegra30_i2s_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
};

static struct platform_driver tegra30_i2s_driver = {
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra30_i2s_of_match,
		.pm = &tegra30_i2s_pm_ops,
	},
	.probe = tegra30_i2s_platform_probe,
	.remove = tegra30_i2s_platform_remove,
};
module_platform_driver(tegra30_i2s_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
Commit	Line	Data
4fb0384f SW	1	/*
	2	* tegra30_i2s.c - Tegra30 I2S driver
	3	*
	4	* Author: Stephen Warren <swarren@nvidia.com>
	5	* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms and conditions of the GNU General Public License,
	17	* version 2, as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	26	*/
	27
	28	#include <linux/clk.h>
	29	#include <linux/device.h>
	30	#include <linux/io.h>
	31	#include <linux/module.h>
	32	#include <linux/of.h>
5e049fce	33	#include <linux/of_device.h>
4fb0384f SW	34	#include <linux/platform_device.h>
	35	#include <linux/pm_runtime.h>
	36	#include <linux/regmap.h>
	37	#include <linux/slab.h>
	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
	41	#include <sound/soc.h>
3489d506	42	#include <sound/dmaengine_pcm.h>
4fb0384f SW	43
	44	#include "tegra30_ahub.h"
	45	#include "tegra30_i2s.h"
	46
	47	#define DRV_NAME "tegra30-i2s"
	48
4fb0384f SW	49	static int tegra30_i2s_runtime_suspend(struct device *dev)
	50	{
	51	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	52
	53	regcache_cache_only(i2s->regmap, true);
	54
65d2bdd3	55	clk_disable_unprepare(i2s->clk_i2s);
4fb0384f SW	56
	57	return 0;
	58	}
	59
	60	static int tegra30_i2s_runtime_resume(struct device *dev)
	61	{
	62	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	63	int ret;
	64
65d2bdd3	65	ret = clk_prepare_enable(i2s->clk_i2s);
4fb0384f SW	66	if (ret) {
	67	dev_err(dev, "clk_enable failed: %d\n", ret);
	68	return ret;
	69	}
	70
	71	regcache_cache_only(i2s->regmap, false);
	72
	73	return 0;
	74	}
	75
4fb0384f SW	76	static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
	77	unsigned int fmt)
	78	{
	79	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
241bf433	80	unsigned int mask = 0, val = 0;
4fb0384f SW	81
	82	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	83	case SND_SOC_DAIFMT_NB_NF:
	84	break;
	85	default:
	86	return -EINVAL;
	87	}
	88
241bf433	89	mask \|= TEGRA30_I2S_CTRL_MASTER_ENABLE;
4fb0384f SW	90	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4fb0384f SW	91	case SND_SOC_DAIFMT_CBS_CFS:
241bf433	92	val \|= TEGRA30_I2S_CTRL_MASTER_ENABLE;
4fb0384f SW	93	break;
	94	case SND_SOC_DAIFMT_CBM_CFM:
	95	break;
	96	default:
	97	return -EINVAL;
	98	}
	99
0f163546 SW	100	mask \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK \|
0f163546 SW	101	TEGRA30_I2S_CTRL_LRCK_MASK;
4fb0384f SW	102	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4fb0384f SW	103	case SND_SOC_DAIFMT_DSP_A:
0f163546 SW	104	val \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
0f163546 SW	105	val \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
4fb0384f SW	106	break;
4fb0384f SW	107	case SND_SOC_DAIFMT_DSP_B:
0f163546 SW	108	val \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
0f163546 SW	109	val \|= TEGRA30_I2S_CTRL_LRCK_R_LOW;
4fb0384f SW	110	break;
4fb0384f SW	111	case SND_SOC_DAIFMT_I2S:
0f163546 SW	112	val \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
0f163546 SW	113	val \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
4fb0384f SW	114	break;
4fb0384f SW	115	case SND_SOC_DAIFMT_RIGHT_J:
0f163546 SW	116	val \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
0f163546 SW	117	val \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
4fb0384f SW	118	break;
4fb0384f SW	119	case SND_SOC_DAIFMT_LEFT_J:
0f163546 SW	120	val \|= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
0f163546 SW	121	val \|= TEGRA30_I2S_CTRL_LRCK_L_LOW;
4fb0384f SW	122	break;
	123	default:
	124	return -EINVAL;
	125	}
	126
0f163546 SW	127	pm_runtime_get_sync(dai->dev);
	128	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
	129	pm_runtime_put(dai->dev);
	130
4fb0384f SW	131	return 0;
	132	}
	133
	134	static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
	135	struct snd_pcm_hw_params *params,
	136	struct snd_soc_dai *dai)
	137	{
c92a40e3	138	struct device *dev = dai->dev;
4fb0384f	139	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0f163546	140	unsigned int mask, val, reg;
4fb0384f	141	int ret, sample_size, srate, i2sclock, bitcnt;
5e049fce	142	struct tegra30_ahub_cif_conf cif_conf;
4fb0384f SW	143
	144	if (params_channels(params) != 2)
	145	return -EINVAL;
	146
0f163546	147	mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
4fb0384f SW	148	switch (params_format(params)) {
4fb0384f SW	149	case SNDRV_PCM_FORMAT_S16_LE:
0f163546	150	val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
4fb0384f SW	151	sample_size = 16;
	152	break;
	153	default:
	154	return -EINVAL;
	155	}
	156
0f163546 SW	157	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
0f163546 SW	158
4fb0384f SW	159	srate = params_rate(params);
	160
	161	/* Final "* 2" required by Tegra hardware */
	162	i2sclock = srate * params_channels(params) * sample_size * 2;
	163
	164	bitcnt = (i2sclock / (2 * srate)) - 1;
	165	if (bitcnt < 0 \|\| bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
	166	return -EINVAL;
	167
	168	ret = clk_set_rate(i2s->clk_i2s, i2sclock);
	169	if (ret) {
	170	dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
	171	return ret;
	172	}
	173
	174	val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
	175
	176	if (i2sclock % (2 * srate))
	177	val \|= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
	178
0f163546	179	regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
4fb0384f	180
5e049fce SW	181	cif_conf.threshold = 0;
	182	cif_conf.audio_channels = 2;
	183	cif_conf.client_channels = 2;
	184	cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
	185	cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
	186	cif_conf.expand = 0;
	187	cif_conf.stereo_conv = 0;
	188	cif_conf.replicate = 0;
	189	cif_conf.truncate = 0;
	190	cif_conf.mono_conv = 0;
4fb0384f SW	191
4fb0384f SW	192	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5e049fce	193	cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
0f163546	194	reg = TEGRA30_I2S_CIF_RX_CTRL;
4fb0384f	195	} else {
5e049fce	196	cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
c90c0d7a	197	reg = TEGRA30_I2S_CIF_TX_CTRL;
4fb0384f SW	198	}
4fb0384f SW	199
5e049fce	200	i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
0f163546	201
4fb0384f SW	202	val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) \|
4fb0384f SW	203	(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
0f163546	204	regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
4fb0384f SW	205
	206	return 0;
	207	}
	208
	209	static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
	210	{
	211	tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
0f163546 SW	212	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
	213	TEGRA30_I2S_CTRL_XFER_EN_TX,
	214	TEGRA30_I2S_CTRL_XFER_EN_TX);
4fb0384f SW	215	}
	216
	217	static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
	218	{
	219	tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
0f163546 SW	220	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
0f163546 SW	221	TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
4fb0384f SW	222	}
	223
	224	static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
	225	{
	226	tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
0f163546 SW	227	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
	228	TEGRA30_I2S_CTRL_XFER_EN_RX,
	229	TEGRA30_I2S_CTRL_XFER_EN_RX);
4fb0384f SW	230	}
	231
	232	static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
	233	{
	234	tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
0f163546 SW	235	regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
0f163546 SW	236	TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
4fb0384f SW	237	}
	238
	239	static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	240	struct snd_soc_dai *dai)
	241	{
	242	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	243
	244	switch (cmd) {
	245	case SNDRV_PCM_TRIGGER_START:
	246	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	247	case SNDRV_PCM_TRIGGER_RESUME:
	248	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	249	tegra30_i2s_start_playback(i2s);
	250	else
	251	tegra30_i2s_start_capture(i2s);
	252	break;
	253	case SNDRV_PCM_TRIGGER_STOP:
	254	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	255	case SNDRV_PCM_TRIGGER_SUSPEND:
	256	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	257	tegra30_i2s_stop_playback(i2s);
	258	else
	259	tegra30_i2s_stop_capture(i2s);
	260	break;
	261	default:
	262	return -EINVAL;
	263	}
	264
	265	return 0;
	266	}
	267
	268	static int tegra30_i2s_probe(struct snd_soc_dai *dai)
	269	{
	270	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	271
	272	dai->capture_dma_data = &i2s->capture_dma_data;
	273	dai->playback_dma_data = &i2s->playback_dma_data;
	274
	275	return 0;
	276	}
	277
	278	static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
4fb0384f SW	279	.set_fmt = tegra30_i2s_set_fmt,
	280	.hw_params = tegra30_i2s_hw_params,
	281	.trigger = tegra30_i2s_trigger,
	282	};
	283
	284	static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
	285	.probe = tegra30_i2s_probe,
	286	.playback = {
9515c101	287	.stream_name = "Playback",
4fb0384f SW	288	.channels_min = 2,
	289	.channels_max = 2,
	290	.rates = SNDRV_PCM_RATE_8000_96000,
	291	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	292	},
	293	.capture = {
9515c101	294	.stream_name = "Capture",
4fb0384f SW	295	.channels_min = 2,
	296	.channels_max = 2,
	297	.rates = SNDRV_PCM_RATE_8000_96000,
	298	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	299	},
	300	.ops = &tegra30_i2s_dai_ops,
	301	.symmetric_rates = 1,
	302	};
	303
65328454 KM	304	static const struct snd_soc_component_driver tegra30_i2s_component = {
	305	.name = DRV_NAME,
	306	};
	307
4fb0384f SW	308	static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
	309	{
	310	switch (reg) {
	311	case TEGRA30_I2S_CTRL:
	312	case TEGRA30_I2S_TIMING:
	313	case TEGRA30_I2S_OFFSET:
	314	case TEGRA30_I2S_CH_CTRL:
	315	case TEGRA30_I2S_SLOT_CTRL:
	316	case TEGRA30_I2S_CIF_RX_CTRL:
	317	case TEGRA30_I2S_CIF_TX_CTRL:
	318	case TEGRA30_I2S_FLOWCTL:
	319	case TEGRA30_I2S_TX_STEP:
	320	case TEGRA30_I2S_FLOW_STATUS:
	321	case TEGRA30_I2S_FLOW_TOTAL:
	322	case TEGRA30_I2S_FLOW_OVER:
	323	case TEGRA30_I2S_FLOW_UNDER:
	324	case TEGRA30_I2S_LCOEF_1_4_0:
	325	case TEGRA30_I2S_LCOEF_1_4_1:
	326	case TEGRA30_I2S_LCOEF_1_4_2:
	327	case TEGRA30_I2S_LCOEF_1_4_3:
	328	case TEGRA30_I2S_LCOEF_1_4_4:
	329	case TEGRA30_I2S_LCOEF_1_4_5:
	330	case TEGRA30_I2S_LCOEF_2_4_0:
	331	case TEGRA30_I2S_LCOEF_2_4_1:
	332	case TEGRA30_I2S_LCOEF_2_4_2:
	333	return true;
	334	default:
	335	return false;
1d198f26	336	}
4fb0384f SW	337	}
	338
	339	static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
	340	{
	341	switch (reg) {
	342	case TEGRA30_I2S_FLOW_STATUS:
	343	case TEGRA30_I2S_FLOW_TOTAL:
	344	case TEGRA30_I2S_FLOW_OVER:
	345	case TEGRA30_I2S_FLOW_UNDER:
	346	return true;
	347	default:
	348	return false;
1d198f26	349	}
4fb0384f SW	350	}
	351
	352	static const struct regmap_config tegra30_i2s_regmap_config = {
	353	.reg_bits = 32,
	354	.reg_stride = 4,
	355	.val_bits = 32,
	356	.max_register = TEGRA30_I2S_LCOEF_2_4_2,
	357	.writeable_reg = tegra30_i2s_wr_rd_reg,
	358	.readable_reg = tegra30_i2s_wr_rd_reg,
	359	.volatile_reg = tegra30_i2s_volatile_reg,
591d14f0	360	.cache_type = REGCACHE_FLAT,
4fb0384f SW	361	};
4fb0384f SW	362
5e049fce SW	363	static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
	364	.set_audio_cif = tegra30_ahub_set_cif,
	365	};
	366
	367	static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
	368	.set_audio_cif = tegra124_ahub_set_cif,
	369	};
	370
	371	static const struct of_device_id tegra30_i2s_of_match[] = {
	372	{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
	373	{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
	374	{},
	375	};
	376
4652a0d0	377	static int tegra30_i2s_platform_probe(struct platform_device *pdev)
4fb0384f SW	378	{
4fb0384f SW	379	struct tegra30_i2s *i2s;
5e049fce	380	const struct of_device_id *match;
4fb0384f	381	u32 cif_ids[2];
f57ddcdf	382	struct resource *mem;
4fb0384f SW	383	void __iomem *regs;
	384	int ret;
	385
	386	i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
	387	if (!i2s) {
	388	dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
	389	ret = -ENOMEM;
	390	goto err;
	391	}
	392	dev_set_drvdata(&pdev->dev, i2s);
	393
5e049fce SW	394	match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
	395	if (!match) {
	396	dev_err(&pdev->dev, "Error: No device match found\n");
	397	ret = -ENODEV;
	398	goto err;
	399	}
	400	i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
	401
4fb0384f SW	402	i2s->dai = tegra30_i2s_dai_template;
	403	i2s->dai.name = dev_name(&pdev->dev);
	404
	405	ret = of_property_read_u32_array(pdev->dev.of_node,
	406	"nvidia,ahub-cif-ids", cif_ids,
	407	ARRAY_SIZE(cif_ids));
	408	if (ret < 0)
	409	goto err;
	410
	411	i2s->playback_i2s_cif = cif_ids[0];
	412	i2s->capture_i2s_cif = cif_ids[1];
	413
	414	i2s->clk_i2s = clk_get(&pdev->dev, NULL);
	415	if (IS_ERR(i2s->clk_i2s)) {
	416	dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
	417	ret = PTR_ERR(i2s->clk_i2s);
	418	goto err;
	419	}
	420
	421	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f57ddcdf AL	422	regs = devm_ioremap_resource(&pdev->dev, mem);
	423	if (IS_ERR(regs)) {
	424	ret = PTR_ERR(regs);
4fb0384f SW	425	goto err_clk_put;
	426	}
	427
	428	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	429	&tegra30_i2s_regmap_config);
	430	if (IS_ERR(i2s->regmap)) {
	431	dev_err(&pdev->dev, "regmap init failed\n");
	432	ret = PTR_ERR(i2s->regmap);
	433	goto err_clk_put;
	434	}
	435	regcache_cache_only(i2s->regmap, true);
	436
	437	pm_runtime_enable(&pdev->dev);
	438	if (!pm_runtime_enabled(&pdev->dev)) {
	439	ret = tegra30_i2s_runtime_resume(&pdev->dev);
	440	if (ret)
	441	goto err_pm_disable;
	442	}
	443
d59afb6a SW	444	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	445	i2s->playback_dma_data.maxburst = 4;
	446	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
5608bd3e SW	447	i2s->playback_dma_chan,
	448	sizeof(i2s->playback_dma_chan),
	449	&i2s->playback_dma_data.addr);
d59afb6a SW	450	if (ret) {
	451	dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
	452	goto err_suspend;
	453	}
	454	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
	455	i2s->playback_fifo_cif);
	456	if (ret) {
	457	dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
	458	goto err_free_tx_fifo;
	459	}
	460
	461	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	462	i2s->capture_dma_data.maxburst = 4;
	463	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
5608bd3e SW	464	i2s->capture_dma_chan,
	465	sizeof(i2s->capture_dma_chan),
	466	&i2s->capture_dma_data.addr);
d59afb6a SW	467	if (ret) {
	468	dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
	469	goto err_unroute_tx_fifo;
	470	}
	471	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
	472	i2s->capture_i2s_cif);
	473	if (ret) {
	474	dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
	475	goto err_free_rx_fifo;
	476	}
	477
65328454 KM	478	ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
65328454 KM	479	&i2s->dai, 1);
4fb0384f SW	480	if (ret) {
	481	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	482	ret = -ENOMEM;
d59afb6a	483	goto err_unroute_rx_fifo;
4fb0384f SW	484	}
4fb0384f SW	485
5608bd3e SW	486	ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
	487	&i2s->dma_config, i2s->playback_dma_chan,
	488	i2s->capture_dma_chan);
4fb0384f SW	489	if (ret) {
4fb0384f SW	490	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
65328454	491	goto err_unregister_component;
4fb0384f SW	492	}
	493
	494	return 0;
	495
65328454 KM	496	err_unregister_component:
65328454 KM	497	snd_soc_unregister_component(&pdev->dev);
d59afb6a SW	498	err_unroute_rx_fifo:
	499	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
	500	err_free_rx_fifo:
	501	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
	502	err_unroute_tx_fifo:
	503	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
	504	err_free_tx_fifo:
	505	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
4fb0384f SW	506	err_suspend:
	507	if (!pm_runtime_status_suspended(&pdev->dev))
	508	tegra30_i2s_runtime_suspend(&pdev->dev);
	509	err_pm_disable:
	510	pm_runtime_disable(&pdev->dev);
	511	err_clk_put:
	512	clk_put(i2s->clk_i2s);
	513	err:
	514	return ret;
	515	}
	516
4652a0d0	517	static int tegra30_i2s_platform_remove(struct platform_device *pdev)
4fb0384f SW	518	{
	519	struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
	520
	521	pm_runtime_disable(&pdev->dev);
	522	if (!pm_runtime_status_suspended(&pdev->dev))
	523	tegra30_i2s_runtime_suspend(&pdev->dev);
	524
	525	tegra_pcm_platform_unregister(&pdev->dev);
65328454	526	snd_soc_unregister_component(&pdev->dev);
4fb0384f	527
d59afb6a SW	528	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
	529	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
	530
	531	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
	532	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
	533
4fb0384f SW	534	clk_put(i2s->clk_i2s);
	535
	536	return 0;
	537	}
	538
5c5b0828 SW	539	#ifdef CONFIG_PM_SLEEP
	540	static int tegra30_i2s_suspend(struct device *dev)
	541	{
	542	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
	543
	544	regcache_mark_dirty(i2s->regmap);
	545
	546	return 0;
	547	}
	548
	549	static int tegra30_i2s_resume(struct device *dev)
	550	{
	551	struct tegra30_i2s *i2s = dev_get_drvdata(dev);
249e66c3	552	int ret;
5c5b0828	553
249e66c3 SW	554	ret = pm_runtime_get_sync(dev);
	555	if (ret < 0)
	556	return ret;
	557	ret = regcache_sync(i2s->regmap);
	558	pm_runtime_put(dev);
	559
	560	return ret;
5c5b0828 SW	561	}
	562	#endif
	563
f6e65744	564	static const struct dev_pm_ops tegra30_i2s_pm_ops = {
4fb0384f SW	565	SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
4fb0384f SW	566	tegra30_i2s_runtime_resume, NULL)
5c5b0828	567	SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
4fb0384f SW	568	};
	569
	570	static struct platform_driver tegra30_i2s_driver = {
	571	.driver = {
	572	.name = DRV_NAME,
4fb0384f SW	573	.of_match_table = tegra30_i2s_of_match,
	574	.pm = &tegra30_i2s_pm_ops,
	575	},
	576	.probe = tegra30_i2s_platform_probe,
4652a0d0	577	.remove = tegra30_i2s_platform_remove,
4fb0384f SW	578	};
	579	module_platform_driver(tegra30_i2s_driver);
	580
	581	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
	582	MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
	583	MODULE_LICENSE("GPL");
	584	MODULE_ALIAS("platform:" DRV_NAME);
	585	MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);