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Merge tag 'asoc-v5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / ti / davinci-mcasp.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
b67f4487
C		 2/*
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 *
5 * Multi-channel Audio Serial Port Driver
6 *
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
10 *
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
b67f4487
C		 13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/device.h>
5a0e3ad6 18#include <linux/slab.h>
b67f4487
C		 19#include <linux/delay.h>
20#include <linux/io.h>
ae726e93 21#include <linux/clk.h>
10884347 22#include <linux/pm_runtime.h>
3e3b8c34
HG		 23#include <linux/of.h>
24#include <linux/of_platform.h>
25#include <linux/of_device.h>
9759e7ef 26#include <linux/platform_data/davinci_asp.h>
a75a053f 27#include <linux/math64.h>
ca3d9433 28#include <linux/bitmap.h>
540f1ba7 29#include <linux/gpio/driver.h>
b67f4487 30
6479285d 31#include <sound/asoundef.h>
b67f4487
C		 32#include <sound/core.h>
33#include <sound/pcm.h>
34#include <sound/pcm_params.h>
35#include <sound/initval.h>
36#include <sound/soc.h>
453c4990 37#include <sound/dmaengine_pcm.h>
b67f4487 38
f3f9cfa8 39#include "edma-pcm.h"
f2055e14 40#include "sdma-pcm.h"
fb0c3c6e 41#include "udma-pcm.h"
b67f4487
C		 42#include "davinci-mcasp.h"
43
0bf0e8ae
PU		 44#define MCASP_MAX_AFIFO_DEPTH 64
45
8ca51047 46#ifdef CONFIG_PM
1cc0c054
PU		 47static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
f114ce60
PU		 54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
1cc0c054 56 DAVINCI_MCASP_PDIR_REG,
540f1ba7 57 DAVINCI_MCASP_PFUNC_REG,
f114ce60
PU		 58 DAVINCI_MCASP_RXMASK_REG,
59 DAVINCI_MCASP_TXMASK_REG,
60 DAVINCI_MCASP_RXTDM_REG,
61 DAVINCI_MCASP_TXTDM_REG,
1cc0c054
PU		 62};
63
790bb94b 64struct davinci_mcasp_context {
1cc0c054 65 u32 config_regs[ARRAY_SIZE(context_regs)];
f114ce60
PU		 66 u32 afifo_regs[2]; /* for read/write fifo control registers */
67 u32 *xrsr_regs; /* for serializer configuration */
6afda7f5 68 bool pm_state;
790bb94b 69};
8ca51047 70#endif
790bb94b 71
a75a053f
JS		 72struct davinci_mcasp_ruledata {
73 struct davinci_mcasp *mcasp;
74 int serializers;
75};
76
70091a3e 77struct davinci_mcasp {
453c4990 78 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 79 void __iomem *base;
487dce88 80 u32 fifo_base;
21400a72 81 struct device *dev;
a7a3324a 82 struct snd_pcm_substream *substreams[2];
4a11ff26 83 unsigned int dai_fmt;
21400a72
PU		 84
85 /* McASP specific data */
86 int tdm_slots;
dd55ff83
JS		 87 u32 tdm_mask[2];
88 int slot_width;
21400a72 89 u8 op_mode;
bc184549 90 u8 dismod;
21400a72
PU		 91 u8 num_serializer;
92 u8 *serial_dir;
93 u8 version;
8267525c 94 u8 bclk_div;
4dcb5a0b 95 int streams;
a7a3324a 96 u32 irq_request[2];
9759e7ef 97 int dma_request[2];
21400a72 98
ab8b14b6
JS		 99 int sysclk_freq;
100 bool bclk_master;
764958f2 101 u32 auxclk_fs_ratio;
ab8b14b6 102
ca3d9433
PU		 103 unsigned long pdir; /* Pin direction bitfield */
104
21400a72
PU		 105 /* McASP FIFO related */
106 u8 txnumevt;
107 u8 rxnumevt;
108
cbc7956c
PU		 109 bool dat_port;
110
11277833
PU		 111 /* Used for comstraint setting on the second stream */
112 u32 channels;
2448c813 113 int max_format_width;
b7989e27 114 u8 active_serializers[2];
11277833 115
540f1ba7
PU		 116#ifdef CONFIG_GPIOLIB
117 struct gpio_chip gpio_chip;
118#endif
119
61754717 120#ifdef CONFIG_PM
790bb94b 121 struct davinci_mcasp_context context;
21400a72 122#endif
a75a053f
JS		 123
124 struct davinci_mcasp_ruledata ruledata[2];
5935a056 125 struct snd_pcm_hw_constraint_list chconstr[2];
21400a72
PU		 126};
127
f68205a7
PU		 128static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
129 u32 val)
b67f4487 130{
f68205a7 131 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 132 __raw_writel(__raw_readl(reg) | val, reg);
133}
134
f68205a7
PU		 135static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
136 u32 val)
b67f4487 137{
f68205a7 138 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 139 __raw_writel((__raw_readl(reg) & ~(val)), reg);
140}
141
f68205a7
PU		 142static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
143 u32 val, u32 mask)
b67f4487 144{
f68205a7 145 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 146 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
147}
148
f68205a7
PU		 149static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
150 u32 val)
b67f4487 151{
f68205a7 152 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 153}
154
f68205a7 155static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 156{
f68205a7 157 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 158}
159
f68205a7 160static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 161{
162 int i = 0;
163
f68205a7 164 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 165
166 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
167 /* loop count is to avoid the lock-up */
168 for (i = 0; i < 1000; i++) {
f68205a7 169 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 170 break;
171 }
172
f68205a7 173 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 174 printk(KERN_ERR "GBLCTL write error\n");
175}
176
4dcb5a0b
PU		 177static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
178{
f68205a7
PU		 179 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
180 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 181
182 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
183}
184
ca3d9433
PU		 185static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
186{
187 u32 bit = PIN_BIT_AMUTE;
188
189 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
190 if (enable)
191 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
192 else
193 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
194 }
195}
196
197static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
198{
199 u32 bit;
200
34a2a80f 201 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
ca3d9433
PU		 202 if (enable)
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
204 else
205 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
206 }
207}
208
70091a3e 209static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 210{
bb372af0
PU		 211 if (mcasp->rxnumevt) { /* enable FIFO */
212 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
213
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
216 }
217
44982735 218 /* Start clocks */
f68205a7
PU		 219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 221 /*
222 * When ASYNC == 0 the transmit and receive sections operate
223 * synchronously from the transmit clock and frame sync. We need to make
224 * sure that the TX signlas are enabled when starting reception.
225 */
226 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
34a2a80f 229 mcasp_set_clk_pdir(mcasp, true);
4dcb5a0b
PU		 230 }
231
44982735 232 /* Activate serializer(s) */
1003c27a 233 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
f68205a7 234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
44982735 235 /* Release RX state machine */
f68205a7 236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
44982735 237 /* Release Frame Sync generator */
f68205a7 238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b 239 if (mcasp_is_synchronous(mcasp))
f68205a7 240 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 241
242 /* enable receive IRQs */
243 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
b67f4487
C		 245}
246
70091a3e 247static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 248{
6a99fb5f
C		 249 u32 cnt;
250
bb372af0
PU		 251 if (mcasp->txnumevt) { /* enable FIFO */
252 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
253
254 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
255 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
256 }
257
36bcecd0 258 /* Start clocks */
f68205a7
PU		 259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
ca3d9433
PU		 261 mcasp_set_clk_pdir(mcasp, true);
262
36bcecd0 263 /* Activate serializer(s) */
1003c27a 264 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
f68205a7 265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
b67f4487 266
36bcecd0 267 /* wait for XDATA to be cleared */
6a99fb5f 268 cnt = 0;
e2a0c9fa
PU		 269 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
270 (cnt < 100000))
6a99fb5f
C		 271 cnt++;
272
ca3d9433
PU		 273 mcasp_set_axr_pdir(mcasp, true);
274
36bcecd0
PU		 275 /* Release TX state machine */
276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
277 /* Release Frame Sync generator */
278 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 279
280 /* enable transmit IRQs */
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
b67f4487
C		 283}
284
70091a3e 285static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 286{
4dcb5a0b
PU		 287 mcasp->streams++;
288
bb372af0 289 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 290 mcasp_start_tx(mcasp);
bb372af0 291 else
70091a3e 292 mcasp_start_rx(mcasp);
b67f4487
C		 293}
294
70091a3e 295static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 296{
a7a3324a
MLC		 297 /* disable IRQ sources */
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
299 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
300
4dcb5a0b
PU		 301 /*
302 * In synchronous mode stop the TX clocks if no other stream is
303 * running
304 */
ca3d9433
PU		 305 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
306 mcasp_set_clk_pdir(mcasp, false);
f68205a7 307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
ca3d9433 308 }
4dcb5a0b 309
f68205a7
PU		 310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
311 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 312
313 if (mcasp->rxnumevt) { /* disable FIFO */
314 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
315
316 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
317 }
b67f4487
C		 318}
319
70091a3e 320static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 321{
4dcb5a0b
PU		 322 u32 val = 0;
323
a7a3324a
MLC		 324 /* disable IRQ sources */
325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
326 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
327
4dcb5a0b
PU		 328 /*
329 * In synchronous mode keep TX clocks running if the capture stream is
330 * still running.
331 */
332 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
333 val = TXHCLKRST | TXCLKRST | TXFSRST;
ca3d9433
PU		 334 else
335 mcasp_set_clk_pdir(mcasp, false);
336
4dcb5a0b 337
f68205a7
PU		 338 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 340
341 if (mcasp->txnumevt) { /* disable FIFO */
342 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
343
344 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
345 }
ca3d9433
PU		 346
347 mcasp_set_axr_pdir(mcasp, false);
b67f4487
C		 348}
349
70091a3e 350static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 351{
4dcb5a0b
PU		 352 mcasp->streams--;
353
0380866a 354 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 355 mcasp_stop_tx(mcasp);
0380866a 356 else
70091a3e 357 mcasp_stop_rx(mcasp);
b67f4487
C		 358}
359
a7a3324a
MLC		 360static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
361{
362 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
363 struct snd_pcm_substream *substream;
364 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
365 u32 handled_mask = 0;
366 u32 stat;
367
368 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
369 if (stat & XUNDRN & irq_mask) {
370 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
371 handled_mask |= XUNDRN;
372
373 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
dae35d1f
TI		 374 if (substream)
375 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 376 }
377
378 if (!handled_mask)
379 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
380 stat);
381
382 if (stat & XRERR)
383 handled_mask |= XRERR;
384
385 /* Ack the handled event only */
386 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
387
388 return IRQ_RETVAL(handled_mask);
389}
390
391static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
392{
393 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
394 struct snd_pcm_substream *substream;
395 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
396 u32 handled_mask = 0;
397 u32 stat;
398
399 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
400 if (stat & ROVRN & irq_mask) {
401 dev_warn(mcasp->dev, "Receive buffer overflow\n");
402 handled_mask |= ROVRN;
403
404 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
dae35d1f
TI		 405 if (substream)
406 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 407 }
408
409 if (!handled_mask)
410 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
411 stat);
412
413 if (stat & XRERR)
414 handled_mask |= XRERR;
415
416 /* Ack the handled event only */
417 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
418
419 return IRQ_RETVAL(handled_mask);
420}
421
5a1b8a80
PU		 422static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
423{
424 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
425 irqreturn_t ret = IRQ_NONE;
426
427 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
428 ret = davinci_mcasp_tx_irq_handler(irq, data);
429
430 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
431 ret |= davinci_mcasp_rx_irq_handler(irq, data);
432
433 return ret;
434}
435
b67f4487
C		 436static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
437 unsigned int fmt)
438{
70091a3e 439 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 440 int ret = 0;
6dfa9a4e 441 u32 data_delay;
83f12503 442 bool fs_pol_rising;
ffd950f7 443 bool inv_fs = false;
b67f4487 444
4a11ff26
PU		 445 if (!fmt)
446 return 0;
447
1d17a04e 448 pm_runtime_get_sync(mcasp->dev);
5296cf2d 449 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 450 case SND_SOC_DAIFMT_DSP_A:
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
452 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 453 /* 1st data bit occur one ACLK cycle after the frame sync */
454 data_delay = 1;
455 break;
5296cf2d
DM		 456 case SND_SOC_DAIFMT_DSP_B:
457 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 460 /* No delay after FS */
461 data_delay = 0;
5296cf2d 462 break;
ffd950f7 463 case SND_SOC_DAIFMT_I2S:
5296cf2d 464 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 465 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 467 /* 1st data bit occur one ACLK cycle after the frame sync */
468 data_delay = 1;
ffd950f7
PU		 469 /* FS need to be inverted */
470 inv_fs = true;
5296cf2d 471 break;
816fe206 472 case SND_SOC_DAIFMT_RIGHT_J:
423761e0
PU		 473 case SND_SOC_DAIFMT_LEFT_J:
474 /* configure a full-word SYNC pulse (LRCLK) */
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
477 /* No delay after FS */
478 data_delay = 0;
479 break;
ffd950f7
PU		 480 default:
481 ret = -EINVAL;
482 goto out;
5296cf2d
DM		 483 }
484
6dfa9a4e
PU		 485 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
486 FSXDLY(3));
487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
488 FSRDLY(3));
489
b67f4487
C		 490 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
491 case SND_SOC_DAIFMT_CBS_CFS:
492 /* codec is clock and frame slave */
f68205a7
PU		 493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
494 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 495
f68205a7
PU		 496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 498
ca3d9433
PU		 499 /* BCLK */
500 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
501 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
502 /* Frame Sync */
503 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
504 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
505
ab8b14b6 506 mcasp->bclk_master = 1;
b67f4487 507 break;
226e2f1b
PU		 508 case SND_SOC_DAIFMT_CBS_CFM:
509 /* codec is clock slave and frame master */
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
512
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
515
ca3d9433
PU		 516 /* BCLK */
517 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
518 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
519 /* Frame Sync */
520 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
521 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
522
226e2f1b
PU		 523 mcasp->bclk_master = 1;
524 break;
517ee6cf
C		 525 case SND_SOC_DAIFMT_CBM_CFS:
526 /* codec is clock master and frame slave */
f68205a7
PU		 527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 529
f68205a7
PU		 530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 532
ca3d9433
PU		 533 /* BCLK */
534 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
535 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
536 /* Frame Sync */
537 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
538 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
539
ab8b14b6 540 mcasp->bclk_master = 0;
517ee6cf 541 break;
b67f4487
C		 542 case SND_SOC_DAIFMT_CBM_CFM:
543 /* codec is clock and frame master */
f68205a7
PU		 544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 546
f68205a7
PU		 547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 549
ca3d9433
PU		 550 /* BCLK */
551 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
552 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
553 /* Frame Sync */
554 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
555 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
556
ab8b14b6 557 mcasp->bclk_master = 0;
b67f4487 558 break;
b67f4487 559 default:
1d17a04e
PU		 560 ret = -EINVAL;
561 goto out;
b67f4487
C		 562 }
563
564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
565 case SND_SOC_DAIFMT_IB_NF:
f68205a7 566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 568 fs_pol_rising = true;
b67f4487 569 break;
b67f4487 570 case SND_SOC_DAIFMT_NB_IF:
f68205a7 571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 573 fs_pol_rising = false;
b67f4487 574 break;
b67f4487 575 case SND_SOC_DAIFMT_IB_IF:
f68205a7 576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 577 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 578 fs_pol_rising = false;
b67f4487 579 break;
b67f4487 580 case SND_SOC_DAIFMT_NB_NF:
f68205a7 581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 583 fs_pol_rising = true;
b67f4487 584 break;
b67f4487 585 default:
1d17a04e 586 ret = -EINVAL;
83f12503
PU		 587 goto out;
588 }
589
ffd950f7
PU		 590 if (inv_fs)
591 fs_pol_rising = !fs_pol_rising;
592
83f12503
PU		 593 if (fs_pol_rising) {
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
595 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
596 } else {
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 599 }
4a11ff26
PU		 600
601 mcasp->dai_fmt = fmt;
1d17a04e 602out:
6afda7f5 603 pm_runtime_put(mcasp->dev);
1d17a04e 604 return ret;
b67f4487
C		 605}
606
226e73e2 607static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
8813543e 608 int div, bool explicit)
4ed8c9b7 609{
6afda7f5 610 pm_runtime_get_sync(mcasp->dev);
4ed8c9b7 611 switch (div_id) {
20d4b107 612 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
f68205a7 613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 614 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 616 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
617 break;
618
20d4b107 619 case MCASP_CLKDIV_BCLK: /* BCLK divider */
f68205a7 620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 621 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 622 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7 623 ACLKRDIV(div - 1), ACLKRDIV_MASK);
8813543e
JS		 624 if (explicit)
625 mcasp->bclk_div = div;
4ed8c9b7
DM		 626 break;
627
20d4b107
PU		 628 case MCASP_CLKDIV_BCLK_FS_RATIO:
629 /*
14a998be
JS		 630 * BCLK/LRCLK ratio descries how many bit-clock cycles
631 * fit into one frame. The clock ratio is given for a
632 * full period of data (for I2S format both left and
633 * right channels), so it has to be divided by number
634 * of tdm-slots (for I2S - divided by 2).
635 * Instead of storing this ratio, we calculate a new
636 * tdm_slot width by dividing the the ratio by the
637 * number of configured tdm slots.
638 */
639 mcasp->slot_width = div / mcasp->tdm_slots;
640 if (div % mcasp->tdm_slots)
641 dev_warn(mcasp->dev,
642 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
643 __func__, div, mcasp->tdm_slots);
1b3bc060
DM		 644 break;
645
4ed8c9b7
DM		 646 default:
647 return -EINVAL;
648 }
649
6afda7f5 650 pm_runtime_put(mcasp->dev);
4ed8c9b7
DM		 651 return 0;
652}
653
8813543e
JS		 654static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
655 int div)
656{
226e73e2
PU		 657 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
658
659 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
8813543e
JS		 660}
661
5b66aa2d
DM		 662static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
663 unsigned int freq, int dir)
664{
70091a3e 665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d 666
6afda7f5 667 pm_runtime_get_sync(mcasp->dev);
253f584a
PU		 668
669 if (dir == SND_SOC_CLOCK_IN) {
670 switch (clk_id) {
671 case MCASP_CLK_HCLK_AHCLK:
672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
673 AHCLKXE);
674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
675 AHCLKRE);
676 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
677 break;
678 case MCASP_CLK_HCLK_AUXCLK:
679 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
680 AHCLKXE);
681 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
682 AHCLKRE);
683 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
684 break;
685 default:
686 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
687 goto out;
688 }
689 } else {
690 /* Select AUXCLK as HCLK */
f68205a7
PU		 691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
692 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
ca3d9433 693 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
5b66aa2d 694 }
253f584a
PU		 695 /*
696 * When AHCLK X/R is selected to be output it means that the HCLK is
697 * the same clock - coming via AUXCLK.
698 */
ab8b14b6 699 mcasp->sysclk_freq = freq;
253f584a 700out:
6afda7f5 701 pm_runtime_put(mcasp->dev);
5b66aa2d
DM		 702 return 0;
703}
704
dd55ff83
JS		 705/* All serializers must have equal number of channels */
706static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
707 int serializers)
708{
709 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
710 unsigned int *list = (unsigned int *) cl->list;
711 int slots = mcasp->tdm_slots;
712 int i, count = 0;
713
714 if (mcasp->tdm_mask[stream])
715 slots = hweight32(mcasp->tdm_mask[stream]);
716
e4798d26 717 for (i = 1; i <= slots; i++)
dd55ff83
JS		 718 list[count++] = i;
719
720 for (i = 2; i <= serializers; i++)
721 list[count++] = i*slots;
722
723 cl->count = count;
724
725 return 0;
726}
727
728static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
729{
730 int rx_serializers = 0, tx_serializers = 0, ret, i;
731
732 for (i = 0; i < mcasp->num_serializer; i++)
733 if (mcasp->serial_dir[i] == TX_MODE)
734 tx_serializers++;
735 else if (mcasp->serial_dir[i] == RX_MODE)
736 rx_serializers++;
737
738 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
739 tx_serializers);
740 if (ret)
741 return ret;
742
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
744 rx_serializers);
745
746 return ret;
747}
748
749
750static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
751 unsigned int tx_mask,
752 unsigned int rx_mask,
753 int slots, int slot_width)
754{
755 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
756
757 dev_dbg(mcasp->dev,
758 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
759 __func__, tx_mask, rx_mask, slots, slot_width);
760
761 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
762 dev_err(mcasp->dev,
763 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
764 tx_mask, rx_mask, slots);
765 return -EINVAL;
766 }
767
768 if (slot_width &&
769 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
770 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
771 __func__, slot_width);
772 return -EINVAL;
773 }
774
775 mcasp->tdm_slots = slots;
1bdd5932
AD		 776 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
777 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
dd55ff83
JS		 778 mcasp->slot_width = slot_width;
779
780 return davinci_mcasp_set_ch_constraints(mcasp);
781}
782
70091a3e 783static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
14a998be 784 int sample_width)
b67f4487 785{
ba764b3d 786 u32 fmt;
816fe206 787 u32 tx_rotate, rx_rotate, slot_width;
14a998be 788 u32 mask = (1ULL << sample_width) - 1;
b67f4487 789
816fe206
PU		 790 if (mcasp->slot_width)
791 slot_width = mcasp->slot_width;
2448c813
PU		 792 else if (mcasp->max_format_width)
793 slot_width = mcasp->max_format_width;
816fe206
PU		 794 else
795 slot_width = sample_width;
1b3bc060 796 /*
816fe206
PU		 797 * TX rotation:
798 * right aligned formats: rotate w/ slot_width
799 * left aligned formats: rotate w/ sample_width
800 *
801 * RX rotation:
802 * right aligned formats: no rotation needed
803 * left aligned formats: rotate w/ (slot_width - sample_width)
1b3bc060 804 */
816fe206
PU		 805 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
806 SND_SOC_DAIFMT_RIGHT_J) {
807 tx_rotate = (slot_width / 4) & 0x7;
808 rx_rotate = 0;
809 } else {
810 tx_rotate = (sample_width / 4) & 0x7;
14a998be 811 rx_rotate = (slot_width - sample_width) / 4;
d742b925 812 }
1b3bc060 813
ba764b3d 814 /* mapping of the XSSZ bit-field as described in the datasheet */
14a998be 815 fmt = (slot_width >> 1) - 1;
b67f4487 816
70091a3e 817 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 818 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
819 RXSSZ(0x0F));
820 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
821 TXSSZ(0x0F));
822 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
823 TXROT(7));
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
825 RXROT(7));
826 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 827 }
828
f68205a7 829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 830
b67f4487
C		 831 return 0;
832}
833
662ffae9 834static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 835 int period_words, int channels)
b67f4487 836{
5f04c603 837 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 838 int i;
6a99fb5f
C		 839 u8 tx_ser = 0;
840 u8 rx_ser = 0;
70091a3e 841 u8 slots = mcasp->tdm_slots;
2952b27e 842 u8 max_active_serializers = (channels + slots - 1) / slots;
b7989e27 843 u8 max_rx_serializers, max_tx_serializers;
72383192 844 int active_serializers, numevt;
487dce88 845 u32 reg;
b67f4487 846 /* Default configuration */
40448e5e 847 if (mcasp->version < MCASP_VERSION_3)
f68205a7 848 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487 849
b67f4487 850 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
852 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b7989e27
PU		 853 max_tx_serializers = max_active_serializers;
854 max_rx_serializers =
855 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
b67f4487 856 } else {
f68205a7
PU		 857 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
858 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b7989e27
PU		 859 max_tx_serializers =
860 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
861 max_rx_serializers = max_active_serializers;
b67f4487
C		 862 }
863
70091a3e 864 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 865 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
866 mcasp->serial_dir[i]);
70091a3e 867 if (mcasp->serial_dir[i] == TX_MODE &&
b7989e27 868 tx_ser < max_tx_serializers) {
19db62ea 869 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
bc184549 870 mcasp->dismod, DISMOD_MASK);
ca3d9433 871 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 872 tx_ser++;
70091a3e 873 } else if (mcasp->serial_dir[i] == RX_MODE &&
b7989e27 874 rx_ser < max_rx_serializers) {
ca3d9433 875 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 876 rx_ser++;
5dd17a3c
PU		 877 } else {
878 /* Inactive or unused pin, set it to inactive */
f68205a7
PU		 879 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
880 SRMOD_INACTIVE, SRMOD_MASK);
5dd17a3c
PU		 881 /* If unused, set DISMOD for the pin */
882 if (mcasp->serial_dir[i] != INACTIVE_MODE)
883 mcasp_mod_bits(mcasp,
884 DAVINCI_MCASP_XRSRCTL_REG(i),
885 mcasp->dismod, DISMOD_MASK);
ca3d9433 886 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f
C		 887 }
888 }
889
0bf0e8ae
PU		 890 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
891 active_serializers = tx_ser;
892 numevt = mcasp->txnumevt;
893 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
894 } else {
895 active_serializers = rx_ser;
896 numevt = mcasp->rxnumevt;
897 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
898 }
ecf327c7 899
0bf0e8ae 900 if (active_serializers < max_active_serializers) {
70091a3e 901 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 902 "enabled in mcasp (%d)\n", channels,
903 active_serializers * slots);
ecf327c7
DM		 904 return -EINVAL;
905 }
906
0bf0e8ae 907 /* AFIFO is not in use */
5f04c603
PU		 908 if (!numevt) {
909 /* Configure the burst size for platform drivers */
33445643
PU		 910 if (active_serializers > 1) {
911 /*
912 * If more than one serializers are in use we have one
913 * DMA request to provide data for all serializers.
914 * For example if three serializers are enabled the DMA
915 * need to transfer three words per DMA request.
916 */
33445643
PU		 917 dma_data->maxburst = active_serializers;
918 } else {
33445643
PU		 919 dma_data->maxburst = 0;
920 }
b7989e27
PU		 921
922 goto out;
5f04c603 923 }
6a99fb5f 924
dd093a0f
PU		 925 if (period_words % active_serializers) {
926 dev_err(mcasp->dev, "Invalid combination of period words and "
927 "active serializers: %d, %d\n", period_words,
928 active_serializers);
929 return -EINVAL;
930 }
931
932 /*
933 * Calculate the optimal AFIFO depth for platform side:
934 * The number of words for numevt need to be in steps of active
935 * serializers.
936 */
72383192
PU		 937 numevt = (numevt / active_serializers) * active_serializers;
938
dd093a0f
PU		 939 while (period_words % numevt && numevt > 0)
940 numevt -= active_serializers;
941 if (numevt <= 0)
0bf0e8ae 942 numevt = active_serializers;
487dce88 943
0bf0e8ae
PU		 944 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
945 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 946
5f04c603 947 /* Configure the burst size for platform drivers */
33445643
PU		 948 if (numevt == 1)
949 numevt = 0;
5f04c603
PU		 950 dma_data->maxburst = numevt;
951
b7989e27
PU		 952out:
953 mcasp->active_serializers[stream] = active_serializers;
954
2952b27e 955 return 0;
b67f4487
C		 956}
957
18a4f557
MLC		 958static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
959 int channels)
b67f4487
C		 960{
961 int i, active_slots;
18a4f557
MLC		 962 int total_slots;
963 int active_serializers;
b67f4487 964 u32 mask = 0;
cbc7956c 965 u32 busel = 0;
b67f4487 966
18a4f557
MLC		 967 total_slots = mcasp->tdm_slots;
968
969 /*
970 * If more than one serializer is needed, then use them with
dd55ff83
JS		 971 * all the specified tdm_slots. Otherwise, one serializer can
972 * cope with the transaction using just as many slots as there
973 * are channels in the stream.
18a4f557 974 */
dd55ff83
JS		 975 if (mcasp->tdm_mask[stream]) {
976 active_slots = hweight32(mcasp->tdm_mask[stream]);
977 active_serializers = (channels + active_slots - 1) /
978 active_slots;
fd14f443 979 if (active_serializers == 1)
dd55ff83 980 active_slots = channels;
fd14f443
PU		 981 for (i = 0; i < total_slots; i++) {
982 if ((1 << i) & mcasp->tdm_mask[stream]) {
983 mask |= (1 << i);
984 if (--active_slots <= 0)
985 break;
dd55ff83
JS		 986 }
987 }
988 } else {
989 active_serializers = (channels + total_slots - 1) / total_slots;
990 if (active_serializers == 1)
991 active_slots = channels;
992 else
993 active_slots = total_slots;
b67f4487 994
dd55ff83
JS		 995 for (i = 0; i < active_slots; i++)
996 mask |= (1 << i);
997 }
5dd17a3c 998
f68205a7 999 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 1000
cbc7956c
PU		 1001 if (!mcasp->dat_port)
1002 busel = TXSEL;
1003
dd55ff83
JS		 1004 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1006 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1007 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1008 FSXMOD(total_slots), FSXMOD(0x1FF));
1009 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1012 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1013 FSRMOD(total_slots), FSRMOD(0x1FF));
0ad7d3a0
PU		 1014 /*
1015 * If McASP is set to be TX/RX synchronous and the playback is
1016 * not running already we need to configure the TX slots in
1017 * order to have correct FSX on the bus
1018 */
1019 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1020 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1021 FSXMOD(total_slots), FSXMOD(0x1FF));
dd55ff83 1022 }
2c56c4c2
PU		 1023
1024 return 0;
b67f4487
C		 1025}
1026
1027/* S/PDIF */
6479285d
DM		 1028static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1029 unsigned int rate)
b67f4487 1030{
6479285d
DM		 1031 u32 cs_value = 0;
1032 u8 *cs_bytes = (u8*) &cs_value;
1033
b67f4487
C		 1034 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1035 and LSB first */
f68205a7 1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 1037
1038 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 1039 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 1040
1041 /* Set the TX tdm : for all the slots */
f68205a7 1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 1043
1044 /* Set the TX clock controls : div = 1 and internal */
f68205a7 1045 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 1046
f68205a7 1047 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 1048
1049 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 1050 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 1051
1052 /* Enable the DIT */
f68205a7 1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2 1054
6479285d
DM		 1055 /* Set S/PDIF channel status bits */
1056 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1057 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1058
1059 switch (rate) {
1060 case 22050:
1061 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1062 break;
1063 case 24000:
1064 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1065 break;
1066 case 32000:
1067 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1068 break;
1069 case 44100:
1070 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1071 break;
1072 case 48000:
1073 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1074 break;
1075 case 88200:
1076 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1077 break;
1078 case 96000:
1079 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1080 break;
1081 case 176400:
1082 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1083 break;
1084 case 192000:
1085 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1086 break;
1087 default:
1088 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1089 return -EINVAL;
1090 }
1091
1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1093 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1094
2c56c4c2 1095 return 0;
b67f4487
C		 1096}
1097
a75a053f 1098static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
764958f2 1099 unsigned int sysclk_freq,
3e9bee11 1100 unsigned int bclk_freq, bool set)
a75a053f 1101{
ddecd149
PU		 1102 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1103 int div = sysclk_freq / bclk_freq;
1104 int rem = sysclk_freq % bclk_freq;
764958f2 1105 int error_ppm;
ddecd149
PU		 1106 int aux_div = 1;
1107
1108 if (div > (ACLKXDIV_MASK + 1)) {
1109 if (reg & AHCLKXE) {
1110 aux_div = div / (ACLKXDIV_MASK + 1);
1111 if (div % (ACLKXDIV_MASK + 1))
1112 aux_div++;
1113
1114 sysclk_freq /= aux_div;
1115 div = sysclk_freq / bclk_freq;
1116 rem = sysclk_freq % bclk_freq;
1117 } else if (set) {
1118 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1119 sysclk_freq);
1120 }
1121 }
a75a053f
JS		 1122
1123 if (rem != 0) {
1124 if (div == 0 ||
ddecd149
PU		 1125 ((sysclk_freq / div) - bclk_freq) >
1126 (bclk_freq - (sysclk_freq / (div+1)))) {
a75a053f
JS		 1127 div++;
1128 rem = rem - bclk_freq;
1129 }
1130 }
3e9bee11
PU		 1131 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1132 (int)bclk_freq)) / div - 1000000;
a75a053f 1133
3e9bee11
PU		 1134 if (set) {
1135 if (error_ppm)
1136 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1137 error_ppm);
1138
1139 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
ddecd149
PU		 1140 if (reg & AHCLKXE)
1141 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1142 aux_div, 0);
3e9bee11 1143 }
a75a053f 1144
3e9bee11 1145 return error_ppm;
a75a053f
JS		 1146}
1147
5fcb457a
PU		 1148static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1149{
1150 if (!mcasp->txnumevt)
1151 return 0;
1152
1153 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1154}
1155
1156static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1157{
1158 if (!mcasp->rxnumevt)
1159 return 0;
1160
1161 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1162}
1163
1164static snd_pcm_sframes_t davinci_mcasp_delay(
1165 struct snd_pcm_substream *substream,
1166 struct snd_soc_dai *cpu_dai)
1167{
1168 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1169 u32 fifo_use;
1170
1171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1172 fifo_use = davinci_mcasp_tx_delay(mcasp);
1173 else
1174 fifo_use = davinci_mcasp_rx_delay(mcasp);
1175
1176 /*
1177 * Divide the used locations with the channel count to get the
1178 * FIFO usage in samples (don't care about partial samples in the
1179 * buffer).
1180 */
1181 return fifo_use / substream->runtime->channels;
1182}
1183
b67f4487
C		 1184static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1185 struct snd_pcm_hw_params *params,
1186 struct snd_soc_dai *cpu_dai)
1187{
70091a3e 1188 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 1189 int word_length;
a7e46bd9 1190 int channels = params_channels(params);
dd093a0f 1191 int period_size = params_period_size(params);
2c56c4c2 1192 int ret;
ab8b14b6 1193
b7989e27
PU		 1194 switch (params_format(params)) {
1195 case SNDRV_PCM_FORMAT_U8:
1196 case SNDRV_PCM_FORMAT_S8:
1197 word_length = 8;
1198 break;
1199
1200 case SNDRV_PCM_FORMAT_U16_LE:
1201 case SNDRV_PCM_FORMAT_S16_LE:
1202 word_length = 16;
1203 break;
1204
1205 case SNDRV_PCM_FORMAT_U24_3LE:
1206 case SNDRV_PCM_FORMAT_S24_3LE:
1207 word_length = 24;
1208 break;
1209
1210 case SNDRV_PCM_FORMAT_U24_LE:
1211 case SNDRV_PCM_FORMAT_S24_LE:
1212 word_length = 24;
1213 break;
1214
1215 case SNDRV_PCM_FORMAT_U32_LE:
1216 case SNDRV_PCM_FORMAT_S32_LE:
1217 word_length = 32;
1218 break;
1219
1220 default:
1221 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1222 return -EINVAL;
1223 }
1224
4a11ff26
PU		 1225 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1226 if (ret)
1227 return ret;
1228
8267525c
DM		 1229 /*
1230 * If mcasp is BCLK master, and a BCLK divider was not provided by
1231 * the machine driver, we need to calculate the ratio.
1232 */
1233 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1f114f77 1234 int slots = mcasp->tdm_slots;
a75a053f
JS		 1235 int rate = params_rate(params);
1236 int sbits = params_width(params);
a75a053f 1237
dd55ff83
JS		 1238 if (mcasp->slot_width)
1239 sbits = mcasp->slot_width;
1240
764958f2
PU		 1241 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1242 rate * sbits * slots, true);
ab8b14b6
JS		 1243 }
1244
dd093a0f
PU		 1245 ret = mcasp_common_hw_param(mcasp, substream->stream,
1246 period_size * channels, channels);
0f7d9a63
PU		 1247 if (ret)
1248 return ret;
1249
70091a3e 1250 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
6479285d 1251 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
b67f4487 1252 else
18a4f557
MLC		 1253 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1254 channels);
2c56c4c2
PU		 1255
1256 if (ret)
1257 return ret;
b67f4487 1258
70091a3e 1259 davinci_config_channel_size(mcasp, word_length);
b67f4487 1260
2448c813 1261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
11277833 1262 mcasp->channels = channels;
2448c813
PU		 1263 if (!mcasp->max_format_width)
1264 mcasp->max_format_width = word_length;
1265 }
11277833 1266
b67f4487
C		 1267 return 0;
1268}
1269
1270static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1271 int cmd, struct snd_soc_dai *cpu_dai)
1272{
70091a3e 1273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 1274 int ret = 0;
1275
1276 switch (cmd) {
b67f4487 1277 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 1278 case SNDRV_PCM_TRIGGER_START:
1279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 1280 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 1281 break;
b67f4487 1282 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 1283 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 1284 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 1285 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 1286 break;
1287
1288 default:
1289 ret = -EINVAL;
1290 }
1291
1292 return ret;
1293}
1294
1e112c35
PU		 1295static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1296 struct snd_pcm_hw_rule *rule)
1297{
1298 struct davinci_mcasp_ruledata *rd = rule->private;
1299 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1300 struct snd_mask nfmt;
1301 int i, slot_width;
1302
1303 snd_mask_none(&nfmt);
1304 slot_width = rd->mcasp->slot_width;
1305
1306 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1307 if (snd_mask_test(fmt, i)) {
1308 if (snd_pcm_format_width(i) <= slot_width) {
1309 snd_mask_set(&nfmt, i);
1310 }
1311 }
1312 }
1313
1314 return snd_mask_refine(fmt, &nfmt);
1315}
1316
2448c813
PU		 1317static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1318 struct snd_pcm_hw_rule *rule)
1319{
1320 struct davinci_mcasp_ruledata *rd = rule->private;
1321 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1322 struct snd_mask nfmt;
1323 int i, format_width;
1324
1325 snd_mask_none(&nfmt);
1326 format_width = rd->mcasp->max_format_width;
1327
1328 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1329 if (snd_mask_test(fmt, i)) {
1330 if (snd_pcm_format_width(i) == format_width) {
1331 snd_mask_set(&nfmt, i);
1332 }
1333 }
1334 }
1335
1336 return snd_mask_refine(fmt, &nfmt);
1337}
1338
a75a053f
JS		 1339static const unsigned int davinci_mcasp_dai_rates[] = {
1340 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1341 88200, 96000, 176400, 192000,
1342};
1343
1344#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1345
1346static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1347 struct snd_pcm_hw_rule *rule)
1348{
1349 struct davinci_mcasp_ruledata *rd = rule->private;
1350 struct snd_interval *ri =
1351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1352 int sbits = params_width(params);
1f114f77 1353 int slots = rd->mcasp->tdm_slots;
518f6bab
JS		 1354 struct snd_interval range;
1355 int i;
a75a053f 1356
dd55ff83
JS		 1357 if (rd->mcasp->slot_width)
1358 sbits = rd->mcasp->slot_width;
1359
518f6bab
JS		 1360 snd_interval_any(&range);
1361 range.empty = 1;
a75a053f
JS		 1362
1363 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
518f6bab 1364 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
764958f2
PU		 1365 uint bclk_freq = sbits * slots *
1366 davinci_mcasp_dai_rates[i];
1367 unsigned int sysclk_freq;
a75a053f
JS		 1368 int ppm;
1369
764958f2
PU		 1370 if (rd->mcasp->auxclk_fs_ratio)
1371 sysclk_freq = davinci_mcasp_dai_rates[i] *
1372 rd->mcasp->auxclk_fs_ratio;
1373 else
1374 sysclk_freq = rd->mcasp->sysclk_freq;
1375
1376 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1377 bclk_freq, false);
518f6bab
JS		 1378 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1379 if (range.empty) {
1380 range.min = davinci_mcasp_dai_rates[i];
1381 range.empty = 0;
1382 }
1383 range.max = davinci_mcasp_dai_rates[i];
1384 }
a75a053f
JS		 1385 }
1386 }
518f6bab 1387
a75a053f 1388 dev_dbg(rd->mcasp->dev,
518f6bab
JS		 1389 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1390 ri->min, ri->max, range.min, range.max, sbits, slots);
a75a053f 1391
518f6bab
JS		 1392 return snd_interval_refine(hw_param_interval(params, rule->var),
1393 &range);
a75a053f
JS		 1394}
1395
1396static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1397 struct snd_pcm_hw_rule *rule)
1398{
1399 struct davinci_mcasp_ruledata *rd = rule->private;
1400 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1401 struct snd_mask nfmt;
1402 int rate = params_rate(params);
1f114f77 1403 int slots = rd->mcasp->tdm_slots;
a75a053f
JS		 1404 int i, count = 0;
1405
1406 snd_mask_none(&nfmt);
1407
9be072a6 1408 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
a75a053f 1409 if (snd_mask_test(fmt, i)) {
dd55ff83 1410 uint sbits = snd_pcm_format_width(i);
764958f2 1411 unsigned int sysclk_freq;
a75a053f
JS		 1412 int ppm;
1413
764958f2
PU		 1414 if (rd->mcasp->auxclk_fs_ratio)
1415 sysclk_freq = rate *
1416 rd->mcasp->auxclk_fs_ratio;
1417 else
1418 sysclk_freq = rd->mcasp->sysclk_freq;
1419
dd55ff83
JS		 1420 if (rd->mcasp->slot_width)
1421 sbits = rd->mcasp->slot_width;
1422
764958f2 1423 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
3e9bee11
PU		 1424 sbits * slots * rate,
1425 false);
a75a053f
JS		 1426 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1427 snd_mask_set(&nfmt, i);
1428 count++;
1429 }
1430 }
1431 }
1432 dev_dbg(rd->mcasp->dev,
1f114f77
JS		 1433 "%d possible sample format for %d Hz and %d tdm slots\n",
1434 count, rate, slots);
a75a053f
JS		 1435
1436 return snd_mask_refine(fmt, &nfmt);
1437}
1438
d43c17da
PU		 1439static int davinci_mcasp_hw_rule_min_periodsize(
1440 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1441{
1442 struct snd_interval *period_size = hw_param_interval(params,
1443 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1444 struct snd_interval frames;
1445
1446 snd_interval_any(&frames);
1447 frames.min = 64;
1448 frames.integer = 1;
1449
1450 return snd_interval_refine(period_size, &frames);
1451}
1452
11277833
PU		 1453static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1454 struct snd_soc_dai *cpu_dai)
1455{
1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
4cd9db08
PU		 1457 struct davinci_mcasp_ruledata *ruledata =
1458 &mcasp->ruledata[substream->stream];
11277833 1459 u32 max_channels = 0;
1e112c35 1460 int i, dir, ret;
dd55ff83
JS		 1461 int tdm_slots = mcasp->tdm_slots;
1462
19357366
PU		 1463 /* Do not allow more then one stream per direction */
1464 if (mcasp->substreams[substream->stream])
1465 return -EBUSY;
11277833 1466
a7a3324a
MLC		 1467 mcasp->substreams[substream->stream] = substream;
1468
19357366
PU		 1469 if (mcasp->tdm_mask[substream->stream])
1470 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1471
11277833
PU		 1472 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1473 return 0;
1474
1475 /*
1476 * Limit the maximum allowed channels for the first stream:
1477 * number of serializers for the direction * tdm slots per serializer
1478 */
1479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1480 dir = TX_MODE;
1481 else
1482 dir = RX_MODE;
1483
1484 for (i = 0; i < mcasp->num_serializer; i++) {
1485 if (mcasp->serial_dir[i] == dir)
1486 max_channels++;
1487 }
4cd9db08 1488 ruledata->serializers = max_channels;
1e112c35 1489 ruledata->mcasp = mcasp;
dd55ff83 1490 max_channels *= tdm_slots;
11277833
PU		 1491 /*
1492 * If the already active stream has less channels than the calculated
b7989e27
PU		 1493 * limit based on the seirializers * tdm_slots, and only one serializer
1494 * is in use we need to use that as a constraint for the second stream.
1495 * Otherwise (first stream or less allowed channels or more than one
1496 * serializer in use) we use the calculated constraint.
11277833 1497 */
b7989e27
PU		 1498 if (mcasp->channels && mcasp->channels < max_channels &&
1499 ruledata->serializers == 1)
11277833 1500 max_channels = mcasp->channels;
dd55ff83
JS		 1501 /*
1502 * But we can always allow channels upto the amount of
1503 * the available tdm_slots.
1504 */
1505 if (max_channels < tdm_slots)
1506 max_channels = tdm_slots;
11277833
PU		 1507
1508 snd_pcm_hw_constraint_minmax(substream->runtime,
1509 SNDRV_PCM_HW_PARAM_CHANNELS,
e4798d26 1510 0, max_channels);
a75a053f 1511
dd55ff83
JS		 1512 snd_pcm_hw_constraint_list(substream->runtime,
1513 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1514 &mcasp->chconstr[substream->stream]);
1515
2448c813
PU		 1516 if (mcasp->max_format_width) {
1517 /*
1518 * Only allow formats which require same amount of bits on the
1519 * bus as the currently running stream
1520 */
1521 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1522 SNDRV_PCM_HW_PARAM_FORMAT,
1523 davinci_mcasp_hw_rule_format_width,
1524 ruledata,
1525 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1526 if (ret)
1527 return ret;
1528 }
1529 else if (mcasp->slot_width) {
1e112c35
PU		 1530 /* Only allow formats require <= slot_width bits on the bus */
1531 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1532 SNDRV_PCM_HW_PARAM_FORMAT,
1533 davinci_mcasp_hw_rule_slot_width,
1534 ruledata,
1535 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1536 if (ret)
1537 return ret;
1538 }
5935a056 1539
a75a053f
JS		 1540 /*
1541 * If we rely on implicit BCLK divider setting we should
1542 * set constraints based on what we can provide.
1543 */
1544 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
a75a053f
JS		 1545 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1546 SNDRV_PCM_HW_PARAM_RATE,
1547 davinci_mcasp_hw_rule_rate,
4cd9db08 1548 ruledata,
1f114f77 1549 SNDRV_PCM_HW_PARAM_FORMAT, -1);
a75a053f
JS		 1550 if (ret)
1551 return ret;
1552 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1553 SNDRV_PCM_HW_PARAM_FORMAT,
1554 davinci_mcasp_hw_rule_format,
4cd9db08 1555 ruledata,
1f114f77 1556 SNDRV_PCM_HW_PARAM_RATE, -1);
a75a053f
JS		 1557 if (ret)
1558 return ret;
1559 }
1560
d43c17da
PU		 1561 snd_pcm_hw_rule_add(substream->runtime, 0,
1562 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1563 davinci_mcasp_hw_rule_min_periodsize, NULL,
1564 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1565
11277833
PU		 1566 return 0;
1567}
1568
1569static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1570 struct snd_soc_dai *cpu_dai)
1571{
1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1573
a7a3324a 1574 mcasp->substreams[substream->stream] = NULL;
b7989e27 1575 mcasp->active_serializers[substream->stream] = 0;
a7a3324a 1576
11277833
PU		 1577 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1578 return;
1579
2448c813 1580 if (!cpu_dai->active) {
11277833 1581 mcasp->channels = 0;
2448c813
PU		 1582 mcasp->max_format_width = 0;
1583 }
11277833
PU		 1584}
1585
85e7652d 1586static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
11277833
PU		 1587 .startup = davinci_mcasp_startup,
1588 .shutdown = davinci_mcasp_shutdown,
b67f4487 1589 .trigger = davinci_mcasp_trigger,
5fcb457a 1590 .delay = davinci_mcasp_delay,
b67f4487
C		 1591 .hw_params = davinci_mcasp_hw_params,
1592 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 1593 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 1594 .set_sysclk = davinci_mcasp_set_sysclk,
dd55ff83 1595 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
b67f4487
C		 1596};
1597
d5902f69
PU		 1598static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1599{
1600 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1601
9759e7ef
PU		 1602 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1603 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
d5902f69
PU		 1604
1605 return 0;
1606}
1607
ed29cd5e
PU		 1608#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1609
0a9d1385
BG		 1610#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1611 SNDRV_PCM_FMTBIT_U8 | \
1612 SNDRV_PCM_FMTBIT_S16_LE | \
1613 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 1614 SNDRV_PCM_FMTBIT_S24_LE | \
1615 SNDRV_PCM_FMTBIT_U24_LE | \
1616 SNDRV_PCM_FMTBIT_S24_3LE | \
1617 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 1618 SNDRV_PCM_FMTBIT_S32_LE | \
1619 SNDRV_PCM_FMTBIT_U32_LE)
1620
f0fba2ad 1621static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 1622 {
f0fba2ad 1623 .name = "davinci-mcasp.0",
d5902f69 1624 .probe = davinci_mcasp_dai_probe,
b67f4487 1625 .playback = {
e4798d26 1626 .channels_min = 1,
2952b27e 1627 .channels_max = 32 * 16,
b67f4487 1628 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1629 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1630 },
1631 .capture = {
e4798d26 1632 .channels_min = 1,
2952b27e 1633 .channels_max = 32 * 16,
b67f4487 1634 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1635 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1636 },
1637 .ops = &davinci_mcasp_dai_ops,
1638
295c3405 1639 .symmetric_rates = 1,
b67f4487
C		 1640 },
1641 {
58e48d97 1642 .name = "davinci-mcasp.1",
d5902f69 1643 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 1644 .playback = {
1645 .channels_min = 1,
1646 .channels_max = 384,
1647 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1648 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1649 },
1650 .ops = &davinci_mcasp_dai_ops,
1651 },
1652
1653};
b67f4487 1654
eeef0eda
KM		 1655static const struct snd_soc_component_driver davinci_mcasp_component = {
1656 .name = "davinci-mcasp",
1657};
1658
256ba181 1659/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 1660static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 1661 .tx_dma_offset = 0x400,
1662 .rx_dma_offset = 0x400,
256ba181
JS		 1663 .version = MCASP_VERSION_1,
1664};
1665
d1debafc 1666static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 1667 .tx_dma_offset = 0x2000,
1668 .rx_dma_offset = 0x2000,
256ba181
JS		 1669 .version = MCASP_VERSION_2,
1670};
1671
d1debafc 1672static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 1673 .tx_dma_offset = 0,
1674 .rx_dma_offset = 0,
256ba181
JS		 1675 .version = MCASP_VERSION_3,
1676};
1677
d1debafc 1678static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
9ac0013c
PU		 1679 /* The CFG port offset will be calculated if it is needed */
1680 .tx_dma_offset = 0,
1681 .rx_dma_offset = 0,
453c4990
PU		 1682 .version = MCASP_VERSION_4,
1683};
1684
3e3b8c34
HG		 1685static const struct of_device_id mcasp_dt_ids[] = {
1686 {
1687 .compatible = "ti,dm646x-mcasp-audio",
256ba181 1688 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 1689 },
1690 {
1691 .compatible = "ti,da830-mcasp-audio",
256ba181 1692 .data = &da830_mcasp_pdata,
3e3b8c34 1693 },
e5ec69da 1694 {
3af9e031 1695 .compatible = "ti,am33xx-mcasp-audio",
b14899da 1696 .data = &am33xx_mcasp_pdata,
e5ec69da 1697 },
453c4990
PU		 1698 {
1699 .compatible = "ti,dra7-mcasp-audio",
1700 .data = &dra7_mcasp_pdata,
1701 },
3e3b8c34
HG		 1702 { /* sentinel */ }
1703};
1704MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1705
ae726e93
PU		 1706static int mcasp_reparent_fck(struct platform_device *pdev)
1707{
1708 struct device_node *node = pdev->dev.of_node;
1709 struct clk *gfclk, *parent_clk;
1710 const char *parent_name;
1711 int ret;
1712
1713 if (!node)
1714 return 0;
1715
1716 parent_name = of_get_property(node, "fck_parent", NULL);
1717 if (!parent_name)
1718 return 0;
1719
c670254f
PU		 1720 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1721
ae726e93
PU		 1722 gfclk = clk_get(&pdev->dev, "fck");
1723 if (IS_ERR(gfclk)) {
1724 dev_err(&pdev->dev, "failed to get fck\n");
1725 return PTR_ERR(gfclk);
1726 }
1727
1728 parent_clk = clk_get(NULL, parent_name);
1729 if (IS_ERR(parent_clk)) {
1730 dev_err(&pdev->dev, "failed to get parent clock\n");
1731 ret = PTR_ERR(parent_clk);
1732 goto err1;
1733 }
1734
1735 ret = clk_set_parent(gfclk, parent_clk);
1736 if (ret) {
1737 dev_err(&pdev->dev, "failed to reparent fck\n");
1738 goto err2;
1739 }
1740
1741err2:
1742 clk_put(parent_clk);
1743err1:
1744 clk_put(gfclk);
1745 return ret;
1746}
1747
d1debafc 1748static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 1749 struct platform_device *pdev)
1750{
1751 struct device_node *np = pdev->dev.of_node;
d1debafc 1752 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 1753 const struct of_device_id *match =
ea421eb1 1754 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 1755 struct of_phandle_args dma_spec;
3e3b8c34
HG		 1756
1757 const u32 *of_serial_dir32;
3e3b8c34
HG		 1758 u32 val;
1759 int i, ret = 0;
1760
1761 if (pdev->dev.platform_data) {
1762 pdata = pdev->dev.platform_data;
bc184549 1763 pdata->dismod = DISMOD_LOW;
3e3b8c34
HG		 1764 return pdata;
1765 } else if (match) {
272ee030
PU		 1766 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1767 GFP_KERNEL);
f4d95de4
CIK		 1768 if (!pdata)
1769 return NULL;
3e3b8c34
HG		 1770 } else {
1771 /* control shouldn't reach here. something is wrong */
1772 ret = -EINVAL;
1773 goto nodata;
1774 }
1775
3e3b8c34
HG		 1776 ret = of_property_read_u32(np, "op-mode", &val);
1777 if (ret >= 0)
1778 pdata->op_mode = val;
1779
1780 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1781 if (ret >= 0) {
1782 if (val < 2 || val > 32) {
1783 dev_err(&pdev->dev,
1784 "tdm-slots must be in rage [2-32]\n");
1785 ret = -EINVAL;
1786 goto nodata;
1787 }
1788
3e3b8c34 1789 pdata->tdm_slots = val;
2952b27e 1790 }
3e3b8c34 1791
3e3b8c34
HG		 1792 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1793 val /= sizeof(u32);
3e3b8c34 1794 if (of_serial_dir32) {
1427e660
PU		 1795 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1796 (sizeof(*of_serial_dir) * val),
1797 GFP_KERNEL);
3e3b8c34
HG		 1798 if (!of_serial_dir) {
1799 ret = -ENOMEM;
1800 goto nodata;
1801 }
1802
1427e660 1803 for (i = 0; i < val; i++)
3e3b8c34
HG		 1804 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1805
1427e660 1806 pdata->num_serializer = val;
3e3b8c34
HG		 1807 pdata->serial_dir = of_serial_dir;
1808 }
1809
4023fe6f
JS		 1810 ret = of_property_match_string(np, "dma-names", "tx");
1811 if (ret < 0)
1812 goto nodata;
1813
1814 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1815 &dma_spec);
1816 if (ret < 0)
1817 goto nodata;
1818
1819 pdata->tx_dma_channel = dma_spec.args[0];
1820
caa1d794
PU		 1821 /* RX is not valid in DIT mode */
1822 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1823 ret = of_property_match_string(np, "dma-names", "rx");
1824 if (ret < 0)
1825 goto nodata;
4023fe6f 1826
caa1d794
PU		 1827 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1828 &dma_spec);
1829 if (ret < 0)
1830 goto nodata;
4023fe6f 1831
caa1d794
PU		 1832 pdata->rx_dma_channel = dma_spec.args[0];
1833 }
4023fe6f 1834
3e3b8c34
HG		 1835 ret = of_property_read_u32(np, "tx-num-evt", &val);
1836 if (ret >= 0)
1837 pdata->txnumevt = val;
1838
1839 ret = of_property_read_u32(np, "rx-num-evt", &val);
1840 if (ret >= 0)
1841 pdata->rxnumevt = val;
1842
1843 ret = of_property_read_u32(np, "sram-size-playback", &val);
1844 if (ret >= 0)
1845 pdata->sram_size_playback = val;
1846
1847 ret = of_property_read_u32(np, "sram-size-capture", &val);
1848 if (ret >= 0)
1849 pdata->sram_size_capture = val;
1850
bc184549
PU		 1851 ret = of_property_read_u32(np, "dismod", &val);
1852 if (ret >= 0) {
1853 if (val == 0 || val == 2 || val == 3) {
1854 pdata->dismod = DISMOD_VAL(val);
1855 } else {
1856 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1857 pdata->dismod = DISMOD_LOW;
1858 }
1859 } else {
1860 pdata->dismod = DISMOD_LOW;
1861 }
1862
3e3b8c34
HG		 1863 return pdata;
1864
1865nodata:
1866 if (ret < 0) {
1867 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1868 ret);
1869 pdata = NULL;
1870 }
1871 return pdata;
1872}
1873
9fbd58cf
JS		 1874enum {
1875 PCM_EDMA,
1876 PCM_SDMA,
fb0c3c6e 1877 PCM_UDMA,
9fbd58cf
JS		 1878};
1879static const char *sdma_prefix = "ti,omap";
1880
1881static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1882{
1883 struct dma_chan *chan;
1884 const char *tmp;
1885 int ret = PCM_EDMA;
1886
1887 if (!mcasp->dev->of_node)
1888 return PCM_EDMA;
1889
1890 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
f0c97131 1891 chan = dma_request_chan(mcasp->dev, tmp);
9fbd58cf
JS		 1892 if (IS_ERR(chan)) {
1893 if (PTR_ERR(chan) != -EPROBE_DEFER)
1894 dev_err(mcasp->dev,
1895 "Can't verify DMA configuration (%ld)\n",
1896 PTR_ERR(chan));
1897 return PTR_ERR(chan);
1898 }
befff4fb
TI		 1899 if (WARN_ON(!chan->device || !chan->device->dev))
1900 return -EINVAL;
9fbd58cf
JS		 1901
1902 if (chan->device->dev->of_node)
1903 ret = of_property_read_string(chan->device->dev->of_node,
1904 "compatible", &tmp);
1905 else
1906 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1907
1908 dma_release_channel(chan);
1909 if (ret)
1910 return ret;
1911
1912 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1913 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1914 return PCM_SDMA;
fb0c3c6e
PU		 1915 else if (strstr(tmp, "udmap"))
1916 return PCM_UDMA;
9fbd58cf
JS		 1917
1918 return PCM_EDMA;
1919}
1920
9ac0013c
PU		 1921static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1922{
1923 int i;
1924 u32 offset = 0;
1925
1926 if (pdata->version != MCASP_VERSION_4)
1927 return pdata->tx_dma_offset;
1928
1929 for (i = 0; i < pdata->num_serializer; i++) {
1930 if (pdata->serial_dir[i] == TX_MODE) {
1931 if (!offset) {
1932 offset = DAVINCI_MCASP_TXBUF_REG(i);
1933 } else {
1934 pr_err("%s: Only one serializer allowed!\n",
1935 __func__);
1936 break;
1937 }
1938 }
1939 }
1940
1941 return offset;
1942}
1943
1944static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1945{
1946 int i;
1947 u32 offset = 0;
1948
1949 if (pdata->version != MCASP_VERSION_4)
1950 return pdata->rx_dma_offset;
1951
1952 for (i = 0; i < pdata->num_serializer; i++) {
1953 if (pdata->serial_dir[i] == RX_MODE) {
1954 if (!offset) {
1955 offset = DAVINCI_MCASP_RXBUF_REG(i);
1956 } else {
1957 pr_err("%s: Only one serializer allowed!\n",
1958 __func__);
1959 break;
1960 }
1961 }
1962 }
1963
1964 return offset;
1965}
1966
540f1ba7
PU		 1967#ifdef CONFIG_GPIOLIB
1968static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1969{
1970 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1971
1972 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1973 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1974 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1975 return -EBUSY;
1976 }
1977
1978 /* Do not change the PIN yet */
1979
1980 return pm_runtime_get_sync(mcasp->dev);
1981}
1982
1983static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1984{
1985 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1986
1987 /* Set the direction to input */
1988 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1989
1990 /* Set the pin as McASP pin */
1991 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1992
1993 pm_runtime_put_sync(mcasp->dev);
1994}
1995
1996static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1997 unsigned offset, int value)
1998{
1999 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2000 u32 val;
2001
2002 if (value)
2003 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2004 else
2005 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2006
2007 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2008 if (!(val & BIT(offset))) {
2009 /* Set the pin as GPIO pin */
2010 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2011
2012 /* Set the direction to output */
2013 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2014 }
2015
2016 return 0;
2017}
2018
2019static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2020 int value)
2021{
2022 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2023
2024 if (value)
2025 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2026 else
2027 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2028}
2029
2030static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2031 unsigned offset)
2032{
2033 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2034 u32 val;
2035
2036 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2037 if (!(val & BIT(offset))) {
2038 /* Set the direction to input */
2039 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2040
2041 /* Set the pin as GPIO pin */
2042 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2043 }
2044
2045 return 0;
2046}
2047
2048static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2049{
2050 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2051 u32 val;
2052
2053 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2054 if (val & BIT(offset))
2055 return 1;
2056
2057 return 0;
2058}
2059
2060static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2061 unsigned offset)
2062{
2063 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2064 u32 val;
2065
2066 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2067 if (val & BIT(offset))
2068 return 0;
2069
2070 return 1;
2071}
2072
2073static const struct gpio_chip davinci_mcasp_template_chip = {
2074 .owner = THIS_MODULE,
2075 .request = davinci_mcasp_gpio_request,
2076 .free = davinci_mcasp_gpio_free,
2077 .direction_output = davinci_mcasp_gpio_direction_out,
2078 .set = davinci_mcasp_gpio_set,
2079 .direction_input = davinci_mcasp_gpio_direction_in,
2080 .get = davinci_mcasp_gpio_get,
2081 .get_direction = davinci_mcasp_gpio_get_direction,
2082 .base = -1,
2083 .ngpio = 32,
2084};
2085
2086static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2087{
2088 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2089 return 0;
2090
2091 mcasp->gpio_chip = davinci_mcasp_template_chip;
2092 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2093 mcasp->gpio_chip.parent = mcasp->dev;
2094#ifdef CONFIG_OF_GPIO
2095 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2096#endif
2097
2098 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2099}
2100
2101#else /* CONFIG_GPIOLIB */
2102static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2103{
2104 return 0;
2105}
2106#endif /* CONFIG_GPIOLIB */
2107
764958f2
PU		 2108static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2109{
2110 struct device_node *np = mcasp->dev->of_node;
2111 int ret;
2112 u32 val;
2113
2114 if (!np)
2115 return 0;
2116
2117 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2118 if (ret >= 0)
2119 mcasp->auxclk_fs_ratio = val;
2120
2121 return 0;
2122}
2123
b67f4487
C		 2124static int davinci_mcasp_probe(struct platform_device *pdev)
2125{
8de131f2 2126 struct snd_dmaengine_dai_dma_data *dma_data;
508a43fd 2127 struct resource *mem, *res, *dat;
d1debafc 2128 struct davinci_mcasp_pdata *pdata;
70091a3e 2129 struct davinci_mcasp *mcasp;
a7a3324a 2130 char *irq_name;
9759e7ef 2131 int *dma;
a7a3324a 2132 int irq;
96d31e2b 2133 int ret;
b67f4487 2134
3e3b8c34
HG		 2135 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2136 dev_err(&pdev->dev, "No platform data supplied\n");
2137 return -EINVAL;
2138 }
2139
70091a3e 2140 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 2141 GFP_KERNEL);
70091a3e 2142 if (!mcasp)
b67f4487
C		 2143 return -ENOMEM;
2144
3e3b8c34
HG		 2145 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2146 if (!pdata) {
2147 dev_err(&pdev->dev, "no platform data\n");
2148 return -EINVAL;
2149 }
2150
256ba181 2151 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 2152 if (!mem) {
70091a3e 2153 dev_warn(mcasp->dev,
256ba181
JS		 2154 "\"mpu\" mem resource not found, using index 0\n");
2155 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2156 if (!mem) {
2157 dev_err(&pdev->dev, "no mem resource?\n");
2158 return -ENODEV;
2159 }
b67f4487
C		 2160 }
2161
508a43fd
AL		 2162 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2163 if (IS_ERR(mcasp->base))
2164 return PTR_ERR(mcasp->base);
b67f4487 2165
10884347 2166 pm_runtime_enable(&pdev->dev);
b67f4487 2167
70091a3e 2168 mcasp->op_mode = pdata->op_mode;
1a5923da
PU		 2169 /* sanity check for tdm slots parameter */
2170 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2171 if (pdata->tdm_slots < 2) {
2172 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2173 pdata->tdm_slots);
2174 mcasp->tdm_slots = 2;
2175 } else if (pdata->tdm_slots > 32) {
2176 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2177 pdata->tdm_slots);
2178 mcasp->tdm_slots = 32;
2179 } else {
2180 mcasp->tdm_slots = pdata->tdm_slots;
2181 }
2182 }
2183
70091a3e 2184 mcasp->num_serializer = pdata->num_serializer;
61754717 2185#ifdef CONFIG_PM
a86854d0
KC		 2186 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2187 mcasp->num_serializer, sizeof(u32),
f114ce60 2188 GFP_KERNEL);
4243e045
CJ		 2189 if (!mcasp->context.xrsr_regs) {
2190 ret = -ENOMEM;
2191 goto err;
2192 }
f114ce60 2193#endif
70091a3e
PU		 2194 mcasp->serial_dir = pdata->serial_dir;
2195 mcasp->version = pdata->version;
2196 mcasp->txnumevt = pdata->txnumevt;
2197 mcasp->rxnumevt = pdata->rxnumevt;
bc184549 2198 mcasp->dismod = pdata->dismod;
487dce88 2199
70091a3e 2200 mcasp->dev = &pdev->dev;
b67f4487 2201
5a1b8a80
PU		 2202 irq = platform_get_irq_byname(pdev, "common");
2203 if (irq >= 0) {
ab1fffe3 2204 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
5a1b8a80 2205 dev_name(&pdev->dev));
0c8b794c
AY		 2206 if (!irq_name) {
2207 ret = -ENOMEM;
2208 goto err;
2209 }
5a1b8a80
PU		 2210 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2211 davinci_mcasp_common_irq_handler,
8f511ffb
PU		 2212 IRQF_ONESHOT | IRQF_SHARED,
2213 irq_name, mcasp);
5a1b8a80
PU		 2214 if (ret) {
2215 dev_err(&pdev->dev, "common IRQ request failed\n");
2216 goto err;
2217 }
2218
2219 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2220 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2221 }
2222
a7a3324a
MLC		 2223 irq = platform_get_irq_byname(pdev, "rx");
2224 if (irq >= 0) {
ab1fffe3 2225 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
a7a3324a 2226 dev_name(&pdev->dev));
0c8b794c
AY		 2227 if (!irq_name) {
2228 ret = -ENOMEM;
2229 goto err;
2230 }
a7a3324a
MLC		 2231 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2232 davinci_mcasp_rx_irq_handler,
2233 IRQF_ONESHOT, irq_name, mcasp);
2234 if (ret) {
2235 dev_err(&pdev->dev, "RX IRQ request failed\n");
2236 goto err;
2237 }
2238
2239 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2240 }
2241
2242 irq = platform_get_irq_byname(pdev, "tx");
2243 if (irq >= 0) {
ab1fffe3 2244 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
a7a3324a 2245 dev_name(&pdev->dev));
0c8b794c
AY		 2246 if (!irq_name) {
2247 ret = -ENOMEM;
2248 goto err;
2249 }
a7a3324a
MLC		 2250 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2251 davinci_mcasp_tx_irq_handler,
2252 IRQF_ONESHOT, irq_name, mcasp);
2253 if (ret) {
2254 dev_err(&pdev->dev, "TX IRQ request failed\n");
2255 goto err;
2256 }
2257
2258 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2259 }
2260
256ba181 2261 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 2262 if (dat)
2263 mcasp->dat_port = true;
256ba181 2264
8de131f2 2265 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
cbc7956c 2266 if (dat)
9759e7ef 2267 dma_data->addr = dat->start;
cbc7956c 2268 else
9ac0013c 2269 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
453c4990 2270
9759e7ef 2271 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
b67f4487 2272 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 2273 if (res)
9759e7ef 2274 *dma = res->start;
4023fe6f 2275 else
9759e7ef 2276 *dma = pdata->tx_dma_channel;
92e2a6f6 2277
8de131f2
PU		 2278 /* dmaengine filter data for DT and non-DT boot */
2279 if (pdev->dev.of_node)
2280 dma_data->filter_data = "tx";
2281 else
9759e7ef 2282 dma_data->filter_data = dma;
8de131f2 2283
caa1d794
PU		 2284 /* RX is not valid in DIT mode */
2285 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
caa1d794 2286 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
caa1d794 2287 if (dat)
9759e7ef 2288 dma_data->addr = dat->start;
caa1d794 2289 else
9ac0013c
PU		 2290 dma_data->addr =
2291 mem->start + davinci_mcasp_rxdma_offset(pdata);
caa1d794 2292
9759e7ef 2293 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
caa1d794
PU		 2294 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2295 if (res)
9759e7ef 2296 *dma = res->start;
caa1d794 2297 else
9759e7ef 2298 *dma = pdata->rx_dma_channel;
caa1d794
PU		 2299
2300 /* dmaengine filter data for DT and non-DT boot */
2301 if (pdev->dev.of_node)
2302 dma_data->filter_data = "rx";
2303 else
9759e7ef 2304 dma_data->filter_data = dma;
caa1d794 2305 }
453c4990 2306
cbc7956c
PU		 2307 if (mcasp->version < MCASP_VERSION_3) {
2308 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 2309 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 2310 mcasp->dat_port = true;
2311 } else {
2312 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2313 }
b67f4487 2314
dd55ff83
JS		 2315 /* Allocate memory for long enough list for all possible
2316 * scenarios. Maximum number tdm slots is 32 and there cannot
2317 * be more serializers than given in the configuration. The
2318 * serializer directions could be taken into account, but it
2319 * would make code much more complex and save only couple of
2320 * bytes.
2321 */
2322 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
a86854d0
KC		 2323 devm_kcalloc(mcasp->dev,
2324 32 + mcasp->num_serializer - 1,
2325 sizeof(unsigned int),
dd55ff83
JS		 2326 GFP_KERNEL);
2327
2328 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
a86854d0
KC		 2329 devm_kcalloc(mcasp->dev,
2330 32 + mcasp->num_serializer - 1,
2331 sizeof(unsigned int),
dd55ff83
JS		 2332 GFP_KERNEL);
2333
2334 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1b8b68b0
CJ		 2335 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2336 ret = -ENOMEM;
2337 goto err;
2338 }
dd55ff83
JS		 2339
2340 ret = davinci_mcasp_set_ch_constraints(mcasp);
5935a056
JS		 2341 if (ret)
2342 goto err;
2343
70091a3e 2344 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 2345
2346 mcasp_reparent_fck(pdev);
2347
540f1ba7
PU		 2348 /* All PINS as McASP */
2349 pm_runtime_get_sync(mcasp->dev);
2350 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2351 pm_runtime_put(mcasp->dev);
2352
2353 ret = davinci_mcasp_init_gpiochip(mcasp);
2354 if (ret)
2355 goto err;
2356
764958f2
PU		 2357 ret = davinci_mcasp_get_dt_params(mcasp);
2358 if (ret)
2359 return -EINVAL;
2360
b6bb3709
PU		 2361 ret = devm_snd_soc_register_component(&pdev->dev,
2362 &davinci_mcasp_component,
2363 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 2364
2365 if (ret != 0)
b6bb3709 2366 goto err;
f08095a4 2367
9fbd58cf
JS		 2368 ret = davinci_mcasp_get_dma_type(mcasp);
2369 switch (ret) {
2370 case PCM_EDMA:
f3f9cfa8 2371 ret = edma_pcm_platform_register(&pdev->dev);
9fbd58cf
JS		 2372 break;
2373 case PCM_SDMA:
3e802e90 2374 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
9fbd58cf 2375 break;
fb0c3c6e
PU		 2376 case PCM_UDMA:
2377 ret = udma_pcm_platform_register(&pdev->dev);
2378 break;
d5c6c59a 2379 default:
9fbd58cf
JS		 2380 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2381 case -EPROBE_DEFER:
2382 goto err;
d5c6c59a
PU		 2383 break;
2384 }
2385
2386 if (ret) {
2387 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
b6bb3709 2388 goto err;
f08095a4
HG		 2389 }
2390
b67f4487
C		 2391 return 0;
2392
b6bb3709 2393err:
10884347 2394 pm_runtime_disable(&pdev->dev);
b67f4487
C		 2395 return ret;
2396}
2397
2398static int davinci_mcasp_remove(struct platform_device *pdev)
2399{
10884347 2400 pm_runtime_disable(&pdev->dev);
b67f4487 2401
b67f4487
C		 2402 return 0;
2403}
2404
61754717
PU		 2405#ifdef CONFIG_PM
2406static int davinci_mcasp_runtime_suspend(struct device *dev)
2407{
2408 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2409 struct davinci_mcasp_context *context = &mcasp->context;
2410 u32 reg;
2411 int i;
2412
2413 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2414 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2415
2416 if (mcasp->txnumevt) {
2417 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2418 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2419 }
2420 if (mcasp->rxnumevt) {
2421 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2422 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2423 }
2424
2425 for (i = 0; i < mcasp->num_serializer; i++)
2426 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2427 DAVINCI_MCASP_XRSRCTL_REG(i));
2428
2429 return 0;
2430}
2431
2432static int davinci_mcasp_runtime_resume(struct device *dev)
2433{
2434 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2435 struct davinci_mcasp_context *context = &mcasp->context;
2436 u32 reg;
2437 int i;
2438
2439 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2440 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2441
2442 if (mcasp->txnumevt) {
2443 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2444 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2445 }
2446 if (mcasp->rxnumevt) {
2447 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2448 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2449 }
2450
2451 for (i = 0; i < mcasp->num_serializer; i++)
2452 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2453 context->xrsr_regs[i]);
2454
2455 return 0;
2456}
2457
2458#endif
2459
2460static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2461 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2462 davinci_mcasp_runtime_resume,
2463 NULL)
2464};
2465
b67f4487
C		 2466static struct platform_driver davinci_mcasp_driver = {
2467 .probe = davinci_mcasp_probe,
2468 .remove = davinci_mcasp_remove,
2469 .driver = {
2470 .name = "davinci-mcasp",
61754717 2471 .pm = &davinci_mcasp_pm_ops,
ea421eb1 2472 .of_match_table = mcasp_dt_ids,
b67f4487
C		 2473 },
2474};
2475
f9b8a514 2476module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 2477
2478MODULE_AUTHOR("Steve Chen");
2479MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2480MODULE_LICENSE("GPL");
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