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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
fd26f947 PU |
2 | /* |
3 | * omap-dmic.h -- OMAP Digital Microphone Controller | |
fd26f947 PU |
4 | */ |
5 | ||
6 | #ifndef _OMAP_DMIC_H | |
7 | #define _OMAP_DMIC_H | |
8 | ||
9 | #define OMAP_DMIC_REVISION_REG 0x00 | |
10 | #define OMAP_DMIC_SYSCONFIG_REG 0x10 | |
11 | #define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24 | |
12 | #define OMAP_DMIC_IRQSTATUS_REG 0x28 | |
13 | #define OMAP_DMIC_IRQENABLE_SET_REG 0x2C | |
14 | #define OMAP_DMIC_IRQENABLE_CLR_REG 0x30 | |
15 | #define OMAP_DMIC_IRQWAKE_EN_REG 0x34 | |
16 | #define OMAP_DMIC_DMAENABLE_SET_REG 0x38 | |
17 | #define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C | |
18 | #define OMAP_DMIC_DMAWAKEEN_REG 0x40 | |
19 | #define OMAP_DMIC_CTRL_REG 0x44 | |
20 | #define OMAP_DMIC_DATA_REG 0x48 | |
21 | #define OMAP_DMIC_FIFO_CTRL_REG 0x4C | |
22 | #define OMAP_DMIC_FIFO_DMIC1R_DATA_REG 0x50 | |
23 | #define OMAP_DMIC_FIFO_DMIC1L_DATA_REG 0x54 | |
24 | #define OMAP_DMIC_FIFO_DMIC2R_DATA_REG 0x58 | |
25 | #define OMAP_DMIC_FIFO_DMIC2L_DATA_REG 0x5C | |
26 | #define OMAP_DMIC_FIFO_DMIC3R_DATA_REG 0x60 | |
27 | #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64 | |
28 | ||
29 | /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */ | |
30 | #define OMAP_DMIC_IRQ (1 << 0) | |
31 | #define OMAP_DMIC_IRQ_FULL (1 << 1) | |
32 | #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2) | |
33 | #define OMAP_DMIC_IRQ_EMPTY (1 << 3) | |
34 | #define OMAP_DMIC_IRQ_MASK 0x07 | |
35 | ||
36 | /* DMIC_DMAENABLE bit fields */ | |
37 | #define OMAP_DMIC_DMA_ENABLE 0x1 | |
38 | ||
39 | /* DMIC_CTRL bit fields */ | |
40 | #define OMAP_DMIC_UP1_ENABLE (1 << 0) | |
41 | #define OMAP_DMIC_UP2_ENABLE (1 << 1) | |
42 | #define OMAP_DMIC_UP3_ENABLE (1 << 2) | |
43 | #define OMAP_DMIC_UP_ENABLE_MASK 0x7 | |
44 | #define OMAP_DMIC_FORMAT (1 << 3) | |
45 | #define OMAP_DMIC_POLAR1 (1 << 4) | |
46 | #define OMAP_DMIC_POLAR2 (1 << 5) | |
47 | #define OMAP_DMIC_POLAR3 (1 << 6) | |
48 | #define OMAP_DMIC_POLAR_MASK (0x7 << 4) | |
49 | #define OMAP_DMIC_CLK_DIV(x) (((x) & 0x7) << 7) | |
50 | #define OMAP_DMIC_CLK_DIV_MASK (0x7 << 7) | |
51 | #define OMAP_DMIC_RESET (1 << 10) | |
52 | ||
53 | #define OMAP_DMICOUTFORMAT_LJUST (0 << 3) | |
54 | #define OMAP_DMICOUTFORMAT_RJUST (1 << 3) | |
55 | ||
56 | /* DMIC_FIFO_CTRL bit fields */ | |
57 | #define OMAP_DMIC_THRES_MAX 0xF | |
58 | ||
59 | enum omap_dmic_clk { | |
60 | OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */ | |
61 | OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */ | |
62 | OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */ | |
63 | OMAP_DMIC_ABE_DMIC_CLK, /* abe_dmic_clk */ | |
64 | }; | |
65 | ||
66 | #endif |