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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Driver for AMD7930 sound chips found on Sparcs. | |
dc8aa2e9 | 4 | * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net> |
1da177e4 LT |
5 | * |
6 | * Based entirely upon drivers/sbus/audio/amd7930.c which is: | |
7 | * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu) | |
8 | * | |
9 | * --- Notes from Thomas's original driver --- | |
10 | * This is the lowlevel driver for the AMD7930 audio chip found on all | |
11 | * sun4c machines and some sun4m machines. | |
12 | * | |
13 | * The amd7930 is actually an ISDN chip which has a very simple | |
14 | * integrated audio encoder/decoder. When Sun decided on what chip to | |
15 | * use for audio, they had the brilliant idea of using the amd7930 and | |
16 | * only connecting the audio encoder/decoder pins. | |
17 | * | |
18 | * Thanks to the AMD engineer who was able to get us the AMD79C30 | |
19 | * databook which has all the programming information and gain tables. | |
20 | * | |
21 | * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the | |
22 | * SparcStation 1+. The chip provides microphone and speaker interfaces | |
23 | * which provide mono-channel audio at 8K samples per second via either | |
24 | * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an | |
25 | * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface, | |
26 | * which performs basic D channel LAPD processing and provides raw | |
27 | * B channel data. The digital audio channel, the two ISDN B channels, | |
28 | * and two 64 Kbps channels to the microprocessor are all interconnected | |
29 | * via a multiplexer. | |
30 | * --- End of notes from Thoamas's original driver --- | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/moduleparam.h> | |
dc8aa2e9 DM |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
6cbbfe1c | 41 | #include <linux/io.h> |
1da177e4 | 42 | |
1da177e4 LT |
43 | #include <sound/core.h> |
44 | #include <sound/pcm.h> | |
45 | #include <sound/info.h> | |
46 | #include <sound/control.h> | |
47 | #include <sound/initval.h> | |
48 | ||
1da177e4 | 49 | #include <asm/irq.h> |
69b5c4f1 | 50 | #include <asm/prom.h> |
1da177e4 LT |
51 | |
52 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
53 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 54 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
1da177e4 LT |
55 | |
56 | module_param_array(index, int, NULL, 0444); | |
57 | MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard."); | |
58 | module_param_array(id, charp, NULL, 0444); | |
59 | MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard."); | |
60 | module_param_array(enable, bool, NULL, 0444); | |
61 | MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard."); | |
62 | MODULE_AUTHOR("Thomas K. Dyas and David S. Miller"); | |
63 | MODULE_DESCRIPTION("Sun AMD7930"); | |
64 | MODULE_LICENSE("GPL"); | |
65 | MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}"); | |
66 | ||
67 | /* Device register layout. */ | |
68 | ||
69 | /* Register interface presented to the CPU by the amd7930. */ | |
70 | #define AMD7930_CR 0x00UL /* Command Register (W) */ | |
71 | #define AMD7930_IR AMD7930_CR /* Interrupt Register (R) */ | |
72 | #define AMD7930_DR 0x01UL /* Data Register (R/W) */ | |
73 | #define AMD7930_DSR1 0x02UL /* D-channel Status Register 1 (R) */ | |
74 | #define AMD7930_DER 0x03UL /* D-channel Error Register (R) */ | |
75 | #define AMD7930_DCTB 0x04UL /* D-channel Transmit Buffer (W) */ | |
76 | #define AMD7930_DCRB AMD7930_DCTB /* D-channel Receive Buffer (R) */ | |
77 | #define AMD7930_BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */ | |
78 | #define AMD7930_BBRB AMD7930_BBTB /* Bb-channel Receive Buffer (R) */ | |
79 | #define AMD7930_BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */ | |
80 | #define AMD7930_BCRB AMD7930_BCTB /* Bc-channel Receive Buffer (R) */ | |
81 | #define AMD7930_DSR2 0x07UL /* D-channel Status Register 2 (R) */ | |
82 | ||
83 | /* Indirect registers in the Main Audio Processor. */ | |
84 | struct amd7930_map { | |
85 | __u16 x[8]; | |
86 | __u16 r[8]; | |
87 | __u16 gx; | |
88 | __u16 gr; | |
89 | __u16 ger; | |
90 | __u16 stgr; | |
91 | __u16 ftgr; | |
92 | __u16 atgr; | |
93 | __u8 mmr1; | |
94 | __u8 mmr2; | |
95 | }; | |
96 | ||
97 | /* After an amd7930 interrupt, reading the Interrupt Register (ir) | |
98 | * clears the interrupt and returns a bitmask indicating which | |
99 | * interrupt source(s) require service. | |
100 | */ | |
101 | ||
102 | #define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */ | |
103 | #define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */ | |
104 | #define AMR_IR_DSRI 0x04 /* D-channel packet status */ | |
105 | #define AMR_IR_DERI 0x08 /* D-channel error */ | |
106 | #define AMR_IR_BBUF 0x10 /* B-channel data xfer */ | |
107 | #define AMR_IR_LSRI 0x20 /* LIU status */ | |
108 | #define AMR_IR_DSR2I 0x40 /* D-channel buffer status */ | |
109 | #define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */ | |
110 | ||
111 | /* The amd7930 has "indirect registers" which are accessed by writing | |
112 | * the register number into the Command Register and then reading or | |
113 | * writing values from the Data Register as appropriate. We define the | |
114 | * AMR_* macros to be the indirect register numbers and AM_* macros to | |
115 | * be bits in whatever register is referred to. | |
116 | */ | |
117 | ||
118 | /* Initialization */ | |
119 | #define AMR_INIT 0x21 | |
120 | #define AM_INIT_ACTIVE 0x01 | |
121 | #define AM_INIT_DATAONLY 0x02 | |
122 | #define AM_INIT_POWERDOWN 0x03 | |
123 | #define AM_INIT_DISABLE_INTS 0x04 | |
124 | #define AMR_INIT2 0x20 | |
125 | #define AM_INIT2_ENABLE_POWERDOWN 0x20 | |
126 | #define AM_INIT2_ENABLE_MULTIFRAME 0x10 | |
127 | ||
128 | /* Line Interface Unit */ | |
129 | #define AMR_LIU_LSR 0xA1 | |
130 | #define AM_LIU_LSR_STATE 0x07 | |
131 | #define AM_LIU_LSR_F3 0x08 | |
132 | #define AM_LIU_LSR_F7 0x10 | |
133 | #define AM_LIU_LSR_F8 0x20 | |
134 | #define AM_LIU_LSR_HSW 0x40 | |
135 | #define AM_LIU_LSR_HSW_CHG 0x80 | |
136 | #define AMR_LIU_LPR 0xA2 | |
137 | #define AMR_LIU_LMR1 0xA3 | |
138 | #define AM_LIU_LMR1_B1_ENABL 0x01 | |
139 | #define AM_LIU_LMR1_B2_ENABL 0x02 | |
140 | #define AM_LIU_LMR1_F_DISABL 0x04 | |
141 | #define AM_LIU_LMR1_FA_DISABL 0x08 | |
142 | #define AM_LIU_LMR1_REQ_ACTIV 0x10 | |
143 | #define AM_LIU_LMR1_F8_F3 0x20 | |
144 | #define AM_LIU_LMR1_LIU_ENABL 0x40 | |
145 | #define AMR_LIU_LMR2 0xA4 | |
146 | #define AM_LIU_LMR2_DECHO 0x01 | |
147 | #define AM_LIU_LMR2_DLOOP 0x02 | |
148 | #define AM_LIU_LMR2_DBACKOFF 0x04 | |
149 | #define AM_LIU_LMR2_EN_F3_INT 0x08 | |
150 | #define AM_LIU_LMR2_EN_F8_INT 0x10 | |
151 | #define AM_LIU_LMR2_EN_HSW_INT 0x20 | |
152 | #define AM_LIU_LMR2_EN_F7_INT 0x40 | |
153 | #define AMR_LIU_2_4 0xA5 | |
154 | #define AMR_LIU_MF 0xA6 | |
155 | #define AMR_LIU_MFSB 0xA7 | |
156 | #define AMR_LIU_MFQB 0xA8 | |
157 | ||
158 | /* Multiplexor */ | |
159 | #define AMR_MUX_MCR1 0x41 | |
160 | #define AMR_MUX_MCR2 0x42 | |
161 | #define AMR_MUX_MCR3 0x43 | |
162 | #define AM_MUX_CHANNEL_B1 0x01 | |
163 | #define AM_MUX_CHANNEL_B2 0x02 | |
164 | #define AM_MUX_CHANNEL_Ba 0x03 | |
165 | #define AM_MUX_CHANNEL_Bb 0x04 | |
166 | #define AM_MUX_CHANNEL_Bc 0x05 | |
167 | #define AM_MUX_CHANNEL_Bd 0x06 | |
168 | #define AM_MUX_CHANNEL_Be 0x07 | |
169 | #define AM_MUX_CHANNEL_Bf 0x08 | |
170 | #define AMR_MUX_MCR4 0x44 | |
171 | #define AM_MUX_MCR4_ENABLE_INTS 0x08 | |
172 | #define AM_MUX_MCR4_REVERSE_Bb 0x10 | |
173 | #define AM_MUX_MCR4_REVERSE_Bc 0x20 | |
174 | #define AMR_MUX_1_4 0x45 | |
175 | ||
176 | /* Main Audio Processor */ | |
177 | #define AMR_MAP_X 0x61 | |
178 | #define AMR_MAP_R 0x62 | |
179 | #define AMR_MAP_GX 0x63 | |
180 | #define AMR_MAP_GR 0x64 | |
181 | #define AMR_MAP_GER 0x65 | |
182 | #define AMR_MAP_STGR 0x66 | |
183 | #define AMR_MAP_FTGR_1_2 0x67 | |
184 | #define AMR_MAP_ATGR_1_2 0x68 | |
185 | #define AMR_MAP_MMR1 0x69 | |
186 | #define AM_MAP_MMR1_ALAW 0x01 | |
187 | #define AM_MAP_MMR1_GX 0x02 | |
188 | #define AM_MAP_MMR1_GR 0x04 | |
189 | #define AM_MAP_MMR1_GER 0x08 | |
190 | #define AM_MAP_MMR1_X 0x10 | |
191 | #define AM_MAP_MMR1_R 0x20 | |
192 | #define AM_MAP_MMR1_STG 0x40 | |
193 | #define AM_MAP_MMR1_LOOPBACK 0x80 | |
194 | #define AMR_MAP_MMR2 0x6A | |
195 | #define AM_MAP_MMR2_AINB 0x01 | |
196 | #define AM_MAP_MMR2_LS 0x02 | |
197 | #define AM_MAP_MMR2_ENABLE_DTMF 0x04 | |
198 | #define AM_MAP_MMR2_ENABLE_TONEGEN 0x08 | |
199 | #define AM_MAP_MMR2_ENABLE_TONERING 0x10 | |
200 | #define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20 | |
201 | #define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40 | |
202 | #define AMR_MAP_1_10 0x6B | |
203 | #define AMR_MAP_MMR3 0x6C | |
204 | #define AMR_MAP_STRA 0x6D | |
205 | #define AMR_MAP_STRF 0x6E | |
206 | #define AMR_MAP_PEAKX 0x70 | |
207 | #define AMR_MAP_PEAKR 0x71 | |
208 | #define AMR_MAP_15_16 0x72 | |
209 | ||
210 | /* Data Link Controller */ | |
211 | #define AMR_DLC_FRAR_1_2_3 0x81 | |
212 | #define AMR_DLC_SRAR_1_2_3 0x82 | |
213 | #define AMR_DLC_TAR 0x83 | |
214 | #define AMR_DLC_DRLR 0x84 | |
215 | #define AMR_DLC_DTCR 0x85 | |
216 | #define AMR_DLC_DMR1 0x86 | |
217 | #define AMR_DLC_DMR1_DTTHRSH_INT 0x01 | |
218 | #define AMR_DLC_DMR1_DRTHRSH_INT 0x02 | |
219 | #define AMR_DLC_DMR1_TAR_ENABL 0x04 | |
220 | #define AMR_DLC_DMR1_EORP_INT 0x08 | |
221 | #define AMR_DLC_DMR1_EN_ADDR1 0x10 | |
222 | #define AMR_DLC_DMR1_EN_ADDR2 0x20 | |
223 | #define AMR_DLC_DMR1_EN_ADDR3 0x40 | |
224 | #define AMR_DLC_DMR1_EN_ADDR4 0x80 | |
225 | #define AMR_DLC_DMR1_EN_ADDRS 0xf0 | |
226 | #define AMR_DLC_DMR2 0x87 | |
227 | #define AMR_DLC_DMR2_RABRT_INT 0x01 | |
228 | #define AMR_DLC_DMR2_RESID_INT 0x02 | |
229 | #define AMR_DLC_DMR2_COLL_INT 0x04 | |
230 | #define AMR_DLC_DMR2_FCS_INT 0x08 | |
231 | #define AMR_DLC_DMR2_OVFL_INT 0x10 | |
232 | #define AMR_DLC_DMR2_UNFL_INT 0x20 | |
233 | #define AMR_DLC_DMR2_OVRN_INT 0x40 | |
234 | #define AMR_DLC_DMR2_UNRN_INT 0x80 | |
235 | #define AMR_DLC_1_7 0x88 | |
236 | #define AMR_DLC_DRCR 0x89 | |
237 | #define AMR_DLC_RNGR1 0x8A | |
238 | #define AMR_DLC_RNGR2 0x8B | |
239 | #define AMR_DLC_FRAR4 0x8C | |
240 | #define AMR_DLC_SRAR4 0x8D | |
241 | #define AMR_DLC_DMR3 0x8E | |
242 | #define AMR_DLC_DMR3_VA_INT 0x01 | |
243 | #define AMR_DLC_DMR3_EOTP_INT 0x02 | |
244 | #define AMR_DLC_DMR3_LBRP_INT 0x04 | |
245 | #define AMR_DLC_DMR3_RBA_INT 0x08 | |
246 | #define AMR_DLC_DMR3_LBT_INT 0x10 | |
247 | #define AMR_DLC_DMR3_TBE_INT 0x20 | |
248 | #define AMR_DLC_DMR3_RPLOST_INT 0x40 | |
249 | #define AMR_DLC_DMR3_KEEP_FCS 0x80 | |
250 | #define AMR_DLC_DMR4 0x8F | |
251 | #define AMR_DLC_DMR4_RCV_1 0x00 | |
252 | #define AMR_DLC_DMR4_RCV_2 0x01 | |
253 | #define AMR_DLC_DMR4_RCV_4 0x02 | |
254 | #define AMR_DLC_DMR4_RCV_8 0x03 | |
255 | #define AMR_DLC_DMR4_RCV_16 0x01 | |
256 | #define AMR_DLC_DMR4_RCV_24 0x02 | |
257 | #define AMR_DLC_DMR4_RCV_30 0x03 | |
258 | #define AMR_DLC_DMR4_XMT_1 0x00 | |
259 | #define AMR_DLC_DMR4_XMT_2 0x04 | |
260 | #define AMR_DLC_DMR4_XMT_4 0x08 | |
261 | #define AMR_DLC_DMR4_XMT_8 0x0c | |
262 | #define AMR_DLC_DMR4_XMT_10 0x08 | |
263 | #define AMR_DLC_DMR4_XMT_14 0x0c | |
264 | #define AMR_DLC_DMR4_IDLE_MARK 0x00 | |
265 | #define AMR_DLC_DMR4_IDLE_FLAG 0x10 | |
266 | #define AMR_DLC_DMR4_ADDR_BOTH 0x00 | |
267 | #define AMR_DLC_DMR4_ADDR_1ST 0x20 | |
268 | #define AMR_DLC_DMR4_ADDR_2ND 0xa0 | |
269 | #define AMR_DLC_DMR4_CR_ENABLE 0x40 | |
270 | #define AMR_DLC_12_15 0x90 | |
271 | #define AMR_DLC_ASR 0x91 | |
272 | #define AMR_DLC_EFCR 0x92 | |
273 | #define AMR_DLC_EFCR_EXTEND_FIFO 0x01 | |
274 | #define AMR_DLC_EFCR_SEC_PKT_INT 0x02 | |
275 | ||
276 | #define AMR_DSR1_VADDR 0x01 | |
277 | #define AMR_DSR1_EORP 0x02 | |
278 | #define AMR_DSR1_PKT_IP 0x04 | |
279 | #define AMR_DSR1_DECHO_ON 0x08 | |
280 | #define AMR_DSR1_DLOOP_ON 0x10 | |
281 | #define AMR_DSR1_DBACK_OFF 0x20 | |
282 | #define AMR_DSR1_EOTP 0x40 | |
283 | #define AMR_DSR1_CXMT_ABRT 0x80 | |
284 | ||
285 | #define AMR_DSR2_LBRP 0x01 | |
286 | #define AMR_DSR2_RBA 0x02 | |
287 | #define AMR_DSR2_RPLOST 0x04 | |
288 | #define AMR_DSR2_LAST_BYTE 0x08 | |
289 | #define AMR_DSR2_TBE 0x10 | |
290 | #define AMR_DSR2_MARK_IDLE 0x20 | |
291 | #define AMR_DSR2_FLAG_IDLE 0x40 | |
292 | #define AMR_DSR2_SECOND_PKT 0x80 | |
293 | ||
294 | #define AMR_DER_RABRT 0x01 | |
295 | #define AMR_DER_RFRAME 0x02 | |
296 | #define AMR_DER_COLLISION 0x04 | |
297 | #define AMR_DER_FCS 0x08 | |
298 | #define AMR_DER_OVFL 0x10 | |
299 | #define AMR_DER_UNFL 0x20 | |
300 | #define AMR_DER_OVRN 0x40 | |
301 | #define AMR_DER_UNRN 0x80 | |
302 | ||
303 | /* Peripheral Port */ | |
304 | #define AMR_PP_PPCR1 0xC0 | |
305 | #define AMR_PP_PPSR 0xC1 | |
306 | #define AMR_PP_PPIER 0xC2 | |
307 | #define AMR_PP_MTDR 0xC3 | |
308 | #define AMR_PP_MRDR 0xC3 | |
309 | #define AMR_PP_CITDR0 0xC4 | |
310 | #define AMR_PP_CIRDR0 0xC4 | |
311 | #define AMR_PP_CITDR1 0xC5 | |
312 | #define AMR_PP_CIRDR1 0xC5 | |
313 | #define AMR_PP_PPCR2 0xC8 | |
314 | #define AMR_PP_PPCR3 0xC9 | |
315 | ||
dcc94db7 | 316 | struct snd_amd7930 { |
1da177e4 LT |
317 | spinlock_t lock; |
318 | void __iomem *regs; | |
319 | u32 flags; | |
320 | #define AMD7930_FLAG_PLAYBACK 0x00000001 | |
321 | #define AMD7930_FLAG_CAPTURE 0x00000002 | |
322 | ||
323 | struct amd7930_map map; | |
324 | ||
dcc94db7 TI |
325 | struct snd_card *card; |
326 | struct snd_pcm *pcm; | |
327 | struct snd_pcm_substream *playback_substream; | |
328 | struct snd_pcm_substream *capture_substream; | |
1da177e4 LT |
329 | |
330 | /* Playback/Capture buffer state. */ | |
331 | unsigned char *p_orig, *p_cur; | |
332 | int p_left; | |
333 | unsigned char *c_orig, *c_cur; | |
334 | int c_left; | |
335 | ||
336 | int rgain; | |
337 | int pgain; | |
338 | int mgain; | |
339 | ||
2dc11581 | 340 | struct platform_device *op; |
1da177e4 | 341 | unsigned int irq; |
1da177e4 | 342 | struct snd_amd7930 *next; |
dcc94db7 | 343 | }; |
1da177e4 | 344 | |
dcc94db7 | 345 | static struct snd_amd7930 *amd7930_list; |
1da177e4 LT |
346 | |
347 | /* Idle the AMD7930 chip. The amd->lock is not held. */ | |
dcc94db7 | 348 | static __inline__ void amd7930_idle(struct snd_amd7930 *amd) |
1da177e4 LT |
349 | { |
350 | unsigned long flags; | |
351 | ||
352 | spin_lock_irqsave(&amd->lock, flags); | |
353 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); | |
354 | sbus_writeb(0, amd->regs + AMD7930_DR); | |
355 | spin_unlock_irqrestore(&amd->lock, flags); | |
356 | } | |
357 | ||
358 | /* Enable chip interrupts. The amd->lock is not held. */ | |
dcc94db7 | 359 | static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd) |
1da177e4 LT |
360 | { |
361 | unsigned long flags; | |
362 | ||
363 | spin_lock_irqsave(&amd->lock, flags); | |
364 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); | |
365 | sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR); | |
366 | spin_unlock_irqrestore(&amd->lock, flags); | |
367 | } | |
368 | ||
369 | /* Disable chip interrupts. The amd->lock is not held. */ | |
dcc94db7 | 370 | static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd) |
1da177e4 LT |
371 | { |
372 | unsigned long flags; | |
373 | ||
374 | spin_lock_irqsave(&amd->lock, flags); | |
375 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); | |
376 | sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR); | |
377 | spin_unlock_irqrestore(&amd->lock, flags); | |
378 | } | |
379 | ||
380 | /* Commit amd7930_map settings to the hardware. | |
381 | * The amd->lock is held and local interrupts are disabled. | |
382 | */ | |
dcc94db7 | 383 | static void __amd7930_write_map(struct snd_amd7930 *amd) |
1da177e4 LT |
384 | { |
385 | struct amd7930_map *map = &amd->map; | |
386 | ||
387 | sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR); | |
388 | sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR); | |
389 | sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR); | |
390 | ||
391 | sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR); | |
392 | sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR); | |
393 | sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR); | |
394 | ||
395 | sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR); | |
396 | sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR); | |
397 | sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR); | |
398 | ||
399 | sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR); | |
400 | sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR); | |
401 | sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR); | |
402 | ||
403 | sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR); | |
404 | sbus_writeb(map->mmr1, amd->regs + AMD7930_DR); | |
405 | ||
406 | sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR); | |
407 | sbus_writeb(map->mmr2, amd->regs + AMD7930_DR); | |
408 | } | |
409 | ||
410 | /* gx, gr & stg gains. this table must contain 256 elements with | |
411 | * the 0th being "infinity" (the magic value 9008). The remaining | |
412 | * elements match sun's gain curve (but with higher resolution): | |
413 | * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps. | |
414 | */ | |
415 | static __const__ __u16 gx_coeff[256] = { | |
416 | 0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33, | |
417 | 0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22, | |
418 | 0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b, | |
419 | 0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb, | |
420 | 0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a, | |
421 | 0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213, | |
422 | 0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231, | |
423 | 0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4, | |
424 | 0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2, | |
425 | 0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa, | |
426 | 0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b, | |
427 | 0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b, | |
428 | 0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd, | |
429 | 0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808, | |
430 | 0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243, | |
431 | 0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224, | |
432 | 0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb, | |
433 | 0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33, | |
434 | 0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32, | |
435 | 0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323, | |
436 | 0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a, | |
437 | 0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23, | |
438 | 0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1, | |
439 | 0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333, | |
440 | 0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227, | |
441 | 0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6, | |
442 | 0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2, | |
443 | 0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba, | |
444 | 0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033, | |
445 | 0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021, | |
446 | 0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012, | |
447 | 0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e, | |
448 | }; | |
449 | ||
450 | static __const__ __u16 ger_coeff[] = { | |
451 | 0x431f, /* 5. dB */ | |
452 | 0x331f, /* 5.5 dB */ | |
453 | 0x40dd, /* 6. dB */ | |
454 | 0x11dd, /* 6.5 dB */ | |
455 | 0x440f, /* 7. dB */ | |
456 | 0x411f, /* 7.5 dB */ | |
457 | 0x311f, /* 8. dB */ | |
458 | 0x5520, /* 8.5 dB */ | |
459 | 0x10dd, /* 9. dB */ | |
460 | 0x4211, /* 9.5 dB */ | |
461 | 0x410f, /* 10. dB */ | |
462 | 0x111f, /* 10.5 dB */ | |
463 | 0x600b, /* 11. dB */ | |
464 | 0x00dd, /* 11.5 dB */ | |
465 | 0x4210, /* 12. dB */ | |
466 | 0x110f, /* 13. dB */ | |
467 | 0x7200, /* 14. dB */ | |
468 | 0x2110, /* 15. dB */ | |
469 | 0x2200, /* 15.9 dB */ | |
470 | 0x000b, /* 16.9 dB */ | |
471 | 0x000f /* 18. dB */ | |
472 | }; | |
473 | ||
474 | /* Update amd7930_map settings and program them into the hardware. | |
475 | * The amd->lock is held and local interrupts are disabled. | |
476 | */ | |
dcc94db7 | 477 | static void __amd7930_update_map(struct snd_amd7930 *amd) |
1da177e4 LT |
478 | { |
479 | struct amd7930_map *map = &amd->map; | |
480 | int level; | |
481 | ||
482 | map->gx = gx_coeff[amd->rgain]; | |
483 | map->stgr = gx_coeff[amd->mgain]; | |
484 | level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8; | |
485 | if (level >= 256) { | |
486 | map->ger = ger_coeff[level - 256]; | |
487 | map->gr = gx_coeff[255]; | |
488 | } else { | |
489 | map->ger = ger_coeff[0]; | |
490 | map->gr = gx_coeff[level]; | |
491 | } | |
492 | __amd7930_write_map(amd); | |
493 | } | |
494 | ||
7d12e780 | 495 | static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id) |
1da177e4 | 496 | { |
dcc94db7 | 497 | struct snd_amd7930 *amd = dev_id; |
1da177e4 LT |
498 | unsigned int elapsed; |
499 | u8 ir; | |
500 | ||
501 | spin_lock(&amd->lock); | |
502 | ||
503 | elapsed = 0; | |
504 | ||
505 | ir = sbus_readb(amd->regs + AMD7930_IR); | |
506 | if (ir & AMR_IR_BBUF) { | |
507 | u8 byte; | |
508 | ||
509 | if (amd->flags & AMD7930_FLAG_PLAYBACK) { | |
510 | if (amd->p_left > 0) { | |
511 | byte = *(amd->p_cur++); | |
512 | amd->p_left--; | |
513 | sbus_writeb(byte, amd->regs + AMD7930_BBTB); | |
514 | if (amd->p_left == 0) | |
515 | elapsed |= AMD7930_FLAG_PLAYBACK; | |
516 | } else | |
517 | sbus_writeb(0, amd->regs + AMD7930_BBTB); | |
518 | } else if (amd->flags & AMD7930_FLAG_CAPTURE) { | |
519 | byte = sbus_readb(amd->regs + AMD7930_BBRB); | |
520 | if (amd->c_left > 0) { | |
521 | *(amd->c_cur++) = byte; | |
522 | amd->c_left--; | |
523 | if (amd->c_left == 0) | |
524 | elapsed |= AMD7930_FLAG_CAPTURE; | |
525 | } | |
526 | } | |
527 | } | |
528 | spin_unlock(&amd->lock); | |
529 | ||
530 | if (elapsed & AMD7930_FLAG_PLAYBACK) | |
531 | snd_pcm_period_elapsed(amd->playback_substream); | |
532 | else | |
533 | snd_pcm_period_elapsed(amd->capture_substream); | |
534 | ||
535 | return IRQ_HANDLED; | |
536 | } | |
537 | ||
dcc94db7 | 538 | static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd) |
1da177e4 LT |
539 | { |
540 | unsigned long flags; | |
541 | int result = 0; | |
542 | ||
543 | spin_lock_irqsave(&amd->lock, flags); | |
544 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
545 | if (!(amd->flags & flag)) { | |
546 | amd->flags |= flag; | |
547 | ||
548 | /* Enable B channel interrupts. */ | |
549 | sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR); | |
550 | sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR); | |
551 | } | |
552 | } else if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
553 | if (amd->flags & flag) { | |
554 | amd->flags &= ~flag; | |
555 | ||
556 | /* Disable B channel interrupts. */ | |
557 | sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR); | |
558 | sbus_writeb(0, amd->regs + AMD7930_DR); | |
559 | } | |
560 | } else { | |
561 | result = -EINVAL; | |
562 | } | |
563 | spin_unlock_irqrestore(&amd->lock, flags); | |
564 | ||
565 | return result; | |
566 | } | |
567 | ||
dcc94db7 | 568 | static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
569 | int cmd) |
570 | { | |
dcc94db7 | 571 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
572 | return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd); |
573 | } | |
574 | ||
dcc94db7 | 575 | static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
576 | int cmd) |
577 | { | |
dcc94db7 | 578 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
579 | return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd); |
580 | } | |
581 | ||
dcc94db7 | 582 | static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 583 | { |
dcc94db7 TI |
584 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
585 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
586 | unsigned int size = snd_pcm_lib_buffer_bytes(substream); |
587 | unsigned long flags; | |
588 | u8 new_mmr1; | |
589 | ||
590 | spin_lock_irqsave(&amd->lock, flags); | |
591 | ||
592 | amd->flags |= AMD7930_FLAG_PLAYBACK; | |
593 | ||
594 | /* Setup the pseudo-dma transfer pointers. */ | |
595 | amd->p_orig = amd->p_cur = runtime->dma_area; | |
596 | amd->p_left = size; | |
597 | ||
598 | /* Put the chip into the correct encoding format. */ | |
599 | new_mmr1 = amd->map.mmr1; | |
600 | if (runtime->format == SNDRV_PCM_FORMAT_A_LAW) | |
601 | new_mmr1 |= AM_MAP_MMR1_ALAW; | |
602 | else | |
603 | new_mmr1 &= ~AM_MAP_MMR1_ALAW; | |
604 | if (new_mmr1 != amd->map.mmr1) { | |
605 | amd->map.mmr1 = new_mmr1; | |
606 | __amd7930_update_map(amd); | |
607 | } | |
608 | ||
609 | spin_unlock_irqrestore(&amd->lock, flags); | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
dcc94db7 | 614 | static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 615 | { |
dcc94db7 TI |
616 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
617 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
618 | unsigned int size = snd_pcm_lib_buffer_bytes(substream); |
619 | unsigned long flags; | |
620 | u8 new_mmr1; | |
621 | ||
622 | spin_lock_irqsave(&amd->lock, flags); | |
623 | ||
624 | amd->flags |= AMD7930_FLAG_CAPTURE; | |
625 | ||
626 | /* Setup the pseudo-dma transfer pointers. */ | |
627 | amd->c_orig = amd->c_cur = runtime->dma_area; | |
628 | amd->c_left = size; | |
629 | ||
630 | /* Put the chip into the correct encoding format. */ | |
631 | new_mmr1 = amd->map.mmr1; | |
632 | if (runtime->format == SNDRV_PCM_FORMAT_A_LAW) | |
633 | new_mmr1 |= AM_MAP_MMR1_ALAW; | |
634 | else | |
635 | new_mmr1 &= ~AM_MAP_MMR1_ALAW; | |
636 | if (new_mmr1 != amd->map.mmr1) { | |
637 | amd->map.mmr1 = new_mmr1; | |
638 | __amd7930_update_map(amd); | |
639 | } | |
640 | ||
641 | spin_unlock_irqrestore(&amd->lock, flags); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
dcc94db7 | 646 | static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 647 | { |
dcc94db7 | 648 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
649 | size_t ptr; |
650 | ||
651 | if (!(amd->flags & AMD7930_FLAG_PLAYBACK)) | |
652 | return 0; | |
653 | ptr = amd->p_cur - amd->p_orig; | |
654 | return bytes_to_frames(substream->runtime, ptr); | |
655 | } | |
656 | ||
dcc94db7 | 657 | static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 658 | { |
dcc94db7 | 659 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
660 | size_t ptr; |
661 | ||
662 | if (!(amd->flags & AMD7930_FLAG_CAPTURE)) | |
663 | return 0; | |
664 | ||
665 | ptr = amd->c_cur - amd->c_orig; | |
666 | return bytes_to_frames(substream->runtime, ptr); | |
667 | } | |
668 | ||
669 | /* Playback and capture have identical properties. */ | |
688ed206 | 670 | static const struct snd_pcm_hardware snd_amd7930_pcm_hw = |
1da177e4 LT |
671 | { |
672 | .info = (SNDRV_PCM_INFO_MMAP | | |
673 | SNDRV_PCM_INFO_MMAP_VALID | | |
674 | SNDRV_PCM_INFO_INTERLEAVED | | |
675 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
676 | SNDRV_PCM_INFO_HALF_DUPLEX), | |
677 | .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, | |
678 | .rates = SNDRV_PCM_RATE_8000, | |
679 | .rate_min = 8000, | |
680 | .rate_max = 8000, | |
681 | .channels_min = 1, | |
682 | .channels_max = 1, | |
683 | .buffer_bytes_max = (64*1024), | |
684 | .period_bytes_min = 1, | |
685 | .period_bytes_max = (64*1024), | |
686 | .periods_min = 1, | |
687 | .periods_max = 1024, | |
688 | }; | |
689 | ||
dcc94db7 | 690 | static int snd_amd7930_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 691 | { |
dcc94db7 TI |
692 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
693 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
694 | |
695 | amd->playback_substream = substream; | |
696 | runtime->hw = snd_amd7930_pcm_hw; | |
697 | return 0; | |
698 | } | |
699 | ||
dcc94db7 | 700 | static int snd_amd7930_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 701 | { |
dcc94db7 TI |
702 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
703 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
704 | |
705 | amd->capture_substream = substream; | |
706 | runtime->hw = snd_amd7930_pcm_hw; | |
707 | return 0; | |
708 | } | |
709 | ||
dcc94db7 | 710 | static int snd_amd7930_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 711 | { |
dcc94db7 | 712 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
713 | |
714 | amd->playback_substream = NULL; | |
715 | return 0; | |
716 | } | |
717 | ||
dcc94db7 | 718 | static int snd_amd7930_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 719 | { |
dcc94db7 | 720 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
1da177e4 LT |
721 | |
722 | amd->capture_substream = NULL; | |
723 | return 0; | |
724 | } | |
725 | ||
dcc94db7 TI |
726 | static int snd_amd7930_hw_params(struct snd_pcm_substream *substream, |
727 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
728 | { |
729 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
730 | } | |
731 | ||
dcc94db7 | 732 | static int snd_amd7930_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
733 | { |
734 | return snd_pcm_lib_free_pages(substream); | |
735 | } | |
736 | ||
544d6272 | 737 | static const struct snd_pcm_ops snd_amd7930_playback_ops = { |
1da177e4 LT |
738 | .open = snd_amd7930_playback_open, |
739 | .close = snd_amd7930_playback_close, | |
740 | .ioctl = snd_pcm_lib_ioctl, | |
741 | .hw_params = snd_amd7930_hw_params, | |
742 | .hw_free = snd_amd7930_hw_free, | |
743 | .prepare = snd_amd7930_playback_prepare, | |
744 | .trigger = snd_amd7930_playback_trigger, | |
745 | .pointer = snd_amd7930_playback_pointer, | |
746 | }; | |
747 | ||
544d6272 | 748 | static const struct snd_pcm_ops snd_amd7930_capture_ops = { |
1da177e4 LT |
749 | .open = snd_amd7930_capture_open, |
750 | .close = snd_amd7930_capture_close, | |
751 | .ioctl = snd_pcm_lib_ioctl, | |
752 | .hw_params = snd_amd7930_hw_params, | |
753 | .hw_free = snd_amd7930_hw_free, | |
754 | .prepare = snd_amd7930_capture_prepare, | |
755 | .trigger = snd_amd7930_capture_trigger, | |
756 | .pointer = snd_amd7930_capture_pointer, | |
757 | }; | |
758 | ||
32e02a7b | 759 | static int snd_amd7930_pcm(struct snd_amd7930 *amd) |
1da177e4 | 760 | { |
dcc94db7 | 761 | struct snd_pcm *pcm; |
1da177e4 LT |
762 | int err; |
763 | ||
764 | if ((err = snd_pcm_new(amd->card, | |
765 | /* ID */ "sun_amd7930", | |
766 | /* device */ 0, | |
767 | /* playback count */ 1, | |
768 | /* capture count */ 1, &pcm)) < 0) | |
769 | return err; | |
1da177e4 LT |
770 | |
771 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops); | |
772 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops); | |
773 | ||
774 | pcm->private_data = amd; | |
1da177e4 LT |
775 | pcm->info_flags = 0; |
776 | strcpy(pcm->name, amd->card->shortname); | |
777 | amd->pcm = pcm; | |
778 | ||
779 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, | |
780 | snd_dma_continuous_data(GFP_KERNEL), | |
781 | 64*1024, 64*1024); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | #define VOLUME_MONITOR 0 | |
787 | #define VOLUME_CAPTURE 1 | |
788 | #define VOLUME_PLAYBACK 2 | |
789 | ||
dcc94db7 | 790 | static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 791 | { |
1da177e4 LT |
792 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
793 | uinfo->count = 1; | |
794 | uinfo->value.integer.min = 0; | |
795 | uinfo->value.integer.max = 255; | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
dcc94db7 | 800 | static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 801 | { |
dcc94db7 | 802 | struct snd_amd7930 *amd = snd_kcontrol_chip(kctl); |
1da177e4 LT |
803 | int type = kctl->private_value; |
804 | int *swval; | |
805 | ||
1da177e4 LT |
806 | switch (type) { |
807 | case VOLUME_MONITOR: | |
808 | swval = &amd->mgain; | |
809 | break; | |
810 | case VOLUME_CAPTURE: | |
811 | swval = &amd->rgain; | |
812 | break; | |
813 | case VOLUME_PLAYBACK: | |
814 | default: | |
815 | swval = &amd->pgain; | |
816 | break; | |
395d9dd5 | 817 | } |
1da177e4 LT |
818 | |
819 | ucontrol->value.integer.value[0] = *swval; | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
dcc94db7 | 824 | static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 825 | { |
dcc94db7 | 826 | struct snd_amd7930 *amd = snd_kcontrol_chip(kctl); |
1da177e4 LT |
827 | unsigned long flags; |
828 | int type = kctl->private_value; | |
829 | int *swval, change; | |
830 | ||
1da177e4 LT |
831 | switch (type) { |
832 | case VOLUME_MONITOR: | |
833 | swval = &amd->mgain; | |
834 | break; | |
835 | case VOLUME_CAPTURE: | |
836 | swval = &amd->rgain; | |
837 | break; | |
838 | case VOLUME_PLAYBACK: | |
839 | default: | |
840 | swval = &amd->pgain; | |
841 | break; | |
395d9dd5 | 842 | } |
1da177e4 LT |
843 | |
844 | spin_lock_irqsave(&amd->lock, flags); | |
845 | ||
846 | if (*swval != ucontrol->value.integer.value[0]) { | |
3b892467 | 847 | *swval = ucontrol->value.integer.value[0] & 0xff; |
1da177e4 LT |
848 | __amd7930_update_map(amd); |
849 | change = 1; | |
850 | } else | |
851 | change = 0; | |
852 | ||
853 | spin_unlock_irqrestore(&amd->lock, flags); | |
854 | ||
855 | return change; | |
856 | } | |
857 | ||
32e02a7b | 858 | static struct snd_kcontrol_new amd7930_controls[] = { |
1da177e4 LT |
859 | { |
860 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
861 | .name = "Monitor Volume", | |
862 | .index = 0, | |
863 | .info = snd_amd7930_info_volume, | |
864 | .get = snd_amd7930_get_volume, | |
865 | .put = snd_amd7930_put_volume, | |
866 | .private_value = VOLUME_MONITOR, | |
867 | }, | |
868 | { | |
869 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
870 | .name = "Capture Volume", | |
871 | .index = 0, | |
872 | .info = snd_amd7930_info_volume, | |
873 | .get = snd_amd7930_get_volume, | |
874 | .put = snd_amd7930_put_volume, | |
875 | .private_value = VOLUME_CAPTURE, | |
876 | }, | |
877 | { | |
878 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
879 | .name = "Playback Volume", | |
880 | .index = 0, | |
881 | .info = snd_amd7930_info_volume, | |
882 | .get = snd_amd7930_get_volume, | |
883 | .put = snd_amd7930_put_volume, | |
884 | .private_value = VOLUME_PLAYBACK, | |
885 | }, | |
886 | }; | |
887 | ||
32e02a7b | 888 | static int snd_amd7930_mixer(struct snd_amd7930 *amd) |
1da177e4 | 889 | { |
dcc94db7 | 890 | struct snd_card *card; |
1da177e4 LT |
891 | int idx, err; |
892 | ||
5e246b85 TI |
893 | if (snd_BUG_ON(!amd || !amd->card)) |
894 | return -EINVAL; | |
1da177e4 LT |
895 | |
896 | card = amd->card; | |
897 | strcpy(card->mixername, card->shortname); | |
898 | ||
899 | for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) { | |
900 | if ((err = snd_ctl_add(card, | |
901 | snd_ctl_new1(&amd7930_controls[idx], amd))) < 0) | |
902 | return err; | |
903 | } | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
dcc94db7 | 908 | static int snd_amd7930_free(struct snd_amd7930 *amd) |
1da177e4 | 909 | { |
2dc11581 | 910 | struct platform_device *op = amd->op; |
dc8aa2e9 | 911 | |
1da177e4 LT |
912 | amd7930_idle(amd); |
913 | ||
914 | if (amd->irq) | |
915 | free_irq(amd->irq, amd); | |
916 | ||
917 | if (amd->regs) | |
dc8aa2e9 DM |
918 | of_iounmap(&op->resource[0], amd->regs, |
919 | resource_size(&op->resource[0])); | |
1da177e4 LT |
920 | |
921 | kfree(amd); | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
dcc94db7 | 926 | static int snd_amd7930_dev_free(struct snd_device *device) |
1da177e4 | 927 | { |
dcc94db7 | 928 | struct snd_amd7930 *amd = device->device_data; |
1da177e4 LT |
929 | |
930 | return snd_amd7930_free(amd); | |
931 | } | |
932 | ||
dcc94db7 | 933 | static struct snd_device_ops snd_amd7930_dev_ops = { |
1da177e4 LT |
934 | .dev_free = snd_amd7930_dev_free, |
935 | }; | |
936 | ||
32e02a7b BP |
937 | static int snd_amd7930_create(struct snd_card *card, |
938 | struct platform_device *op, | |
939 | int irq, int dev, | |
940 | struct snd_amd7930 **ramd) | |
1da177e4 | 941 | { |
dcc94db7 | 942 | struct snd_amd7930 *amd; |
dc8aa2e9 | 943 | unsigned long flags; |
1da177e4 LT |
944 | int err; |
945 | ||
946 | *ramd = NULL; | |
561b220a | 947 | amd = kzalloc(sizeof(*amd), GFP_KERNEL); |
1da177e4 LT |
948 | if (amd == NULL) |
949 | return -ENOMEM; | |
950 | ||
951 | spin_lock_init(&amd->lock); | |
952 | amd->card = card; | |
dc8aa2e9 | 953 | amd->op = op; |
1da177e4 | 954 | |
dc8aa2e9 DM |
955 | amd->regs = of_ioremap(&op->resource[0], 0, |
956 | resource_size(&op->resource[0]), "amd7930"); | |
1da177e4 | 957 | if (!amd->regs) { |
2ebfb8ee TI |
958 | snd_printk(KERN_ERR |
959 | "amd7930-%d: Unable to map chip registers.\n", dev); | |
25e5eaf1 | 960 | kfree(amd); |
1da177e4 LT |
961 | return -EIO; |
962 | } | |
963 | ||
964 | amd7930_idle(amd); | |
965 | ||
69b5c4f1 | 966 | if (request_irq(irq, snd_amd7930_interrupt, |
88e24c3a | 967 | IRQF_SHARED, "amd7930", amd)) { |
2ebfb8ee | 968 | snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n", |
69b5c4f1 | 969 | dev, irq); |
1da177e4 LT |
970 | snd_amd7930_free(amd); |
971 | return -EBUSY; | |
972 | } | |
69b5c4f1 | 973 | amd->irq = irq; |
1da177e4 LT |
974 | |
975 | amd7930_enable_ints(amd); | |
976 | ||
977 | spin_lock_irqsave(&amd->lock, flags); | |
978 | ||
979 | amd->rgain = 128; | |
980 | amd->pgain = 200; | |
981 | amd->mgain = 0; | |
982 | ||
983 | memset(&amd->map, 0, sizeof(amd->map)); | |
984 | amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER | | |
985 | AM_MAP_MMR1_GR | AM_MAP_MMR1_STG); | |
986 | amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB); | |
987 | ||
988 | __amd7930_update_map(amd); | |
989 | ||
990 | /* Always MUX audio (Ba) to channel Bb. */ | |
991 | sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR); | |
992 | sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4), | |
993 | amd->regs + AMD7930_DR); | |
994 | ||
995 | spin_unlock_irqrestore(&amd->lock, flags); | |
996 | ||
997 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, | |
998 | amd, &snd_amd7930_dev_ops)) < 0) { | |
999 | snd_amd7930_free(amd); | |
1000 | return err; | |
1001 | } | |
1002 | ||
1003 | *ramd = amd; | |
1004 | return 0; | |
1005 | } | |
1006 | ||
32e02a7b | 1007 | static int amd7930_sbus_probe(struct platform_device *op) |
1da177e4 | 1008 | { |
dc8aa2e9 | 1009 | struct resource *rp = &op->resource[0]; |
69b5c4f1 | 1010 | static int dev_num; |
dcc94db7 TI |
1011 | struct snd_card *card; |
1012 | struct snd_amd7930 *amd; | |
dc8aa2e9 DM |
1013 | int err, irq; |
1014 | ||
1636f8ac | 1015 | irq = op->archdata.irqs[0]; |
1da177e4 | 1016 | |
69b5c4f1 | 1017 | if (dev_num >= SNDRV_CARDS) |
1da177e4 | 1018 | return -ENODEV; |
69b5c4f1 DM |
1019 | if (!enable[dev_num]) { |
1020 | dev_num++; | |
1da177e4 LT |
1021 | return -ENOENT; |
1022 | } | |
1023 | ||
a2fefc35 TI |
1024 | err = snd_card_new(&op->dev, index[dev_num], id[dev_num], |
1025 | THIS_MODULE, 0, &card); | |
bd7dd77c TI |
1026 | if (err < 0) |
1027 | return err; | |
1da177e4 LT |
1028 | |
1029 | strcpy(card->driver, "AMD7930"); | |
1030 | strcpy(card->shortname, "Sun AMD7930"); | |
5863aa65 | 1031 | sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d", |
1da177e4 LT |
1032 | card->shortname, |
1033 | rp->flags & 0xffL, | |
5863aa65 | 1034 | (unsigned long long)rp->start, |
69b5c4f1 | 1035 | irq); |
1da177e4 | 1036 | |
dc8aa2e9 | 1037 | if ((err = snd_amd7930_create(card, op, |
69b5c4f1 | 1038 | irq, dev_num, &amd)) < 0) |
1da177e4 LT |
1039 | goto out_err; |
1040 | ||
1041 | if ((err = snd_amd7930_pcm(amd)) < 0) | |
1042 | goto out_err; | |
1043 | ||
1044 | if ((err = snd_amd7930_mixer(amd)) < 0) | |
1045 | goto out_err; | |
1046 | ||
1047 | if ((err = snd_card_register(card)) < 0) | |
1048 | goto out_err; | |
1049 | ||
1050 | amd->next = amd7930_list; | |
1051 | amd7930_list = amd; | |
1052 | ||
69b5c4f1 DM |
1053 | dev_num++; |
1054 | ||
1da177e4 LT |
1055 | return 0; |
1056 | ||
1057 | out_err: | |
1058 | snd_card_free(card); | |
1059 | return err; | |
1060 | } | |
1061 | ||
fd098316 | 1062 | static const struct of_device_id amd7930_match[] = { |
69b5c4f1 DM |
1063 | { |
1064 | .name = "audio", | |
1065 | }, | |
1066 | {}, | |
1067 | }; | |
86bfbc15 | 1068 | MODULE_DEVICE_TABLE(of, amd7930_match); |
69b5c4f1 | 1069 | |
f07eb223 | 1070 | static struct platform_driver amd7930_sbus_driver = { |
4018294b GL |
1071 | .driver = { |
1072 | .name = "audio", | |
4018294b GL |
1073 | .of_match_table = amd7930_match, |
1074 | }, | |
69b5c4f1 DM |
1075 | .probe = amd7930_sbus_probe, |
1076 | }; | |
1077 | ||
1078 | static int __init amd7930_init(void) | |
1079 | { | |
f07eb223 | 1080 | return platform_driver_register(&amd7930_sbus_driver); |
1da177e4 LT |
1081 | } |
1082 | ||
1083 | static void __exit amd7930_exit(void) | |
1084 | { | |
dcc94db7 | 1085 | struct snd_amd7930 *p = amd7930_list; |
1da177e4 LT |
1086 | |
1087 | while (p != NULL) { | |
dcc94db7 | 1088 | struct snd_amd7930 *next = p->next; |
1da177e4 LT |
1089 | |
1090 | snd_card_free(p->card); | |
1091 | ||
1092 | p = next; | |
1093 | } | |
1094 | ||
1095 | amd7930_list = NULL; | |
69b5c4f1 | 1096 | |
f07eb223 | 1097 | platform_driver_unregister(&amd7930_sbus_driver); |
1da177e4 LT |
1098 | } |
1099 | ||
1100 | module_init(amd7930_init); | |
1101 | module_exit(amd7930_exit); |