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ALSA: x86: Drop superfluous state field
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1/*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
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24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
da864809 28#include <linux/interrupt.h>
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29#include <linux/acpi.h>
30#include <asm/cacheflush.h>
31#include <sound/pcm.h>
32#include <sound/core.h>
33#include <sound/pcm_params.h>
34#include <sound/initval.h>
35#include <sound/control.h>
36#include <sound/initval.h>
da864809 37#include <drm/intel_lpe_audio.h>
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38#include "intel_hdmi_audio.h"
39
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40/*standard module options for ALSA. This module supports only one card*/
41static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
42static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
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43
44module_param_named(index, hdmi_card_index, int, 0444);
45MODULE_PARM_DESC(index,
46 "Index value for INTEL Intel HDMI Audio controller.");
47module_param_named(id, hdmi_card_id, charp, 0444);
48MODULE_PARM_DESC(id,
49 "ID string for INTEL Intel HDMI Audio controller.");
50
51/*
52 * ELD SA bits in the CEA Speaker Allocation data block
53 */
4a5ddb2c 54static const int eld_speaker_allocation_bits[] = {
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55 [0] = FL | FR,
56 [1] = LFE,
57 [2] = FC,
58 [3] = RL | RR,
59 [4] = RC,
60 [5] = FLC | FRC,
61 [6] = RLC | RRC,
62 /* the following are not defined in ELD yet */
63 [7] = 0,
64};
65
66/*
67 * This is an ordered list!
68 *
69 * The preceding ones have better chances to be selected by
70 * hdmi_channel_allocation().
71 */
72static struct cea_channel_speaker_allocation channel_allocations[] = {
73/* channel: 7 6 5 4 3 2 1 0 */
74{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
75 /* 2.1 */
76{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
77 /* Dolby Surround */
78{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
79 /* surround40 */
80{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
81 /* surround41 */
82{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
83 /* surround50 */
84{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
85 /* surround51 */
86{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
87 /* 6.1 */
88{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
89 /* surround71 */
90{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
91
92{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
93{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
94{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
95{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
96{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
97{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
98{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
99{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
100{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
101{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
102{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
103{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
104{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
105{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
106{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
107{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
108{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
109{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
110{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
111{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
112{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
113{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
114{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
115};
116
4a5ddb2c 117static const struct channel_map_table map_tables[] = {
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118 { SNDRV_CHMAP_FL, 0x00, FL },
119 { SNDRV_CHMAP_FR, 0x01, FR },
120 { SNDRV_CHMAP_RL, 0x04, RL },
121 { SNDRV_CHMAP_RR, 0x05, RR },
122 { SNDRV_CHMAP_LFE, 0x02, LFE },
123 { SNDRV_CHMAP_FC, 0x03, FC },
124 { SNDRV_CHMAP_RLC, 0x06, RLC },
125 { SNDRV_CHMAP_RRC, 0x07, RRC },
126 {} /* terminator */
127};
128
129/* hardware capability structure */
130static const struct snd_pcm_hardware snd_intel_hadstream = {
131 .info = (SNDRV_PCM_INFO_INTERLEAVED |
132 SNDRV_PCM_INFO_DOUBLE |
133 SNDRV_PCM_INFO_MMAP|
134 SNDRV_PCM_INFO_MMAP_VALID |
135 SNDRV_PCM_INFO_BATCH),
136 .formats = (SNDRV_PCM_FMTBIT_S24 |
137 SNDRV_PCM_FMTBIT_U24),
138 .rates = SNDRV_PCM_RATE_32000 |
139 SNDRV_PCM_RATE_44100 |
140 SNDRV_PCM_RATE_48000 |
141 SNDRV_PCM_RATE_88200 |
142 SNDRV_PCM_RATE_96000 |
143 SNDRV_PCM_RATE_176400 |
144 SNDRV_PCM_RATE_192000,
145 .rate_min = HAD_MIN_RATE,
146 .rate_max = HAD_MAX_RATE,
147 .channels_min = HAD_MIN_CHANNEL,
148 .channels_max = HAD_MAX_CHANNEL,
149 .buffer_bytes_max = HAD_MAX_BUFFER,
150 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
151 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
152 .periods_min = HAD_MIN_PERIODS,
153 .periods_max = HAD_MAX_PERIODS,
154 .fifo_size = HAD_FIFO_SIZE,
155};
156
157/* Register access functions */
da864809
TI
158static inline void
159mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
5dab11d8 160{
da864809 161 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
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162}
163
da864809
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164static inline void
165mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
5dab11d8 166{
da864809 167 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
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168}
169
372d855f
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170static int had_read_register(struct snd_intelhad *intelhaddata,
171 u32 offset, u32 *data)
5dab11d8 172{
79f439ea
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173 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
174 return -ENODEV;
5dab11d8 175
da864809
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176 mid_hdmi_audio_read(intelhaddata, offset, data);
177 return 0;
178}
179
180static void fixup_dp_config(struct snd_intelhad *intelhaddata,
181 u32 offset, u32 *data)
182{
183 if (intelhaddata->dp_output) {
184 if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
185 *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
186 }
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187}
188
372d855f
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189static int had_write_register(struct snd_intelhad *intelhaddata,
190 u32 offset, u32 data)
5dab11d8 191{
79f439ea
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192 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
193 return -ENODEV;
5dab11d8 194
da864809
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195 fixup_dp_config(intelhaddata, offset, &data);
196 mid_hdmi_audio_write(intelhaddata, offset, data);
197 return 0;
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198}
199
372d855f
TI
200static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
201 u32 data, u32 mask)
5dab11d8 202{
da864809 203 u32 val_tmp;
5dab11d8 204
79f439ea
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205 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
206 return -ENODEV;
5dab11d8 207
da864809
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208 mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
209 val_tmp &= ~mask;
210 val_tmp |= (data & mask);
211
212 fixup_dp_config(intelhaddata, offset, &val_tmp);
213 mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
214 return 0;
5dab11d8 215}
da864809
TI
216
217/*
218 * function to read-modify AUD_CONFIG register on VLV2.
219 * The had_read_modify() function should not directly be used on VLV2 for
220 * updating AUD_CONFIG register.
5dab11d8
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221 * This is because:
222 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
223 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
224 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
225 * register. This field should be 1xy binary for configuration with 6 or
226 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
227 * causes the "channels" field to be updated as 0xy binary resulting in
228 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
229 * appropriate value when doing read-modify of AUD_CONFIG register.
230 *
231 * @substream: the current substream or NULL if no active substream
232 * @data : data to be written
233 * @mask : mask
234 *
235 */
da864809 236static int had_read_modify_aud_config_v2(struct snd_intelhad *intelhaddata,
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237 u32 data, u32 mask)
238{
da864809 239 struct snd_pcm_substream *substream;
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240 union aud_cfg cfg_val = {.cfg_regval = 0};
241 u8 channels;
242
243 /*
244 * If substream is NULL, there is no active stream.
245 * In this case just set channels to 2
246 */
da864809
TI
247 substream = intelhaddata->stream_info.had_substream;
248 if (substream && substream->runtime)
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249 channels = substream->runtime->channels;
250 else
251 channels = 2;
4151ee84 252 cfg_val.cfg_regx.num_ch = channels - 2;
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253
254 data = data | cfg_val.cfg_regval;
4151ee84 255 mask = mask | AUD_CONFIG_CH_MASK;
5dab11d8 256
c75b0476
TI
257 dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n",
258 __func__, data, mask);
5dab11d8 259
79dda75a 260 return had_read_modify(intelhaddata, AUD_CONFIG, data, mask);
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261}
262
372d855f 263static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
da864809
TI
264{
265 u32 status_reg;
266
267 if (enable) {
4151ee84 268 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
da864809 269 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
4151ee84
TI
270 mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg);
271 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
da864809
TI
272 }
273}
274
372d855f
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275static void snd_intelhad_enable_audio(struct snd_intelhad *intelhaddata,
276 bool enable)
5dab11d8 277{
da864809
TI
278 had_read_modify_aud_config_v2(intelhaddata, enable ? BIT(0) : 0,
279 BIT(0));
5dab11d8
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280}
281
79dda75a
TI
282static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
283 u8 reset)
5dab11d8 284{
4151ee84 285 had_write_register(intelhaddata, AUD_HDMI_STATUS, reset);
5dab11d8
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286}
287
2e52f5e5 288/*
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289 * initialize audio channel status registers
290 * This function is called in the prepare callback
291 */
292static int had_prog_status_reg(struct snd_pcm_substream *substream,
293 struct snd_intelhad *intelhaddata)
294{
295 union aud_cfg cfg_val = {.cfg_regval = 0};
296 union aud_ch_status_0 ch_stat0 = {.status_0_regval = 0};
297 union aud_ch_status_1 ch_stat1 = {.status_1_regval = 0};
298 int format;
299
5dab11d8 300 ch_stat0.status_0_regx.lpcm_id = (intelhaddata->aes_bits &
2e52f5e5 301 IEC958_AES0_NONAUDIO) >> 1;
5dab11d8 302 ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
2e52f5e5 303 IEC958_AES3_CON_CLOCK) >> 4;
4151ee84 304 cfg_val.cfg_regx.val_bit = ch_stat0.status_0_regx.lpcm_id;
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305
306 switch (substream->runtime->rate) {
307 case AUD_SAMPLE_RATE_32:
308 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_32KHZ;
309 break;
310
311 case AUD_SAMPLE_RATE_44_1:
312 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_44KHZ;
313 break;
314 case AUD_SAMPLE_RATE_48:
315 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_48KHZ;
316 break;
317 case AUD_SAMPLE_RATE_88_2:
318 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_88KHZ;
319 break;
320 case AUD_SAMPLE_RATE_96:
321 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_96KHZ;
322 break;
323 case AUD_SAMPLE_RATE_176_4:
324 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_176KHZ;
325 break;
326 case AUD_SAMPLE_RATE_192:
327 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_192KHZ;
328 break;
329
330 default:
331 /* control should never come here */
332 return -EINVAL;
5dab11d8 333 }
2e52f5e5 334
79dda75a
TI
335 had_write_register(intelhaddata,
336 AUD_CH_STATUS_0, ch_stat0.status_0_regval);
5dab11d8
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337
338 format = substream->runtime->format;
339
340 if (format == SNDRV_PCM_FORMAT_S16_LE) {
341 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_20;
342 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_16BITS;
343 } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
344 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_24;
345 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_24BITS;
346 } else {
347 ch_stat1.status_1_regx.max_wrd_len = 0;
348 ch_stat1.status_1_regx.wrd_len = 0;
349 }
2e52f5e5 350
79dda75a
TI
351 had_write_register(intelhaddata,
352 AUD_CH_STATUS_1, ch_stat1.status_1_regval);
5dab11d8
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353 return 0;
354}
355
76296ef0 356/*
5dab11d8
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357 * function to initialize audio
358 * registers and buffer confgiuration registers
359 * This function is called in the prepare callback
360 */
76296ef0
TI
361static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
362 struct snd_intelhad *intelhaddata)
5dab11d8
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363{
364 union aud_cfg cfg_val = {.cfg_regval = 0};
365 union aud_buf_config buf_cfg = {.buf_cfgval = 0};
366 u8 channels;
367
368 had_prog_status_reg(substream, intelhaddata);
369
4151ee84
TI
370 buf_cfg.buf_cfg_regx.audio_fifo_watermark = FIFO_THRESHOLD;
371 buf_cfg.buf_cfg_regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
372 buf_cfg.buf_cfg_regx.aud_delay = 0;
79dda75a 373 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
5dab11d8
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374
375 channels = substream->runtime->channels;
4151ee84 376 cfg_val.cfg_regx.num_ch = channels - 2;
5dab11d8 377 if (channels <= 2)
4151ee84 378 cfg_val.cfg_regx.layout = LAYOUT0;
5dab11d8 379 else
4151ee84 380 cfg_val.cfg_regx.layout = LAYOUT1;
5dab11d8 381
4151ee84 382 cfg_val.cfg_regx.val_bit = 1;
79dda75a 383 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.cfg_regval);
5dab11d8
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384 return 0;
385}
386
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387/*
388 * Compute derived values in channel_allocations[].
389 */
390static void init_channel_allocations(void)
391{
392 int i, j;
393 struct cea_channel_speaker_allocation *p;
394
5dab11d8
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395 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
396 p = channel_allocations + i;
397 p->channels = 0;
398 p->spk_mask = 0;
399 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
400 if (p->speakers[j]) {
401 p->channels++;
402 p->spk_mask |= p->speakers[j];
403 }
404 }
405}
406
407/*
408 * The transformation takes two steps:
409 *
410 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
411 * spk_mask => (channel_allocations[]) => ai->CA
412 *
413 * TODO: it could select the wrong CA from multiple candidates.
414 */
415static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata,
416 int channels)
417{
418 int i;
419 int ca = 0;
420 int spk_mask = 0;
421
422 /*
423 * CA defaults to 0 for basic stereo audio
424 */
425 if (channels <= 2)
426 return 0;
427
428 /*
429 * expand ELD's speaker allocation mask
430 *
431 * ELD tells the speaker mask in a compact(paired) form,
432 * expand ELD's notions to match the ones used by Audio InfoFrame.
433 */
434
435 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 436 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
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437 spk_mask |= eld_speaker_allocation_bits[i];
438 }
439
440 /* search for the first working match in the CA table */
441 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
442 if (channels == channel_allocations[i].channels &&
443 (spk_mask & channel_allocations[i].spk_mask) ==
444 channel_allocations[i].spk_mask) {
445 ca = channel_allocations[i].ca_index;
446 break;
447 }
448 }
449
c75b0476 450 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
5dab11d8
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451
452 return ca;
453}
454
455/* from speaker bit mask to ALSA API channel position */
456static int spk_to_chmap(int spk)
457{
4a5ddb2c 458 const struct channel_map_table *t = map_tables;
5dab11d8
JA
459
460 for (; t->map; t++) {
461 if (t->spk_mask == spk)
462 return t->map;
463 }
464 return 0;
465}
466
372d855f 467static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
5dab11d8 468{
2e52f5e5 469 int i, c;
5dab11d8
JA
470 int spk_mask = 0;
471 struct snd_pcm_chmap_elem *chmap;
472 u8 eld_high, eld_high_mask = 0xF0;
473 u8 high_msb;
474
475 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
2e52f5e5 476 if (!chmap) {
5dab11d8
JA
477 intelhaddata->chmap->chmap = NULL;
478 return;
479 }
480
c75b0476 481 dev_dbg(intelhaddata->dev, "eld.speaker_allocation_block = %x\n",
da864809 482 intelhaddata->eld.speaker_allocation_block);
5dab11d8
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483
484 /* WA: Fix the max channel supported to 8 */
485
486 /*
487 * Sink may support more than 8 channels, if eld_high has more than
488 * one bit set. SOC supports max 8 channels.
489 * Refer eld_speaker_allocation_bits, for sink speaker allocation
490 */
491
492 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
da864809 493 eld_high = intelhaddata->eld.speaker_allocation_block & eld_high_mask;
5dab11d8
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494 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
495 /* eld_high & (eld_high-1): if more than 1 bit set */
496 /* 0x1F: 7 channels */
497 for (i = 1; i < 4; i++) {
498 high_msb = eld_high & (0x80 >> i);
499 if (high_msb) {
da864809 500 intelhaddata->eld.speaker_allocation_block &=
5dab11d8
JA
501 high_msb | 0xF;
502 break;
503 }
504 }
505 }
506
507 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 508 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
JA
509 spk_mask |= eld_speaker_allocation_bits[i];
510 }
511
512 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
513 if (spk_mask == channel_allocations[i].spk_mask) {
514 for (c = 0; c < channel_allocations[i].channels; c++) {
515 chmap->map[c] = spk_to_chmap(
516 channel_allocations[i].speakers[
2e52f5e5 517 (MAX_SPEAKERS - 1) - c]);
5dab11d8
JA
518 }
519 chmap->channels = channel_allocations[i].channels;
520 intelhaddata->chmap->chmap = chmap;
521 break;
522 }
523 }
524 if (i >= ARRAY_SIZE(channel_allocations)) {
525 intelhaddata->chmap->chmap = NULL;
526 kfree(chmap);
527 }
528}
529
530/*
531 * ALSA API channel-map control callbacks
532 */
533static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
534 struct snd_ctl_elem_info *uinfo)
535{
536 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
537 struct snd_intelhad *intelhaddata = info->private_data;
538
539 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
540 return -ENODEV;
541 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
542 uinfo->count = HAD_MAX_CHANNEL;
543 uinfo->value.integer.min = 0;
544 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
545 return 0;
546}
547
548static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
549 struct snd_ctl_elem_value *ucontrol)
550{
551 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
552 struct snd_intelhad *intelhaddata = info->private_data;
2e52f5e5 553 int i;
5dab11d8
JA
554 const struct snd_pcm_chmap_elem *chmap;
555
556 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
557 return -ENODEV;
8f8d1d7f
TI
558
559 mutex_lock(&intelhaddata->mutex);
560 if (!intelhaddata->chmap->chmap) {
561 mutex_unlock(&intelhaddata->mutex);
5dab11d8 562 return -ENODATA;
8f8d1d7f
TI
563 }
564
5dab11d8 565 chmap = intelhaddata->chmap->chmap;
c75b0476 566 for (i = 0; i < chmap->channels; i++)
5dab11d8 567 ucontrol->value.integer.value[i] = chmap->map[i];
8f8d1d7f 568 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA
569
570 return 0;
571}
572
573static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
574 struct snd_pcm *pcm)
575{
2e52f5e5 576 int err;
5dab11d8
JA
577
578 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
579 NULL, 0, (unsigned long)intelhaddata,
580 &intelhaddata->chmap);
581 if (err < 0)
582 return err;
583
584 intelhaddata->chmap->private_data = intelhaddata;
e9d65abf
TI
585 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
586 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
5dab11d8
JA
587 intelhaddata->chmap->chmap = NULL;
588 return 0;
589}
590
76296ef0
TI
591/*
592 * snd_intelhad_prog_dip - to initialize Data Island Packets registers
5dab11d8
JA
593 *
594 * @substream:substream for which the prepare function is called
595 * @intelhaddata:substream private data
596 *
597 * This function is called in the prepare callback
598 */
76296ef0
TI
599static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream,
600 struct snd_intelhad *intelhaddata)
5dab11d8
JA
601{
602 int i;
603 union aud_ctrl_st ctrl_state = {.ctrl_val = 0};
604 union aud_info_frame2 frame2 = {.fr2_val = 0};
605 union aud_info_frame3 frame3 = {.fr3_val = 0};
606 u8 checksum = 0;
964ca808 607 u32 info_frame;
5dab11d8
JA
608 int channels;
609
610 channels = substream->runtime->channels;
611
79dda75a 612 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8 613
964ca808
PLB
614 if (intelhaddata->dp_output) {
615 info_frame = DP_INFO_FRAME_WORD1;
616 frame2.fr2_val = 1;
617 } else {
618 info_frame = HDMI_INFO_FRAME_WORD1;
619 frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
5dab11d8 620
964ca808
PLB
621 frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
622 intelhaddata, channels);
5dab11d8 623
2e52f5e5 624 /* Calculte the byte wide checksum for all valid DIP words */
964ca808
PLB
625 for (i = 0; i < BYTES_PER_WORD; i++)
626 checksum += (info_frame >> i*BITS_PER_BYTE) & MASK_BYTE0;
627 for (i = 0; i < BYTES_PER_WORD; i++)
628 checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
629 for (i = 0; i < BYTES_PER_WORD; i++)
630 checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
5dab11d8 631
964ca808
PLB
632 frame2.fr2_regx.chksum = -(checksum);
633 }
5dab11d8 634
4151ee84
TI
635 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
636 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.fr2_val);
637 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.fr3_val);
5dab11d8
JA
638
639 /* program remaining DIP words with zero */
640 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
4151ee84 641 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
5dab11d8
JA
642
643 ctrl_state.ctrl_regx.dip_freq = 1;
644 ctrl_state.ctrl_regx.dip_en_sta = 1;
79dda75a 645 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8
JA
646}
647
2e52f5e5
TI
648/*
649 * snd_intelhad_prog_buffer - programs buffer address and length registers
5dab11d8
JA
650 * @substream:substream for which the prepare function is called
651 * @intelhaddata:substream private data
652 *
653 * This function programs ring buffer address and length into registers.
654 */
372d855f 655static int snd_intelhad_prog_buffer(struct snd_intelhad *intelhaddata,
5dab11d8
JA
656 int start, int end)
657{
658 u32 ring_buf_addr, ring_buf_size, period_bytes;
659 u8 i, num_periods;
660 struct snd_pcm_substream *substream;
661
662 substream = intelhaddata->stream_info.had_substream;
c75b0476 663 if (WARN_ON(!substream))
5dab11d8 664 return 0;
5dab11d8
JA
665
666 ring_buf_addr = substream->runtime->dma_addr;
667 ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
668 intelhaddata->stream_info.ring_buf_size = ring_buf_size;
669 period_bytes = frames_to_bytes(substream->runtime,
670 substream->runtime->period_size);
671 num_periods = substream->runtime->periods;
672
673 /*
674 * buffer addr should be 64 byte aligned, period bytes
675 * will be used to calculate addr offset
676 */
677 period_bytes &= ~0x3F;
678
679 /* Hardware supports MAX_PERIODS buffers */
680 if (end >= HAD_MAX_PERIODS)
681 return -EINVAL;
682
683 for (i = start; i <= end; i++) {
684 /* Program the buf registers with addr and len */
685 intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
686 (i * period_bytes);
687 if (i < num_periods-1)
688 intelhaddata->buf_info[i].buf_size = period_bytes;
689 else
690 intelhaddata->buf_info[i].buf_size = ring_buf_size -
2e52f5e5 691 (i * period_bytes);
5dab11d8 692
79dda75a
TI
693 had_write_register(intelhaddata,
694 AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
5dab11d8
JA
695 intelhaddata->buf_info[i].buf_addr |
696 BIT(0) | BIT(1));
79dda75a
TI
697 had_write_register(intelhaddata,
698 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
5dab11d8
JA
699 period_bytes);
700 intelhaddata->buf_info[i].is_valid = true;
701 }
c75b0476
TI
702 dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n",
703 __func__, start, end,
704 intelhaddata->buf_info[start].buf_addr,
705 intelhaddata->buf_info[start].buf_size);
5dab11d8
JA
706 intelhaddata->valid_buf_cnt = num_periods;
707 return 0;
708}
709
372d855f 710static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
5dab11d8
JA
711{
712 int i, retval = 0;
713 u32 len[4];
714
715 for (i = 0; i < 4 ; i++) {
79dda75a
TI
716 had_read_register(intelhaddata,
717 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
718 &len[i]);
5dab11d8
JA
719 if (!len[i])
720 retval++;
721 }
722 if (retval != 1) {
723 for (i = 0; i < 4 ; i++)
c75b0476
TI
724 dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n",
725 i, len[i]);
5dab11d8
JA
726 }
727
728 return retval;
729}
730
964ca808
PLB
731static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
732{
733 u32 maud_val;
734
2e52f5e5 735 /* Select maud according to DP 1.2 spec */
964ca808
PLB
736 if (link_rate == DP_2_7_GHZ) {
737 switch (aud_samp_freq) {
738 case AUD_SAMPLE_RATE_32:
739 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
740 break;
741
742 case AUD_SAMPLE_RATE_44_1:
743 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
744 break;
745
746 case AUD_SAMPLE_RATE_48:
747 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
748 break;
749
750 case AUD_SAMPLE_RATE_88_2:
751 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
752 break;
753
754 case AUD_SAMPLE_RATE_96:
755 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
756 break;
757
758 case AUD_SAMPLE_RATE_176_4:
759 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
760 break;
761
762 case HAD_MAX_RATE:
763 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
764 break;
765
766 default:
767 maud_val = -EINVAL;
768 break;
769 }
770 } else if (link_rate == DP_1_62_GHZ) {
771 switch (aud_samp_freq) {
772 case AUD_SAMPLE_RATE_32:
773 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
774 break;
775
776 case AUD_SAMPLE_RATE_44_1:
777 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
778 break;
779
780 case AUD_SAMPLE_RATE_48:
781 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
782 break;
783
784 case AUD_SAMPLE_RATE_88_2:
785 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
786 break;
787
788 case AUD_SAMPLE_RATE_96:
789 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
790 break;
791
792 case AUD_SAMPLE_RATE_176_4:
793 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
794 break;
795
796 case HAD_MAX_RATE:
797 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
798 break;
799
800 default:
801 maud_val = -EINVAL;
802 break;
803 }
804 } else
805 maud_val = -EINVAL;
806
807 return maud_val;
808}
809
76296ef0
TI
810/*
811 * snd_intelhad_prog_cts - Program HDMI audio CTS value
5dab11d8
JA
812 *
813 * @aud_samp_freq: sampling frequency of audio data
814 * @tmds: sampling frequency of the display data
815 * @n_param: N value, depends on aud_samp_freq
816 * @intelhaddata:substream private data
817 *
818 * Program CTS register based on the audio and display sampling frequency
819 */
76296ef0
TI
820static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds,
821 u32 link_rate, u32 n_param,
822 struct snd_intelhad *intelhaddata)
5dab11d8
JA
823{
824 u32 cts_val;
825 u64 dividend, divisor;
826
964ca808
PLB
827 if (intelhaddata->dp_output) {
828 /* Substitute cts_val with Maud according to DP 1.2 spec*/
829 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
830 } else {
831 /* Calculate CTS according to HDMI 1.3a spec*/
832 dividend = (u64)tmds * n_param*1000;
833 divisor = 128 * aud_samp_freq;
834 cts_val = div64_u64(dividend, divisor);
835 }
c75b0476 836 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
964ca808 837 tmds, n_param, cts_val);
79dda75a 838 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
5dab11d8
JA
839}
840
841static int had_calculate_n_value(u32 aud_samp_freq)
842{
2e52f5e5 843 int n_val;
5dab11d8
JA
844
845 /* Select N according to HDMI 1.3a spec*/
846 switch (aud_samp_freq) {
847 case AUD_SAMPLE_RATE_32:
848 n_val = 4096;
2e52f5e5 849 break;
5dab11d8
JA
850
851 case AUD_SAMPLE_RATE_44_1:
852 n_val = 6272;
2e52f5e5 853 break;
5dab11d8
JA
854
855 case AUD_SAMPLE_RATE_48:
856 n_val = 6144;
2e52f5e5 857 break;
5dab11d8
JA
858
859 case AUD_SAMPLE_RATE_88_2:
860 n_val = 12544;
2e52f5e5 861 break;
5dab11d8
JA
862
863 case AUD_SAMPLE_RATE_96:
864 n_val = 12288;
2e52f5e5 865 break;
5dab11d8
JA
866
867 case AUD_SAMPLE_RATE_176_4:
868 n_val = 25088;
2e52f5e5 869 break;
5dab11d8
JA
870
871 case HAD_MAX_RATE:
872 n_val = 24576;
2e52f5e5 873 break;
5dab11d8
JA
874
875 default:
876 n_val = -EINVAL;
2e52f5e5 877 break;
5dab11d8
JA
878 }
879 return n_val;
880}
881
76296ef0
TI
882/*
883 * snd_intelhad_prog_n - Program HDMI audio N value
5dab11d8
JA
884 *
885 * @aud_samp_freq: sampling frequency of audio data
886 * @n_param: N value, depends on aud_samp_freq
887 * @intelhaddata:substream private data
888 *
889 * This function is called in the prepare callback.
890 * It programs based on the audio and display sampling frequency
891 */
76296ef0
TI
892static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param,
893 struct snd_intelhad *intelhaddata)
5dab11d8 894{
2e52f5e5 895 int n_val;
5dab11d8 896
964ca808
PLB
897 if (intelhaddata->dp_output) {
898 /*
899 * According to DP specs, Maud and Naud values hold
900 * a relationship, which is stated as:
901 * Maud/Naud = 512 * fs / f_LS_Clk
902 * where, fs is the sampling frequency of the audio stream
903 * and Naud is 32768 for Async clock.
904 */
905
906 n_val = DP_NAUD_VAL;
907 } else
908 n_val = had_calculate_n_value(aud_samp_freq);
5dab11d8
JA
909
910 if (n_val < 0)
911 return n_val;
912
79dda75a 913 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
5dab11d8
JA
914 *n_param = n_val;
915 return 0;
916}
917
372d855f 918static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
5dab11d8 919{
79f439ea 920 u32 hdmi_status = 0, i = 0;
5dab11d8
JA
921
922 /* Handle Underrun interrupt within Audio Unit */
79dda75a 923 had_write_register(intelhaddata, AUD_CONFIG, 0);
5dab11d8 924 /* Reset buffer pointers */
4151ee84
TI
925 had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
926 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
2e52f5e5 927 /*
5dab11d8
JA
928 * The interrupt status 'sticky' bits might not be cleared by
929 * setting '1' to that bit once...
930 */
931 do { /* clear bit30, 31 AUD_HDMI_STATUS */
4151ee84 932 had_read_register(intelhaddata, AUD_HDMI_STATUS,
79dda75a 933 &hdmi_status);
c75b0476 934 dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
5dab11d8
JA
935 if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
936 i++;
79dda75a 937 had_write_register(intelhaddata,
4151ee84 938 AUD_HDMI_STATUS, hdmi_status);
5dab11d8
JA
939 } else
940 break;
941 } while (i < MAX_CNT);
942 if (i >= MAX_CNT)
c75b0476 943 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
5dab11d8
JA
944}
945
2e52f5e5 946/*
5dab11d8
JA
947 * snd_intelhad_open - stream initializations are done here
948 * @substream:substream for which the stream function is called
949 *
950 * This function is called whenever a PCM stream is opened
951 */
952static int snd_intelhad_open(struct snd_pcm_substream *substream)
953{
954 struct snd_intelhad *intelhaddata;
955 struct snd_pcm_runtime *runtime;
956 struct had_stream_pvt *stream;
5647aec2 957 struct had_stream_data *had_stream;
5dab11d8
JA
958 int retval;
959
5dab11d8 960 intelhaddata = snd_pcm_substream_chip(substream);
5647aec2 961 had_stream = &intelhaddata->stream_data;
5dab11d8 962 runtime = substream->runtime;
6ddb3ab6 963 intelhaddata->underrun_count = 0;
5dab11d8
JA
964
965 pm_runtime_get(intelhaddata->dev);
966
79f439ea 967 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI
968 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
969 __func__);
5dab11d8
JA
970 retval = -ENODEV;
971 goto exit_put_handle;
972 }
973
974 /* Check, if device already in use */
975 if (runtime->private_data) {
c75b0476 976 dev_dbg(intelhaddata->dev, "Device already in use\n");
5dab11d8
JA
977 retval = -EBUSY;
978 goto exit_put_handle;
979 }
980
981 /* set the runtime hw parameter with local snd_pcm_hardware struct */
982 runtime->hw = snd_intel_hadstream;
983
984 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
985 if (!stream) {
986 retval = -ENOMEM;
987 goto exit_put_handle;
988 }
989 stream->stream_status = STREAM_INIT;
990 runtime->private_data = stream;
991
992 retval = snd_pcm_hw_constraint_integer(runtime,
993 SNDRV_PCM_HW_PARAM_PERIODS);
994 if (retval < 0)
995 goto exit_err;
996
997 /* Make sure, that the period size is always aligned
998 * 64byte boundary
999 */
1000 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1001 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1002 if (retval < 0) {
c75b0476
TI
1003 dev_dbg(intelhaddata->dev, "%s:step_size=64 failed,err=%d\n",
1004 __func__, retval);
5dab11d8
JA
1005 goto exit_err;
1006 }
1007
1008 return retval;
1009exit_err:
1010 kfree(stream);
1011exit_put_handle:
1012 pm_runtime_put(intelhaddata->dev);
1013 runtime->private_data = NULL;
1014 return retval;
1015}
1016
df76df12 1017/*
5dab11d8 1018 * had_period_elapsed - updates the hardware pointer status
df76df12 1019 * @had_substream: substream for which the stream function is called
5dab11d8 1020 */
df76df12 1021static void had_period_elapsed(struct snd_pcm_substream *substream)
5dab11d8 1022{
5dab11d8
JA
1023 struct had_stream_pvt *stream;
1024
5dab11d8
JA
1025 if (!substream || !substream->runtime)
1026 return;
1027 stream = substream->runtime->private_data;
1028 if (!stream)
1029 return;
1030
1031 if (stream->stream_status != STREAM_RUNNING)
1032 return;
1033 snd_pcm_period_elapsed(substream);
1034}
1035
2e52f5e5
TI
1036/*
1037 * snd_intelhad_close - to free parameteres when stream is stopped
5dab11d8
JA
1038 * @substream: substream for which the function is called
1039 *
1040 * This function is called by ALSA framework when stream is stopped
1041 */
1042static int snd_intelhad_close(struct snd_pcm_substream *substream)
1043{
1044 struct snd_intelhad *intelhaddata;
1045 struct snd_pcm_runtime *runtime;
1046
5dab11d8
JA
1047 intelhaddata = snd_pcm_substream_chip(substream);
1048 runtime = substream->runtime;
1049
c75b0476 1050 if (WARN_ON(!runtime->private_data))
5dab11d8 1051 return 0;
5dab11d8
JA
1052
1053 intelhaddata->stream_info.buffer_rendered = 0;
1054 intelhaddata->stream_info.buffer_ptr = 0;
1055 intelhaddata->stream_info.str_id = 0;
1056 intelhaddata->stream_info.had_substream = NULL;
1057
1058 /* Check if following drv_status modification is required - VA */
1059 if (intelhaddata->drv_status != HAD_DRV_DISCONNECTED) {
1060 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI
1061 dev_dbg(intelhaddata->dev,
1062 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
5dab11d8
JA
1063 __func__, __LINE__);
1064 }
1065 kfree(runtime->private_data);
1066 runtime->private_data = NULL;
1067 pm_runtime_put(intelhaddata->dev);
1068 return 0;
1069}
1070
2e52f5e5
TI
1071/*
1072 * snd_intelhad_hw_params - to setup the hardware parameters
1073 * like allocating the buffers
1074 * @substream: substream for which the function is called
5dab11d8
JA
1075 * @hw_params: hardware parameters
1076 *
1077 * This function is called by ALSA framework when hardware params are set
1078 */
1079static int snd_intelhad_hw_params(struct snd_pcm_substream *substream,
1080 struct snd_pcm_hw_params *hw_params)
1081{
c75b0476 1082 struct snd_intelhad *intelhaddata;
5dab11d8
JA
1083 unsigned long addr;
1084 int pages, buf_size, retval;
1085
5dab11d8
JA
1086 if (!hw_params)
1087 return -EINVAL;
1088
c75b0476 1089 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA
1090 buf_size = params_buffer_bytes(hw_params);
1091 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1092 if (retval < 0)
1093 return retval;
c75b0476
TI
1094 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1095 __func__, buf_size);
5dab11d8
JA
1096 /* mark the pages as uncached region */
1097 addr = (unsigned long) substream->runtime->dma_area;
1098 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1099 retval = set_memory_uc(addr, pages);
1100 if (retval) {
c75b0476
TI
1101 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1102 retval);
5dab11d8
JA
1103 return retval;
1104 }
1105 memset(substream->runtime->dma_area, 0, buf_size);
1106
1107 return retval;
1108}
1109
2e52f5e5
TI
1110/*
1111 * snd_intelhad_hw_free - to release the resources allocated during
1112 * hardware params setup
5dab11d8
JA
1113 * @substream: substream for which the function is called
1114 *
1115 * This function is called by ALSA framework before close callback.
5dab11d8
JA
1116 */
1117static int snd_intelhad_hw_free(struct snd_pcm_substream *substream)
1118{
1119 unsigned long addr;
1120 u32 pages;
1121
5dab11d8
JA
1122 /* mark back the pages as cached/writeback region before the free */
1123 if (substream->runtime->dma_area != NULL) {
1124 addr = (unsigned long) substream->runtime->dma_area;
1125 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1126 PAGE_SIZE;
1127 set_memory_wb(addr, pages);
1128 return snd_pcm_lib_free_pages(substream);
1129 }
1130 return 0;
1131}
1132
2e52f5e5 1133/*
5dab11d8 1134 * snd_intelhad_pcm_trigger - stream activities are handled here
2e52f5e5
TI
1135 * @substream: substream for which the stream function is called
1136 * @cmd: the stream commamd thats requested from upper layer
1137 *
5dab11d8
JA
1138 * This function is called whenever an a stream activity is invoked
1139 */
1140static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream,
1141 int cmd)
1142{
da864809 1143 int retval = 0;
5dab11d8
JA
1144 struct snd_intelhad *intelhaddata;
1145 struct had_stream_pvt *stream;
5647aec2 1146 struct had_stream_data *had_stream;
5dab11d8 1147
5dab11d8
JA
1148 intelhaddata = snd_pcm_substream_chip(substream);
1149 stream = substream->runtime->private_data;
5647aec2 1150 had_stream = &intelhaddata->stream_data;
5dab11d8
JA
1151
1152 switch (cmd) {
1153 case SNDRV_PCM_TRIGGER_START:
5dab11d8 1154 /* Disable local INTRs till register prgmng is done */
79f439ea 1155 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI
1156 dev_dbg(intelhaddata->dev,
1157 "_START: HDMI cable plugged-out\n");
5dab11d8
JA
1158 retval = -ENODEV;
1159 break;
1160 }
1161 stream->stream_status = STREAM_RUNNING;
1162
1163 had_stream->stream_type = HAD_RUNNING_STREAM;
1164
1165 /* Enable Audio */
da864809
TI
1166 snd_intelhad_enable_audio_int(intelhaddata, true);
1167 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA
1168 break;
1169
1170 case SNDRV_PCM_TRIGGER_STOP:
bcce775c 1171 spin_lock(&intelhaddata->had_spinlock);
5dab11d8
JA
1172 intelhaddata->stream_info.str_id = 0;
1173 intelhaddata->curr_buf = 0;
1174
c75b0476 1175 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
5dab11d8
JA
1176
1177 had_stream->stream_type = HAD_INIT;
bcce775c 1178 spin_unlock(&intelhaddata->had_spinlock);
5dab11d8 1179 /* Disable Audio */
da864809
TI
1180 snd_intelhad_enable_audio_int(intelhaddata, false);
1181 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8 1182 /* Reset buffer pointers */
79dda75a
TI
1183 snd_intelhad_reset_audio(intelhaddata, 1);
1184 snd_intelhad_reset_audio(intelhaddata, 0);
5dab11d8 1185 stream->stream_status = STREAM_DROPPED;
da864809 1186 snd_intelhad_enable_audio_int(intelhaddata, false);
5dab11d8
JA
1187 break;
1188
1189 default:
1190 retval = -EINVAL;
1191 }
1192 return retval;
1193}
1194
2e52f5e5
TI
1195/*
1196 * snd_intelhad_pcm_prepare - internal preparation before starting a stream
1197 * @substream: substream for which the function is called
5dab11d8
JA
1198 *
1199 * This function is called when a stream is started for internal preparation.
1200 */
1201static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
1202{
1203 int retval;
1204 u32 disp_samp_freq, n_param;
964ca808 1205 u32 link_rate = 0;
5dab11d8
JA
1206 struct snd_intelhad *intelhaddata;
1207 struct snd_pcm_runtime *runtime;
5647aec2 1208 struct had_stream_data *had_stream;
5dab11d8 1209
5dab11d8
JA
1210 intelhaddata = snd_pcm_substream_chip(substream);
1211 runtime = substream->runtime;
5647aec2 1212 had_stream = &intelhaddata->stream_data;
5dab11d8 1213
79f439ea 1214 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI
1215 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1216 __func__);
5dab11d8
JA
1217 retval = -ENODEV;
1218 goto prep_end;
1219 }
1220
c75b0476 1221 dev_dbg(intelhaddata->dev, "period_size=%d\n",
5dab11d8 1222 (int)frames_to_bytes(runtime, runtime->period_size));
c75b0476
TI
1223 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1224 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1225 (int)snd_pcm_lib_buffer_bytes(substream));
1226 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1227 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
5dab11d8
JA
1228
1229 if (intelhaddata->stream_info.str_id) {
c75b0476
TI
1230 dev_dbg(intelhaddata->dev,
1231 "_prepare is called for existing str_id#%d\n",
5dab11d8
JA
1232 intelhaddata->stream_info.str_id);
1233 retval = snd_intelhad_pcm_trigger(substream,
1234 SNDRV_PCM_TRIGGER_STOP);
1235 return retval;
1236 }
1237
2e52f5e5
TI
1238 intelhaddata->stream_info.had_substream = substream;
1239 intelhaddata->stream_info.buffer_ptr = 0;
1240 intelhaddata->stream_info.buffer_rendered = 0;
1241 intelhaddata->stream_info.sfreq = substream->runtime->rate;
5dab11d8
JA
1242
1243 /* Get N value in KHz */
da864809 1244 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1245
76296ef0
TI
1246 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1247 intelhaddata);
5dab11d8 1248 if (retval) {
c75b0476
TI
1249 dev_err(intelhaddata->dev,
1250 "programming N value failed %#x\n", retval);
5dab11d8
JA
1251 goto prep_end;
1252 }
964ca808
PLB
1253
1254 if (intelhaddata->dp_output)
da864809 1255 link_rate = intelhaddata->link_rate;
964ca808 1256
76296ef0
TI
1257 snd_intelhad_prog_cts(substream->runtime->rate,
1258 disp_samp_freq, link_rate,
1259 n_param, intelhaddata);
5dab11d8 1260
76296ef0 1261 snd_intelhad_prog_dip(substream, intelhaddata);
5dab11d8 1262
76296ef0 1263 retval = snd_intelhad_audio_ctrl(substream, intelhaddata);
5dab11d8
JA
1264
1265 /* Prog buffer address */
1266 retval = snd_intelhad_prog_buffer(intelhaddata,
1267 HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
1268
1269 /*
1270 * Program channel mapping in following order:
1271 * FL, FR, C, LFE, RL, RR
1272 */
1273
79dda75a 1274 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
5dab11d8
JA
1275
1276prep_end:
1277 return retval;
1278}
1279
2e52f5e5 1280/*
5dab11d8 1281 * snd_intelhad_pcm_pointer- to send the current buffer pointerprocessed by hw
2e52f5e5 1282 * @substream: substream for which the function is called
5dab11d8
JA
1283 *
1284 * This function is called by ALSA framework to get the current hw buffer ptr
1285 * when a period is elapsed
1286 */
1287static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
1288 struct snd_pcm_substream *substream)
1289{
1290 struct snd_intelhad *intelhaddata;
1291 u32 bytes_rendered = 0;
1292 u32 t;
1293 int buf_id;
1294
5dab11d8
JA
1295 intelhaddata = snd_pcm_substream_chip(substream);
1296
79f439ea
TI
1297 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
1298 return SNDRV_PCM_POS_XRUN;
1299
5dab11d8
JA
1300 /* Use a hw register to calculate sub-period position reports.
1301 * This makes PulseAudio happier.
1302 */
1303
1304 buf_id = intelhaddata->curr_buf % 4;
79dda75a
TI
1305 had_read_register(intelhaddata,
1306 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
232892fb
JA
1307
1308 if ((t == 0) || (t == ((u32)-1L))) {
6ddb3ab6 1309 intelhaddata->underrun_count++;
c75b0476
TI
1310 dev_dbg(intelhaddata->dev,
1311 "discovered buffer done for buf %d, count = %d\n",
6ddb3ab6 1312 buf_id, intelhaddata->underrun_count);
232892fb 1313
6ddb3ab6 1314 if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
c75b0476
TI
1315 dev_dbg(intelhaddata->dev,
1316 "assume audio_codec_reset, underrun = %d - do xrun\n",
6ddb3ab6
TI
1317 intelhaddata->underrun_count);
1318 intelhaddata->underrun_count = 0;
232892fb
JA
1319 return SNDRV_PCM_POS_XRUN;
1320 }
1321 } else {
1322 /* Reset Counter */
6ddb3ab6 1323 intelhaddata->underrun_count = 0;
5dab11d8 1324 }
232892fb 1325
5dab11d8
JA
1326 t = intelhaddata->buf_info[buf_id].buf_size - t;
1327
1328 if (intelhaddata->stream_info.buffer_rendered)
1329 div_u64_rem(intelhaddata->stream_info.buffer_rendered,
1330 intelhaddata->stream_info.ring_buf_size,
1331 &(bytes_rendered));
1332
1333 intelhaddata->stream_info.buffer_ptr = bytes_to_frames(
1334 substream->runtime,
1335 bytes_rendered + t);
1336 return intelhaddata->stream_info.buffer_ptr;
1337}
1338
2e52f5e5 1339/*
5dab11d8 1340 * snd_intelhad_pcm_mmap- mmaps a kernel buffer to user space for copying data
2e52f5e5
TI
1341 * @substream: substream for which the function is called
1342 * @vma: struct instance of memory VMM memory area
5dab11d8
JA
1343 *
1344 * This function is called by OS when a user space component
1345 * tries to get mmap memory from driver
1346 */
1347static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream,
1348 struct vm_area_struct *vma)
1349{
5dab11d8
JA
1350 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1351 return remap_pfn_range(vma, vma->vm_start,
1352 substream->dma_buffer.addr >> PAGE_SHIFT,
1353 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1354}
1355
8f8d1d7f 1356/* process mode change of the running stream; called in mutex */
da864809 1357static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata)
5dab11d8 1358{
da864809 1359 struct snd_pcm_substream *substream;
5dab11d8
JA
1360 int retval = 0;
1361 u32 disp_samp_freq, n_param;
964ca808 1362 u32 link_rate = 0;
5dab11d8 1363
da864809
TI
1364 substream = intelhaddata->stream_info.had_substream;
1365 if (!substream || !substream->runtime)
1366 return 0;
5dab11d8
JA
1367
1368 /* Disable Audio */
da864809 1369 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8
JA
1370
1371 /* Update CTS value */
da864809 1372 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1373
76296ef0
TI
1374 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1375 intelhaddata);
5dab11d8 1376 if (retval) {
c75b0476
TI
1377 dev_err(intelhaddata->dev,
1378 "programming N value failed %#x\n", retval);
5dab11d8
JA
1379 goto out;
1380 }
964ca808
PLB
1381
1382 if (intelhaddata->dp_output)
da864809 1383 link_rate = intelhaddata->link_rate;
964ca808 1384
76296ef0
TI
1385 snd_intelhad_prog_cts(substream->runtime->rate,
1386 disp_samp_freq, link_rate,
1387 n_param, intelhaddata);
5dab11d8
JA
1388
1389 /* Enable Audio */
da864809 1390 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA
1391
1392out:
1393 return retval;
1394}
1395
372d855f
TI
1396/*
1397 * hdmi_lpe_audio_suspend - power management suspend function
372d855f
TI
1398 * @pdev: platform device
1399 *
2e52f5e5 1400 * This function is called to suspend the hdmi audio.
372d855f
TI
1401 */
1402static int hdmi_lpe_audio_suspend(struct platform_device *pdev,
1403 pm_message_t state)
1404{
1405 struct had_stream_data *had_stream;
372d855f
TI
1406 struct snd_pcm_substream *substream;
1407 struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
1408
372d855f
TI
1409 had_stream = &intelhaddata->stream_data;
1410 substream = intelhaddata->stream_info.had_substream;
1411
e29c0f96 1412 if (!pm_runtime_status_suspended(intelhaddata->dev)) {
c75b0476 1413 dev_err(intelhaddata->dev, "audio stream is active\n");
372d855f
TI
1414 return -EAGAIN;
1415 }
1416
bcce775c 1417 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f 1418 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
bcce775c 1419 spin_unlock_irq(&intelhaddata->had_spinlock);
c75b0476 1420 dev_dbg(intelhaddata->dev, "had not connected\n");
372d855f
TI
1421 return 0;
1422 }
1423
1424 if (intelhaddata->drv_status == HAD_DRV_SUSPENDED) {
bcce775c 1425 spin_unlock_irq(&intelhaddata->had_spinlock);
c75b0476 1426 dev_dbg(intelhaddata->dev, "had already suspended\n");
372d855f
TI
1427 return 0;
1428 }
1429
1430 intelhaddata->drv_status = HAD_DRV_SUSPENDED;
c75b0476
TI
1431 dev_dbg(intelhaddata->dev,
1432 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_SUSPENDED\n",
372d855f
TI
1433 __func__, __LINE__);
1434
bcce775c 1435 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f 1436 snd_intelhad_enable_audio_int(intelhaddata, false);
372d855f
TI
1437 return 0;
1438}
1439
1440/*
1441 * hdmi_lpe_audio_resume - power management resume function
2e52f5e5 1442 * @pdev: platform device
372d855f 1443 *
2e52f5e5 1444 * This function is called to resume the hdmi audio.
372d855f
TI
1445 */
1446static int hdmi_lpe_audio_resume(struct platform_device *pdev)
1447{
1448 struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
372d855f 1449
bcce775c 1450 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f 1451 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
bcce775c 1452 spin_unlock_irq(&intelhaddata->had_spinlock);
c75b0476 1453 dev_dbg(intelhaddata->dev, "had not connected\n");
372d855f
TI
1454 return 0;
1455 }
1456
1457 if (intelhaddata->drv_status != HAD_DRV_SUSPENDED) {
bcce775c 1458 spin_unlock_irq(&intelhaddata->had_spinlock);
caa2a61a 1459 dev_dbg(intelhaddata->dev, "had is not in suspended state\n");
372d855f
TI
1460 return 0;
1461 }
1462
372d855f 1463 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI
1464 dev_dbg(intelhaddata->dev,
1465 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f 1466 __func__, __LINE__);
bcce775c 1467 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f 1468 snd_intelhad_enable_audio_int(intelhaddata, true);
372d855f
TI
1469 return 0;
1470}
1471
1472static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata,
1473 enum intel_had_aud_buf_type buf_id)
1474{
1475 int i, intr_count = 0;
1476 enum intel_had_aud_buf_type buff_done;
1477 u32 buf_size, buf_addr;
1478 struct had_stream_data *had_stream;
372d855f
TI
1479
1480 had_stream = &intelhaddata->stream_data;
1481
1482 buff_done = buf_id;
1483
1484 intr_count = snd_intelhad_read_len(intelhaddata);
1485 if (intr_count > 1) {
1486 /* In case of active playback */
c75b0476
TI
1487 dev_err(intelhaddata->dev,
1488 "Driver detected %d missed buffer done interrupt(s)\n",
1489 (intr_count - 1));
372d855f
TI
1490 if (intr_count > 3)
1491 return intr_count;
1492
1493 buf_id += (intr_count - 1);
1494 /* Reprogram registers*/
1495 for (i = buff_done; i < buf_id; i++) {
1496 int j = i % 4;
1497
1498 buf_size = intelhaddata->buf_info[j].buf_size;
1499 buf_addr = intelhaddata->buf_info[j].buf_addr;
1500 had_write_register(intelhaddata,
1501 AUD_BUF_A_LENGTH +
1502 (j * HAD_REG_WIDTH), buf_size);
1503 had_write_register(intelhaddata,
1504 AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH),
1505 (buf_addr | BIT(0) | BIT(1)));
1506 }
1507 buf_id = buf_id % 4;
372d855f 1508 intelhaddata->buff_done = buf_id;
372d855f
TI
1509 }
1510
1511 return intr_count;
1512}
1513
bcce775c 1514/* called from irq handler */
372d855f
TI
1515static int had_process_buffer_done(struct snd_intelhad *intelhaddata)
1516{
1517 u32 len = 1;
1518 enum intel_had_aud_buf_type buf_id;
1519 enum intel_had_aud_buf_type buff_done;
1520 struct pcm_stream_info *stream;
1521 u32 buf_size;
1522 struct had_stream_data *had_stream;
1523 int intr_count;
1524 enum had_status_stream stream_type;
bcce775c 1525 unsigned long flags;
372d855f
TI
1526
1527 had_stream = &intelhaddata->stream_data;
1528 stream = &intelhaddata->stream_info;
1529 intr_count = 1;
1530
bcce775c 1531 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
372d855f 1532 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
bcce775c 1533 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
c75b0476
TI
1534 dev_dbg(intelhaddata->dev,
1535 "%s:Device already disconnected\n", __func__);
372d855f
TI
1536 return 0;
1537 }
1538 buf_id = intelhaddata->curr_buf;
1539 intelhaddata->buff_done = buf_id;
1540 buff_done = intelhaddata->buff_done;
1541 buf_size = intelhaddata->buf_info[buf_id].buf_size;
1542 stream_type = had_stream->stream_type;
1543
372d855f
TI
1544 /* Every debug statement has an implication
1545 * of ~5msec. Thus, avoid having >3 debug statements
1546 * for each buffer_done handling.
1547 */
1548
1549 /* Check for any intr_miss in case of active playback */
1550 if (had_stream->stream_type == HAD_RUNNING_STREAM) {
372d855f
TI
1551 intr_count = had_chk_intrmiss(intelhaddata, buf_id);
1552 if (!intr_count || (intr_count > 3)) {
bcce775c
TI
1553 spin_unlock_irqrestore(&intelhaddata->had_spinlock,
1554 flags);
c75b0476
TI
1555 dev_err(intelhaddata->dev,
1556 "HAD SW state in non-recoverable mode\n");
372d855f
TI
1557 return 0;
1558 }
1559 buf_id += (intr_count - 1);
1560 buf_id = buf_id % 4;
372d855f
TI
1561 }
1562
1563 intelhaddata->buf_info[buf_id].is_valid = true;
1564 if (intelhaddata->valid_buf_cnt-1 == buf_id) {
1565 if (had_stream->stream_type >= HAD_RUNNING_STREAM)
1566 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1567 } else
1568 intelhaddata->curr_buf = buf_id + 1;
1569
bcce775c 1570 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
372d855f 1571
79f439ea 1572 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476 1573 dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n");
372d855f
TI
1574 return 0;
1575 }
1576
2e52f5e5 1577 /* Reprogram the registers with addr and length */
372d855f
TI
1578 had_write_register(intelhaddata,
1579 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1580 buf_size);
1581 had_write_register(intelhaddata,
1582 AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH),
1583 intelhaddata->buf_info[buf_id].buf_addr |
1584 BIT(0) | BIT(1));
1585
1586 had_read_register(intelhaddata,
1587 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1588 &len);
c75b0476 1589 dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id);
372d855f
TI
1590
1591 /* In case of actual data,
1592 * report buffer_done to above ALSA layer
1593 */
df76df12 1594 buf_size = intelhaddata->buf_info[buf_id].buf_size;
372d855f
TI
1595 if (stream_type >= HAD_RUNNING_STREAM) {
1596 intelhaddata->stream_info.buffer_rendered +=
1597 (intr_count * buf_size);
df76df12 1598 had_period_elapsed(stream->had_substream);
372d855f
TI
1599 }
1600
1601 return 0;
1602}
1603
bcce775c 1604/* called from irq handler */
372d855f
TI
1605static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1606{
1607 enum intel_had_aud_buf_type buf_id;
1608 struct pcm_stream_info *stream;
1609 struct had_stream_data *had_stream;
1610 enum had_status_stream stream_type;
bcce775c 1611 unsigned long flags;
372d855f
TI
1612 int drv_status;
1613
1614 had_stream = &intelhaddata->stream_data;
1615 stream = &intelhaddata->stream_info;
1616
bcce775c 1617 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
372d855f
TI
1618 buf_id = intelhaddata->curr_buf;
1619 stream_type = had_stream->stream_type;
1620 intelhaddata->buff_done = buf_id;
1621 drv_status = intelhaddata->drv_status;
1622 if (stream_type == HAD_RUNNING_STREAM)
1623 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1624
bcce775c 1625 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
372d855f 1626
c75b0476 1627 dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_type=%d\n",
372d855f
TI
1628 __func__, buf_id, stream_type);
1629
1630 snd_intelhad_handle_underrun(intelhaddata);
1631
1632 if (drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI
1633 dev_dbg(intelhaddata->dev,
1634 "%s:Device already disconnected\n", __func__);
372d855f
TI
1635 return 0;
1636 }
1637
1638 if (stream_type == HAD_RUNNING_STREAM) {
1639 /* Report UNDERRUN error to above layers */
d0e9b1a2 1640 snd_pcm_stop_xrun(stream->had_substream);
372d855f
TI
1641 }
1642
1643 return 0;
1644}
1645
8f8d1d7f 1646/* process hot plug, called from wq with mutex locked */
0e9c67d7 1647static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
372d855f
TI
1648{
1649 enum intel_had_aud_buf_type buf_id;
1650 struct snd_pcm_substream *substream;
1651 struct had_stream_data *had_stream;
372d855f 1652
372d855f
TI
1653 substream = intelhaddata->stream_info.had_substream;
1654 had_stream = &intelhaddata->stream_data;
1655
bcce775c 1656 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f 1657 if (intelhaddata->drv_status == HAD_DRV_CONNECTED) {
c75b0476 1658 dev_dbg(intelhaddata->dev, "Device already connected\n");
bcce775c 1659 spin_unlock_irq(&intelhaddata->had_spinlock);
0e9c67d7 1660 return;
372d855f 1661 }
0e9c67d7 1662
372d855f
TI
1663 buf_id = intelhaddata->curr_buf;
1664 intelhaddata->buff_done = buf_id;
1665 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI
1666 dev_dbg(intelhaddata->dev,
1667 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
372d855f 1668 __func__, __LINE__);
bcce775c 1669 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f 1670
c75b0476
TI
1671 dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n",
1672 buf_id);
372d855f
TI
1673
1674 /* Safety check */
1675 if (substream) {
c75b0476
TI
1676 dev_dbg(intelhaddata->dev,
1677 "Force to stop the active stream by disconnection\n");
372d855f
TI
1678 /* Set runtime->state to hw_params done */
1679 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1680 }
1681
1682 had_build_channel_allocation_map(intelhaddata);
372d855f
TI
1683}
1684
8f8d1d7f 1685/* process hot unplug, called from wq with mutex locked */
0e9c67d7 1686static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
372d855f
TI
1687{
1688 enum intel_had_aud_buf_type buf_id;
1689 struct had_stream_data *had_stream;
372d855f 1690
372d855f
TI
1691 had_stream = &intelhaddata->stream_data;
1692 buf_id = intelhaddata->curr_buf;
1693
bcce775c 1694 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f
TI
1695
1696 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476 1697 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
bcce775c 1698 spin_unlock_irq(&intelhaddata->had_spinlock);
0e9c67d7 1699 return;
372d855f 1700
372d855f
TI
1701 }
1702
0e9c67d7
TI
1703 /* Disable Audio */
1704 snd_intelhad_enable_audio_int(intelhaddata, false);
1705 snd_intelhad_enable_audio(intelhaddata, false);
1706
372d855f 1707 intelhaddata->drv_status = HAD_DRV_DISCONNECTED;
c75b0476
TI
1708 dev_dbg(intelhaddata->dev,
1709 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f
TI
1710 __func__, __LINE__);
1711
1712 /* Report to above ALSA layer */
1713 if (intelhaddata->stream_info.had_substream != NULL) {
bcce775c 1714 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f
TI
1715 snd_pcm_stop(intelhaddata->stream_info.had_substream,
1716 SNDRV_PCM_STATE_SETUP);
bcce775c 1717 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f
TI
1718 }
1719
1720 had_stream->stream_type = HAD_INIT;
bcce775c 1721 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f
TI
1722 kfree(intelhaddata->chmap->chmap);
1723 intelhaddata->chmap->chmap = NULL;
372d855f
TI
1724}
1725
1726/* PCM operations structure and the calls back for the same */
1727static struct snd_pcm_ops snd_intelhad_playback_ops = {
5dab11d8
JA
1728 .open = snd_intelhad_open,
1729 .close = snd_intelhad_close,
1730 .ioctl = snd_pcm_lib_ioctl,
1731 .hw_params = snd_intelhad_hw_params,
1732 .hw_free = snd_intelhad_hw_free,
1733 .prepare = snd_intelhad_pcm_prepare,
1734 .trigger = snd_intelhad_pcm_trigger,
1735 .pointer = snd_intelhad_pcm_pointer,
1736 .mmap = snd_intelhad_pcm_mmap,
1737};
1738
5dab11d8
JA
1739static int had_iec958_info(struct snd_kcontrol *kcontrol,
1740 struct snd_ctl_elem_info *uinfo)
1741{
1742 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1743 uinfo->count = 1;
1744 return 0;
1745}
1746
1747static int had_iec958_get(struct snd_kcontrol *kcontrol,
1748 struct snd_ctl_elem_value *ucontrol)
1749{
1750 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1751
8f8d1d7f 1752 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA
1753 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1754 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1755 ucontrol->value.iec958.status[2] =
1756 (intelhaddata->aes_bits >> 16) & 0xff;
1757 ucontrol->value.iec958.status[3] =
1758 (intelhaddata->aes_bits >> 24) & 0xff;
8f8d1d7f 1759 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA
1760 return 0;
1761}
372d855f 1762
5dab11d8
JA
1763static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1764 struct snd_ctl_elem_value *ucontrol)
1765{
1766 ucontrol->value.iec958.status[0] = 0xff;
1767 ucontrol->value.iec958.status[1] = 0xff;
1768 ucontrol->value.iec958.status[2] = 0xff;
1769 ucontrol->value.iec958.status[3] = 0xff;
1770 return 0;
1771}
372d855f 1772
5dab11d8
JA
1773static int had_iec958_put(struct snd_kcontrol *kcontrol,
1774 struct snd_ctl_elem_value *ucontrol)
1775{
1776 unsigned int val;
1777 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
8f8d1d7f 1778 int changed = 0;
5dab11d8 1779
5dab11d8
JA
1780 val = (ucontrol->value.iec958.status[0] << 0) |
1781 (ucontrol->value.iec958.status[1] << 8) |
1782 (ucontrol->value.iec958.status[2] << 16) |
1783 (ucontrol->value.iec958.status[3] << 24);
8f8d1d7f 1784 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA
1785 if (intelhaddata->aes_bits != val) {
1786 intelhaddata->aes_bits = val;
8f8d1d7f 1787 changed = 1;
5dab11d8 1788 }
8f8d1d7f
TI
1789 mutex_unlock(&intelhaddata->mutex);
1790 return changed;
5dab11d8
JA
1791}
1792
1793static struct snd_kcontrol_new had_control_iec958_mask = {
1794 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1795 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1796 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1797 .info = had_iec958_info, /* shared */
1798 .get = had_iec958_mask_get,
1799};
1800
1801static struct snd_kcontrol_new had_control_iec958 = {
1802 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1803 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1804 .info = had_iec958_info,
1805 .get = had_iec958_get,
1806 .put = had_iec958_put
1807};
1808
da864809
TI
1809static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1810{
1811 struct snd_intelhad *ctx = dev_id;
1812 u32 audio_stat, audio_reg;
1813
4151ee84 1814 audio_reg = AUD_HDMI_STATUS;
da864809
TI
1815 mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
1816
1817 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1818 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1819 had_process_buffer_underrun(ctx);
1820 }
1821
1822 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1823 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1824 had_process_buffer_done(ctx);
1825 }
1826
1827 return IRQ_HANDLED;
1828}
1829
1830static void notify_audio_lpe(struct platform_device *pdev)
1831{
1832 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
da864809 1833
99b2ab9d
TI
1834 schedule_work(&ctx->hdmi_audio_wq);
1835}
da864809 1836
99b2ab9d
TI
1837static void had_audio_wq(struct work_struct *work)
1838{
1839 struct snd_intelhad *ctx =
1840 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1841 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
da864809 1842
8f8d1d7f 1843 mutex_lock(&ctx->mutex);
99b2ab9d
TI
1844 if (!pdata->hdmi_connected) {
1845 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1846 __func__);
0e9c67d7 1847 had_process_hot_unplug(ctx);
da864809
TI
1848 } else {
1849 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1850
0e9c67d7
TI
1851 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1852 __func__, eld->port_id, pdata->tmds_clock_speed);
1853
da864809
TI
1854 switch (eld->pipe_id) {
1855 case 0:
1856 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1857 break;
1858 case 1:
1859 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1860 break;
1861 case 2:
1862 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1863 break;
1864 default:
99b2ab9d 1865 dev_dbg(ctx->dev, "Invalid pipe %d\n",
da864809
TI
1866 eld->pipe_id);
1867 break;
1868 }
1869
1870 memcpy(&ctx->eld, eld->eld_data, sizeof(ctx->eld));
1871
0e9c67d7
TI
1872 ctx->dp_output = pdata->dp_output;
1873 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1874 ctx->link_rate = pdata->link_rate;
da864809 1875
0e9c67d7 1876 had_process_hot_plug(ctx);
da864809 1877
0e9c67d7
TI
1878 /* Process mode change if stream is active */
1879 if (ctx->stream_data.stream_type == HAD_RUNNING_STREAM)
1880 hdmi_audio_mode_change(ctx);
da864809 1881 }
8f8d1d7f 1882 mutex_unlock(&ctx->mutex);
da864809
TI
1883}
1884
1885/* release resources */
1886static void hdmi_lpe_audio_free(struct snd_card *card)
1887{
1888 struct snd_intelhad *ctx = card->private_data;
1889
99b2ab9d
TI
1890 cancel_work_sync(&ctx->hdmi_audio_wq);
1891
da864809
TI
1892 if (ctx->mmio_start)
1893 iounmap(ctx->mmio_start);
1894 if (ctx->irq >= 0)
1895 free_irq(ctx->irq, ctx);
1896}
1897
79dda75a 1898/*
da864809 1899 * hdmi_lpe_audio_probe - start bridge with i915
5dab11d8 1900 *
da864809 1901 * This function is called when the i915 driver creates the
2e52f5e5 1902 * hdmi-lpe-audio platform device.
5dab11d8 1903 */
da864809 1904static int hdmi_lpe_audio_probe(struct platform_device *pdev)
5dab11d8 1905{
5dab11d8 1906 struct snd_card *card;
da864809
TI
1907 struct snd_intelhad *ctx;
1908 struct snd_pcm *pcm;
1909 struct intel_hdmi_lpe_audio_pdata *pdata;
1910 int irq;
1911 struct resource *res_mmio;
1912 int ret;
da864809 1913
da864809
TI
1914 dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask);
1915
1916 pdata = pdev->dev.platform_data;
1917 if (!pdata) {
1918 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1919 return -EINVAL;
1920 }
5dab11d8 1921
da864809
TI
1922 /* get resources */
1923 irq = platform_get_irq(pdev, 0);
1924 if (irq < 0) {
1925 dev_err(&pdev->dev, "Could not get irq resource\n");
1926 return -ENODEV;
1927 }
1928
1929 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1930 if (!res_mmio) {
1931 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1932 return -ENXIO;
1933 }
5dab11d8 1934
5647aec2 1935 /* create a card instance with ALSA framework */
da864809
TI
1936 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1937 THIS_MODULE, sizeof(*ctx), &card);
1938 if (ret)
1939 return ret;
1940
1941 ctx = card->private_data;
1942 spin_lock_init(&ctx->had_spinlock);
8f8d1d7f 1943 mutex_init(&ctx->mutex);
da864809
TI
1944 ctx->drv_status = HAD_DRV_DISCONNECTED;
1945 ctx->dev = &pdev->dev;
1946 ctx->card = card;
da864809
TI
1947 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1948 strcpy(card->driver, INTEL_HAD);
1949 strcpy(card->shortname, INTEL_HAD);
1950
1951 ctx->irq = -1;
1952 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
99b2ab9d 1953 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
da864809
TI
1954
1955 card->private_free = hdmi_lpe_audio_free;
1956
1957 /* assume pipe A as default */
1958 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1959
1960 platform_set_drvdata(pdev, ctx);
1961
1962 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1963 __func__, (unsigned int)res_mmio->start,
1964 (unsigned int)res_mmio->end);
1965
1966 ctx->mmio_start = ioremap_nocache(res_mmio->start,
1967 (size_t)(resource_size(res_mmio)));
1968 if (!ctx->mmio_start) {
1969 dev_err(&pdev->dev, "Could not get ioremap\n");
1970 ret = -EACCES;
1971 goto err;
1972 }
5dab11d8 1973
da864809
TI
1974 /* setup interrupt handler */
1975 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1976 pdev->name, ctx);
1977 if (ret < 0) {
1978 dev_err(&pdev->dev, "request_irq failed\n");
1979 goto err;
1980 }
5dab11d8 1981
da864809
TI
1982 ctx->irq = irq;
1983
1984 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1985 MAX_CAP_STREAMS, &pcm);
1986 if (ret)
5dab11d8
JA
1987 goto err;
1988
1989 /* setup private data which can be retrieved when required */
da864809 1990 pcm->private_data = ctx;
5dab11d8
JA
1991 pcm->info_flags = 0;
1992 strncpy(pcm->name, card->shortname, strlen(card->shortname));
da864809 1993 /* setup the ops for playabck */
5dab11d8
JA
1994 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1995 &snd_intelhad_playback_ops);
1996 /* allocate dma pages for ALSA stream operations
1997 * memory allocated is based on size, not max value
1998 * thus using same argument for max & size
1999 */
da864809 2000 snd_pcm_lib_preallocate_pages_for_all(pcm,
5dab11d8
JA
2001 SNDRV_DMA_TYPE_DEV, NULL,
2002 HAD_MAX_BUFFER, HAD_MAX_BUFFER);
5dab11d8 2003
5dab11d8 2004 /* IEC958 controls */
da864809
TI
2005 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958_mask, ctx));
2006 if (ret < 0)
5dab11d8 2007 goto err;
da864809
TI
2008 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958, ctx));
2009 if (ret < 0)
5dab11d8
JA
2010 goto err;
2011
2012 init_channel_allocations();
2013
2014 /* Register channel map controls */
da864809
TI
2015 ret = had_register_chmap_ctls(ctx, pcm);
2016 if (ret < 0)
5dab11d8
JA
2017 goto err;
2018
da864809
TI
2019 ret = snd_card_register(card);
2020 if (ret)
36ec0d99
TI
2021 goto err;
2022
bcce775c 2023 spin_lock_irq(&pdata->lpe_audio_slock);
da864809 2024 pdata->notify_audio_lpe = notify_audio_lpe;
99b2ab9d 2025 pdata->notify_pending = false;
bcce775c 2026 spin_unlock_irq(&pdata->lpe_audio_slock);
da864809
TI
2027
2028 pm_runtime_set_active(&pdev->dev);
2029 pm_runtime_enable(&pdev->dev);
2030
99b2ab9d 2031 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
da864809 2032 schedule_work(&ctx->hdmi_audio_wq);
5dab11d8 2033
79dda75a 2034 return 0;
5647aec2 2035
5dab11d8
JA
2036err:
2037 snd_card_free(card);
da864809 2038 return ret;
5dab11d8
JA
2039}
2040
79dda75a 2041/*
da864809 2042 * hdmi_lpe_audio_remove - stop bridge with i915
5dab11d8 2043 *
2e52f5e5 2044 * This function is called when the platform device is destroyed.
5dab11d8 2045 */
da864809 2046static int hdmi_lpe_audio_remove(struct platform_device *pdev)
5dab11d8 2047{
da864809 2048 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
5dab11d8 2049
da864809
TI
2050 if (ctx->drv_status != HAD_DRV_DISCONNECTED)
2051 snd_intelhad_enable_audio_int(ctx, false);
2052 snd_card_free(ctx->card);
5dab11d8
JA
2053 return 0;
2054}
2055
da864809
TI
2056static struct platform_driver hdmi_lpe_audio_driver = {
2057 .driver = {
2058 .name = "hdmi-lpe-audio",
2059 },
2060 .probe = hdmi_lpe_audio_probe,
2061 .remove = hdmi_lpe_audio_remove,
2062 .suspend = hdmi_lpe_audio_suspend,
2063 .resume = hdmi_lpe_audio_resume
2064};
2065
2066module_platform_driver(hdmi_lpe_audio_driver);
2067MODULE_ALIAS("platform:hdmi_lpe_audio");
2068
5dab11d8
JA
2069MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
2070MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
2071MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
2072MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
2073MODULE_DESCRIPTION("Intel HDMI Audio driver");
2074MODULE_LICENSE("GPL v2");
2075MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");