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ALSA: x86: Flatten two abstraction layers
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5dab11d8
JA		 1/*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
24#define pr_fmt(fmt) "had: " fmt
25
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/slab.h>
29#include <linux/module.h>
da864809 30#include <linux/interrupt.h>
5dab11d8
JA		 31#include <linux/acpi.h>
32#include <asm/cacheflush.h>
33#include <sound/pcm.h>
34#include <sound/core.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/control.h>
38#include <sound/initval.h>
da864809 39#include <drm/intel_lpe_audio.h>
5dab11d8
JA		 40#include "intel_hdmi_audio.h"
41
5dab11d8
JA		 42/*standard module options for ALSA. This module supports only one card*/
43static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
44static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
5dab11d8
JA		 45
46module_param_named(index, hdmi_card_index, int, 0444);
47MODULE_PARM_DESC(index,
48 "Index value for INTEL Intel HDMI Audio controller.");
49module_param_named(id, hdmi_card_id, charp, 0444);
50MODULE_PARM_DESC(id,
51 "ID string for INTEL Intel HDMI Audio controller.");
52
53/*
54 * ELD SA bits in the CEA Speaker Allocation data block
55 */
56static int eld_speaker_allocation_bits[] = {
57 [0] = FL | FR,
58 [1] = LFE,
59 [2] = FC,
60 [3] = RL | RR,
61 [4] = RC,
62 [5] = FLC | FRC,
63 [6] = RLC | RRC,
64 /* the following are not defined in ELD yet */
65 [7] = 0,
66};
67
68/*
69 * This is an ordered list!
70 *
71 * The preceding ones have better chances to be selected by
72 * hdmi_channel_allocation().
73 */
74static struct cea_channel_speaker_allocation channel_allocations[] = {
75/* channel: 7 6 5 4 3 2 1 0 */
76{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
77 /* 2.1 */
78{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
79 /* Dolby Surround */
80{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
81 /* surround40 */
82{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
83 /* surround41 */
84{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
85 /* surround50 */
86{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
87 /* surround51 */
88{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
89 /* 6.1 */
90{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
91 /* surround71 */
92{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
93
94{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
95{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
96{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
97{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
98{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
99{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
100{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
101{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
102{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
103{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
104{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
105{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
106{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
107{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
108{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
109{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
110{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
111{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
112{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
113{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
114{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
115{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
116{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
117};
118
119static struct channel_map_table map_tables[] = {
120 { SNDRV_CHMAP_FL, 0x00, FL },
121 { SNDRV_CHMAP_FR, 0x01, FR },
122 { SNDRV_CHMAP_RL, 0x04, RL },
123 { SNDRV_CHMAP_RR, 0x05, RR },
124 { SNDRV_CHMAP_LFE, 0x02, LFE },
125 { SNDRV_CHMAP_FC, 0x03, FC },
126 { SNDRV_CHMAP_RLC, 0x06, RLC },
127 { SNDRV_CHMAP_RRC, 0x07, RRC },
128 {} /* terminator */
129};
130
131/* hardware capability structure */
132static const struct snd_pcm_hardware snd_intel_hadstream = {
133 .info = (SNDRV_PCM_INFO_INTERLEAVED |
134 SNDRV_PCM_INFO_DOUBLE |
135 SNDRV_PCM_INFO_MMAP|
136 SNDRV_PCM_INFO_MMAP_VALID |
137 SNDRV_PCM_INFO_BATCH),
138 .formats = (SNDRV_PCM_FMTBIT_S24 |
139 SNDRV_PCM_FMTBIT_U24),
140 .rates = SNDRV_PCM_RATE_32000 |
141 SNDRV_PCM_RATE_44100 |
142 SNDRV_PCM_RATE_48000 |
143 SNDRV_PCM_RATE_88200 |
144 SNDRV_PCM_RATE_96000 |
145 SNDRV_PCM_RATE_176400 |
146 SNDRV_PCM_RATE_192000,
147 .rate_min = HAD_MIN_RATE,
148 .rate_max = HAD_MAX_RATE,
149 .channels_min = HAD_MIN_CHANNEL,
150 .channels_max = HAD_MAX_CHANNEL,
151 .buffer_bytes_max = HAD_MAX_BUFFER,
152 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
153 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
154 .periods_min = HAD_MIN_PERIODS,
155 .periods_max = HAD_MAX_PERIODS,
156 .fifo_size = HAD_FIFO_SIZE,
157};
158
159/* Register access functions */
160
161int had_get_hwstate(struct snd_intelhad *intelhaddata)
162{
163 /* Check for device presence -SW state */
164 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
165 pr_debug("%s:Device not connected:%d\n", __func__,
166 intelhaddata->drv_status);
167 return -ENODEV;
168 }
169
170 return 0;
171}
172
da864809
TI		 173static inline void
174mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
5dab11d8 175{
da864809 176 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 177}
178
da864809
TI		 179static inline void
180mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
5dab11d8 181{
da864809 182 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 183}
184
79dda75a 185int had_read_register(struct snd_intelhad *intelhaddata, u32 offset, u32 *data)
5dab11d8
JA		 186{
187 int retval;
5dab11d8
JA		 188
189 retval = had_get_hwstate(intelhaddata);
da864809
TI		 190 if (retval)
191 return retval;
5dab11d8 192
da864809
TI		 193 mid_hdmi_audio_read(intelhaddata, offset, data);
194 return 0;
195}
196
197static void fixup_dp_config(struct snd_intelhad *intelhaddata,
198 u32 offset, u32 *data)
199{
200 if (intelhaddata->dp_output) {
201 if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
202 *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
203 }
5dab11d8
JA		 204}
205
79dda75a 206int had_write_register(struct snd_intelhad *intelhaddata, u32 offset, u32 data)
5dab11d8
JA		 207{
208 int retval;
5dab11d8
JA		 209
210 retval = had_get_hwstate(intelhaddata);
da864809
TI		 211 if (retval)
212 return retval;
5dab11d8 213
da864809
TI		 214 fixup_dp_config(intelhaddata, offset, &data);
215 mid_hdmi_audio_write(intelhaddata, offset, data);
216 return 0;
5dab11d8
JA		 217}
218
79dda75a
TI		 219int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
220 u32 data, u32 mask)
5dab11d8 221{
da864809 222 u32 val_tmp;
5dab11d8 223 int retval;
5dab11d8
JA		 224
225 retval = had_get_hwstate(intelhaddata);
da864809
TI		 226 if (retval)
227 return retval;
5dab11d8 228
da864809
TI		 229 mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
230 val_tmp &= ~mask;
231 val_tmp |= (data & mask);
232
233 fixup_dp_config(intelhaddata, offset, &val_tmp);
234 mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
235 return 0;
5dab11d8 236}
da864809
TI		 237
238/*
239 * function to read-modify AUD_CONFIG register on VLV2.
240 * The had_read_modify() function should not directly be used on VLV2 for
241 * updating AUD_CONFIG register.
5dab11d8
JA		 242 * This is because:
243 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
244 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
245 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
246 * register. This field should be 1xy binary for configuration with 6 or
247 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
248 * causes the "channels" field to be updated as 0xy binary resulting in
249 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
250 * appropriate value when doing read-modify of AUD_CONFIG register.
251 *
252 * @substream: the current substream or NULL if no active substream
253 * @data : data to be written
254 * @mask : mask
255 *
256 */
da864809 257static int had_read_modify_aud_config_v2(struct snd_intelhad *intelhaddata,
5dab11d8
JA		 258 u32 data, u32 mask)
259{
da864809 260 struct snd_pcm_substream *substream;
5dab11d8
JA		 261 union aud_cfg cfg_val = {.cfg_regval = 0};
262 u8 channels;
263
264 /*
265 * If substream is NULL, there is no active stream.
266 * In this case just set channels to 2
267 */
da864809
TI		 268 substream = intelhaddata->stream_info.had_substream;
269 if (substream && substream->runtime)
5dab11d8
JA		 270 channels = substream->runtime->channels;
271 else
272 channels = 2;
273 cfg_val.cfg_regx_v2.num_ch = channels - 2;
274
275 data = data | cfg_val.cfg_regval;
276 mask = mask | AUD_CONFIG_CH_MASK_V2;
277
278 pr_debug("%s : data = %x, mask =%x\n", __func__, data, mask);
279
79dda75a 280 return had_read_modify(intelhaddata, AUD_CONFIG, data, mask);
5dab11d8
JA		 281}
282
da864809
TI		 283void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
284{
285 u32 status_reg;
286
287 if (enable) {
288 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
289 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
290 mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS_v2, status_reg);
291 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
292 }
293}
294
295void snd_intelhad_enable_audio(struct snd_intelhad *intelhaddata,
296 bool enable)
5dab11d8 297{
da864809
TI		 298 had_read_modify_aud_config_v2(intelhaddata, enable ? BIT(0) : 0,
299 BIT(0));
5dab11d8
JA		 300}
301
79dda75a
TI		 302static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
303 u8 reset)
5dab11d8 304{
79dda75a 305 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, reset);
5dab11d8
JA		 306}
307
308/**
309 * initialize audio channel status registers
310 * This function is called in the prepare callback
311 */
312static int had_prog_status_reg(struct snd_pcm_substream *substream,
313 struct snd_intelhad *intelhaddata)
314{
315 union aud_cfg cfg_val = {.cfg_regval = 0};
316 union aud_ch_status_0 ch_stat0 = {.status_0_regval = 0};
317 union aud_ch_status_1 ch_stat1 = {.status_1_regval = 0};
318 int format;
319
320 pr_debug("Entry %s\n", __func__);
321
322 ch_stat0.status_0_regx.lpcm_id = (intelhaddata->aes_bits &
323 IEC958_AES0_NONAUDIO)>>1;
324 ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
325 IEC958_AES3_CON_CLOCK)>>4;
4812dcc4 326 cfg_val.cfg_regx_v2.val_bit = ch_stat0.status_0_regx.lpcm_id;
5dab11d8
JA		 327
328 switch (substream->runtime->rate) {
329 case AUD_SAMPLE_RATE_32:
330 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_32KHZ;
331 break;
332
333 case AUD_SAMPLE_RATE_44_1:
334 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_44KHZ;
335 break;
336 case AUD_SAMPLE_RATE_48:
337 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_48KHZ;
338 break;
339 case AUD_SAMPLE_RATE_88_2:
340 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_88KHZ;
341 break;
342 case AUD_SAMPLE_RATE_96:
343 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_96KHZ;
344 break;
345 case AUD_SAMPLE_RATE_176_4:
346 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_176KHZ;
347 break;
348 case AUD_SAMPLE_RATE_192:
349 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_192KHZ;
350 break;
351
352 default:
353 /* control should never come here */
354 return -EINVAL;
355 break;
356
357 }
79dda75a
TI		 358 had_write_register(intelhaddata,
359 AUD_CH_STATUS_0, ch_stat0.status_0_regval);
5dab11d8
JA		 360
361 format = substream->runtime->format;
362
363 if (format == SNDRV_PCM_FORMAT_S16_LE) {
364 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_20;
365 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_16BITS;
366 } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
367 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_24;
368 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_24BITS;
369 } else {
370 ch_stat1.status_1_regx.max_wrd_len = 0;
371 ch_stat1.status_1_regx.wrd_len = 0;
372 }
79dda75a
TI		 373 had_write_register(intelhaddata,
374 AUD_CH_STATUS_1, ch_stat1.status_1_regval);
5dab11d8
JA		 375 return 0;
376}
377
76296ef0 378/*
5dab11d8
JA		 379 * function to initialize audio
380 * registers and buffer confgiuration registers
381 * This function is called in the prepare callback
382 */
76296ef0
TI		 383static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
384 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 385{
386 union aud_cfg cfg_val = {.cfg_regval = 0};
387 union aud_buf_config buf_cfg = {.buf_cfgval = 0};
388 u8 channels;
389
390 had_prog_status_reg(substream, intelhaddata);
391
392 buf_cfg.buf_cfg_regx_v2.audio_fifo_watermark = FIFO_THRESHOLD;
393 buf_cfg.buf_cfg_regx_v2.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
394 buf_cfg.buf_cfg_regx_v2.aud_delay = 0;
79dda75a 395 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
5dab11d8
JA		 396
397 channels = substream->runtime->channels;
398 cfg_val.cfg_regx_v2.num_ch = channels - 2;
399 if (channels <= 2)
400 cfg_val.cfg_regx_v2.layout = LAYOUT0;
401 else
402 cfg_val.cfg_regx_v2.layout = LAYOUT1;
403
964ca808 404 cfg_val.cfg_regx_v2.val_bit = 1;
79dda75a 405 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.cfg_regval);
5dab11d8
JA		 406 return 0;
407}
408
5dab11d8
JA		 409/*
410 * Compute derived values in channel_allocations[].
411 */
412static void init_channel_allocations(void)
413{
414 int i, j;
415 struct cea_channel_speaker_allocation *p;
416
417 pr_debug("%s: Enter\n", __func__);
418
419 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
420 p = channel_allocations + i;
421 p->channels = 0;
422 p->spk_mask = 0;
423 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
424 if (p->speakers[j]) {
425 p->channels++;
426 p->spk_mask |= p->speakers[j];
427 }
428 }
429}
430
431/*
432 * The transformation takes two steps:
433 *
434 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
435 * spk_mask => (channel_allocations[]) => ai->CA
436 *
437 * TODO: it could select the wrong CA from multiple candidates.
438 */
439static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata,
440 int channels)
441{
442 int i;
443 int ca = 0;
444 int spk_mask = 0;
445
446 /*
447 * CA defaults to 0 for basic stereo audio
448 */
449 if (channels <= 2)
450 return 0;
451
452 /*
453 * expand ELD's speaker allocation mask
454 *
455 * ELD tells the speaker mask in a compact(paired) form,
456 * expand ELD's notions to match the ones used by Audio InfoFrame.
457 */
458
459 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 460 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
JA		 461 spk_mask |= eld_speaker_allocation_bits[i];
462 }
463
464 /* search for the first working match in the CA table */
465 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
466 if (channels == channel_allocations[i].channels &&
467 (spk_mask & channel_allocations[i].spk_mask) ==
468 channel_allocations[i].spk_mask) {
469 ca = channel_allocations[i].ca_index;
470 break;
471 }
472 }
473
474 pr_debug("HDMI: select CA 0x%x for %d\n", ca, channels);
475
476 return ca;
477}
478
479/* from speaker bit mask to ALSA API channel position */
480static int spk_to_chmap(int spk)
481{
482 struct channel_map_table *t = map_tables;
483
484 for (; t->map; t++) {
485 if (t->spk_mask == spk)
486 return t->map;
487 }
488 return 0;
489}
490
491void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
492{
493 int i = 0, c = 0;
494 int spk_mask = 0;
495 struct snd_pcm_chmap_elem *chmap;
496 u8 eld_high, eld_high_mask = 0xF0;
497 u8 high_msb;
498
499 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
500 if (chmap == NULL) {
501 intelhaddata->chmap->chmap = NULL;
502 return;
503 }
504
da864809
TI		 505 pr_debug("eld.speaker_allocation_block = %x\n",
506 intelhaddata->eld.speaker_allocation_block);
5dab11d8
JA		 507
508 /* WA: Fix the max channel supported to 8 */
509
510 /*
511 * Sink may support more than 8 channels, if eld_high has more than
512 * one bit set. SOC supports max 8 channels.
513 * Refer eld_speaker_allocation_bits, for sink speaker allocation
514 */
515
516 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
da864809 517 eld_high = intelhaddata->eld.speaker_allocation_block & eld_high_mask;
5dab11d8
JA		 518 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
519 /* eld_high & (eld_high-1): if more than 1 bit set */
520 /* 0x1F: 7 channels */
521 for (i = 1; i < 4; i++) {
522 high_msb = eld_high & (0x80 >> i);
523 if (high_msb) {
da864809 524 intelhaddata->eld.speaker_allocation_block &=
5dab11d8
JA		 525 high_msb | 0xF;
526 break;
527 }
528 }
529 }
530
531 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 532 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
JA		 533 spk_mask |= eld_speaker_allocation_bits[i];
534 }
535
536 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
537 if (spk_mask == channel_allocations[i].spk_mask) {
538 for (c = 0; c < channel_allocations[i].channels; c++) {
539 chmap->map[c] = spk_to_chmap(
540 channel_allocations[i].speakers[
541 (MAX_SPEAKERS - 1)-c]);
542 }
543 chmap->channels = channel_allocations[i].channels;
544 intelhaddata->chmap->chmap = chmap;
545 break;
546 }
547 }
548 if (i >= ARRAY_SIZE(channel_allocations)) {
549 intelhaddata->chmap->chmap = NULL;
550 kfree(chmap);
551 }
552}
553
554/*
555 * ALSA API channel-map control callbacks
556 */
557static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
558 struct snd_ctl_elem_info *uinfo)
559{
560 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
561 struct snd_intelhad *intelhaddata = info->private_data;
562
563 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
564 return -ENODEV;
565 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
566 uinfo->count = HAD_MAX_CHANNEL;
567 uinfo->value.integer.min = 0;
568 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
569 return 0;
570}
571
572static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
573 struct snd_ctl_elem_value *ucontrol)
574{
575 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
576 struct snd_intelhad *intelhaddata = info->private_data;
577 int i = 0;
578 const struct snd_pcm_chmap_elem *chmap;
579
580 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
581 return -ENODEV;
582 if (intelhaddata->chmap->chmap == NULL)
583 return -ENODATA;
584 chmap = intelhaddata->chmap->chmap;
585 for (i = 0; i < chmap->channels; i++) {
586 ucontrol->value.integer.value[i] = chmap->map[i];
587 pr_debug("chmap->map[%d] = %d\n", i, chmap->map[i]);
588 }
589
590 return 0;
591}
592
593static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
594 struct snd_pcm *pcm)
595{
596 int err = 0;
597
598 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
599 NULL, 0, (unsigned long)intelhaddata,
600 &intelhaddata->chmap);
601 if (err < 0)
602 return err;
603
604 intelhaddata->chmap->private_data = intelhaddata;
605 intelhaddata->kctl = intelhaddata->chmap->kctl;
606 intelhaddata->kctl->info = had_chmap_ctl_info;
607 intelhaddata->kctl->get = had_chmap_ctl_get;
608 intelhaddata->chmap->chmap = NULL;
609 return 0;
610}
611
76296ef0
TI		 612/*
613 * snd_intelhad_prog_dip - to initialize Data Island Packets registers
5dab11d8
JA		 614 *
615 * @substream:substream for which the prepare function is called
616 * @intelhaddata:substream private data
617 *
618 * This function is called in the prepare callback
619 */
76296ef0
TI		 620static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream,
621 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 622{
623 int i;
624 union aud_ctrl_st ctrl_state = {.ctrl_val = 0};
625 union aud_info_frame2 frame2 = {.fr2_val = 0};
626 union aud_info_frame3 frame3 = {.fr3_val = 0};
627 u8 checksum = 0;
964ca808 628 u32 info_frame;
5dab11d8
JA		 629 int channels;
630
631 channels = substream->runtime->channels;
632
79dda75a 633 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8 634
964ca808
PLB		 635 if (intelhaddata->dp_output) {
636 info_frame = DP_INFO_FRAME_WORD1;
637 frame2.fr2_val = 1;
638 } else {
639 info_frame = HDMI_INFO_FRAME_WORD1;
640 frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
5dab11d8 641
964ca808
PLB		 642 frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
643 intelhaddata, channels);
5dab11d8 644
964ca808
PLB		 645 /*Calculte the byte wide checksum for all valid DIP words*/
646 for (i = 0; i < BYTES_PER_WORD; i++)
647 checksum += (info_frame >> i*BITS_PER_BYTE) & MASK_BYTE0;
648 for (i = 0; i < BYTES_PER_WORD; i++)
649 checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
650 for (i = 0; i < BYTES_PER_WORD; i++)
651 checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
5dab11d8 652
964ca808
PLB		 653 frame2.fr2_regx.chksum = -(checksum);
654 }
5dab11d8 655
79dda75a
TI		 656 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, info_frame);
657 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame2.fr2_val);
658 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame3.fr3_val);
5dab11d8
JA		 659
660 /* program remaining DIP words with zero */
661 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
79dda75a 662 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, 0x0);
5dab11d8
JA		 663
664 ctrl_state.ctrl_regx.dip_freq = 1;
665 ctrl_state.ctrl_regx.dip_en_sta = 1;
79dda75a 666 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8
JA		 667}
668
669/**
670 * snd_intelhad_prog_buffer - programs buffer
671 * address and length registers
672 *
673 * @substream:substream for which the prepare function is called
674 * @intelhaddata:substream private data
675 *
676 * This function programs ring buffer address and length into registers.
677 */
678int snd_intelhad_prog_buffer(struct snd_intelhad *intelhaddata,
679 int start, int end)
680{
681 u32 ring_buf_addr, ring_buf_size, period_bytes;
682 u8 i, num_periods;
683 struct snd_pcm_substream *substream;
684
685 substream = intelhaddata->stream_info.had_substream;
686 if (!substream) {
687 pr_err("substream is NULL\n");
688 dump_stack();
689 return 0;
690 }
691
692 ring_buf_addr = substream->runtime->dma_addr;
693 ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
694 intelhaddata->stream_info.ring_buf_size = ring_buf_size;
695 period_bytes = frames_to_bytes(substream->runtime,
696 substream->runtime->period_size);
697 num_periods = substream->runtime->periods;
698
699 /*
700 * buffer addr should be 64 byte aligned, period bytes
701 * will be used to calculate addr offset
702 */
703 period_bytes &= ~0x3F;
704
705 /* Hardware supports MAX_PERIODS buffers */
706 if (end >= HAD_MAX_PERIODS)
707 return -EINVAL;
708
709 for (i = start; i <= end; i++) {
710 /* Program the buf registers with addr and len */
711 intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
712 (i * period_bytes);
713 if (i < num_periods-1)
714 intelhaddata->buf_info[i].buf_size = period_bytes;
715 else
716 intelhaddata->buf_info[i].buf_size = ring_buf_size -
717 (period_bytes*i);
718
79dda75a
TI		 719 had_write_register(intelhaddata,
720 AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
5dab11d8
JA		 721 intelhaddata->buf_info[i].buf_addr |
722 BIT(0) | BIT(1));
79dda75a
TI		 723 had_write_register(intelhaddata,
724 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
5dab11d8
JA		 725 period_bytes);
726 intelhaddata->buf_info[i].is_valid = true;
727 }
728 pr_debug("%s:buf[%d-%d] addr=%#x and size=%d\n", __func__, start, end,
729 intelhaddata->buf_info[start].buf_addr,
730 intelhaddata->buf_info[start].buf_size);
731 intelhaddata->valid_buf_cnt = num_periods;
732 return 0;
733}
734
735int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
736{
737 int i, retval = 0;
738 u32 len[4];
739
740 for (i = 0; i < 4 ; i++) {
79dda75a
TI		 741 had_read_register(intelhaddata,
742 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
743 &len[i]);
5dab11d8
JA		 744 if (!len[i])
745 retval++;
746 }
747 if (retval != 1) {
748 for (i = 0; i < 4 ; i++)
749 pr_debug("buf[%d] size=%d\n", i, len[i]);
750 }
751
752 return retval;
753}
754
964ca808
PLB		 755static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
756{
757 u32 maud_val;
758
759 /* Select maud according to DP 1.2 spec*/
760 if (link_rate == DP_2_7_GHZ) {
761 switch (aud_samp_freq) {
762 case AUD_SAMPLE_RATE_32:
763 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
764 break;
765
766 case AUD_SAMPLE_RATE_44_1:
767 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
768 break;
769
770 case AUD_SAMPLE_RATE_48:
771 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
772 break;
773
774 case AUD_SAMPLE_RATE_88_2:
775 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
776 break;
777
778 case AUD_SAMPLE_RATE_96:
779 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
780 break;
781
782 case AUD_SAMPLE_RATE_176_4:
783 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
784 break;
785
786 case HAD_MAX_RATE:
787 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
788 break;
789
790 default:
791 maud_val = -EINVAL;
792 break;
793 }
794 } else if (link_rate == DP_1_62_GHZ) {
795 switch (aud_samp_freq) {
796 case AUD_SAMPLE_RATE_32:
797 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
798 break;
799
800 case AUD_SAMPLE_RATE_44_1:
801 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
802 break;
803
804 case AUD_SAMPLE_RATE_48:
805 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
806 break;
807
808 case AUD_SAMPLE_RATE_88_2:
809 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
810 break;
811
812 case AUD_SAMPLE_RATE_96:
813 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
814 break;
815
816 case AUD_SAMPLE_RATE_176_4:
817 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
818 break;
819
820 case HAD_MAX_RATE:
821 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
822 break;
823
824 default:
825 maud_val = -EINVAL;
826 break;
827 }
828 } else
829 maud_val = -EINVAL;
830
831 return maud_val;
832}
833
76296ef0
TI		 834/*
835 * snd_intelhad_prog_cts - Program HDMI audio CTS value
5dab11d8
JA		 836 *
837 * @aud_samp_freq: sampling frequency of audio data
838 * @tmds: sampling frequency of the display data
839 * @n_param: N value, depends on aud_samp_freq
840 * @intelhaddata:substream private data
841 *
842 * Program CTS register based on the audio and display sampling frequency
843 */
76296ef0
TI		 844static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds,
845 u32 link_rate, u32 n_param,
846 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 847{
848 u32 cts_val;
849 u64 dividend, divisor;
850
964ca808
PLB		 851 if (intelhaddata->dp_output) {
852 /* Substitute cts_val with Maud according to DP 1.2 spec*/
853 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
854 } else {
855 /* Calculate CTS according to HDMI 1.3a spec*/
856 dividend = (u64)tmds * n_param*1000;
857 divisor = 128 * aud_samp_freq;
858 cts_val = div64_u64(dividend, divisor);
859 }
5dab11d8 860 pr_debug("TMDS value=%d, N value=%d, CTS Value=%d\n",
964ca808 861 tmds, n_param, cts_val);
79dda75a 862 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
5dab11d8
JA		 863}
864
865static int had_calculate_n_value(u32 aud_samp_freq)
866{
867 s32 n_val;
868
869 /* Select N according to HDMI 1.3a spec*/
870 switch (aud_samp_freq) {
871 case AUD_SAMPLE_RATE_32:
872 n_val = 4096;
873 break;
874
875 case AUD_SAMPLE_RATE_44_1:
876 n_val = 6272;
877 break;
878
879 case AUD_SAMPLE_RATE_48:
880 n_val = 6144;
881 break;
882
883 case AUD_SAMPLE_RATE_88_2:
884 n_val = 12544;
885 break;
886
887 case AUD_SAMPLE_RATE_96:
888 n_val = 12288;
889 break;
890
891 case AUD_SAMPLE_RATE_176_4:
892 n_val = 25088;
893 break;
894
895 case HAD_MAX_RATE:
896 n_val = 24576;
897 break;
898
899 default:
900 n_val = -EINVAL;
901 break;
902 }
903 return n_val;
904}
905
76296ef0
TI		 906/*
907 * snd_intelhad_prog_n - Program HDMI audio N value
5dab11d8
JA		 908 *
909 * @aud_samp_freq: sampling frequency of audio data
910 * @n_param: N value, depends on aud_samp_freq
911 * @intelhaddata:substream private data
912 *
913 * This function is called in the prepare callback.
914 * It programs based on the audio and display sampling frequency
915 */
76296ef0
TI		 916static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param,
917 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 918{
919 s32 n_val;
920
964ca808
PLB		 921 if (intelhaddata->dp_output) {
922 /*
923 * According to DP specs, Maud and Naud values hold
924 * a relationship, which is stated as:
925 * Maud/Naud = 512 * fs / f_LS_Clk
926 * where, fs is the sampling frequency of the audio stream
927 * and Naud is 32768 for Async clock.
928 */
929
930 n_val = DP_NAUD_VAL;
931 } else
932 n_val = had_calculate_n_value(aud_samp_freq);
5dab11d8
JA		 933
934 if (n_val < 0)
935 return n_val;
936
79dda75a 937 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
5dab11d8
JA		 938 *n_param = n_val;
939 return 0;
940}
941
76296ef0 942void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 943{
944 u32 hdmi_status, i = 0;
945
946 /* Handle Underrun interrupt within Audio Unit */
79dda75a 947 had_write_register(intelhaddata, AUD_CONFIG, 0);
5dab11d8 948 /* Reset buffer pointers */
79dda75a
TI		 949 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 1);
950 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 0);
5dab11d8
JA		 951 /**
952 * The interrupt status 'sticky' bits might not be cleared by
953 * setting '1' to that bit once...
954 */
955 do { /* clear bit30, 31 AUD_HDMI_STATUS */
79dda75a
TI		 956 had_read_register(intelhaddata, AUD_HDMI_STATUS_v2,
957 &hdmi_status);
5dab11d8
JA		 958 pr_debug("HDMI status =0x%x\n", hdmi_status);
959 if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
960 i++;
79dda75a
TI		 961 had_write_register(intelhaddata,
962 AUD_HDMI_STATUS_v2, hdmi_status);
5dab11d8
JA		 963 } else
964 break;
965 } while (i < MAX_CNT);
966 if (i >= MAX_CNT)
967 pr_err("Unable to clear UNDERRUN bits\n");
968}
969
970/**
971 * snd_intelhad_open - stream initializations are done here
972 * @substream:substream for which the stream function is called
973 *
974 * This function is called whenever a PCM stream is opened
975 */
976static int snd_intelhad_open(struct snd_pcm_substream *substream)
977{
978 struct snd_intelhad *intelhaddata;
979 struct snd_pcm_runtime *runtime;
980 struct had_stream_pvt *stream;
5647aec2 981 struct had_stream_data *had_stream;
5dab11d8
JA		 982 int retval;
983
984 pr_debug("snd_intelhad_open called\n");
985 intelhaddata = snd_pcm_substream_chip(substream);
5647aec2 986 had_stream = &intelhaddata->stream_data;
5dab11d8 987 runtime = substream->runtime;
6ddb3ab6 988 intelhaddata->underrun_count = 0;
5dab11d8
JA		 989
990 pm_runtime_get(intelhaddata->dev);
991
992 if (had_get_hwstate(intelhaddata)) {
993 pr_err("%s: HDMI cable plugged-out\n", __func__);
994 retval = -ENODEV;
995 goto exit_put_handle;
996 }
997
998 /* Check, if device already in use */
999 if (runtime->private_data) {
1000 pr_err("Device already in use\n");
1001 retval = -EBUSY;
1002 goto exit_put_handle;
1003 }
1004
1005 /* set the runtime hw parameter with local snd_pcm_hardware struct */
1006 runtime->hw = snd_intel_hadstream;
1007
1008 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1009 if (!stream) {
1010 retval = -ENOMEM;
1011 goto exit_put_handle;
1012 }
1013 stream->stream_status = STREAM_INIT;
1014 runtime->private_data = stream;
1015
1016 retval = snd_pcm_hw_constraint_integer(runtime,
1017 SNDRV_PCM_HW_PARAM_PERIODS);
1018 if (retval < 0)
1019 goto exit_err;
1020
1021 /* Make sure, that the period size is always aligned
1022 * 64byte boundary
1023 */
1024 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1025 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1026 if (retval < 0) {
1027 pr_err("%s:step_size=64 failed,err=%d\n", __func__, retval);
1028 goto exit_err;
1029 }
1030
1031 return retval;
1032exit_err:
1033 kfree(stream);
1034exit_put_handle:
1035 pm_runtime_put(intelhaddata->dev);
1036 runtime->private_data = NULL;
1037 return retval;
1038}
1039
1040/**
1041 * had_period_elapsed - updates the hardware pointer status
1042 * @had_substream:substream for which the stream function is called
1043 *
1044 */
1045static void had_period_elapsed(void *had_substream)
1046{
1047 struct snd_pcm_substream *substream = had_substream;
1048 struct had_stream_pvt *stream;
1049
1050 /* pr_debug("had_period_elapsed called\n"); */
1051
1052 if (!substream || !substream->runtime)
1053 return;
1054 stream = substream->runtime->private_data;
1055 if (!stream)
1056 return;
1057
1058 if (stream->stream_status != STREAM_RUNNING)
1059 return;
1060 snd_pcm_period_elapsed(substream);
1061}
1062
1063/**
1064 * snd_intelhad_init_stream - internal function to initialize stream info
1065 * @substream:substream for which the stream function is called
1066 *
1067 */
1068static int snd_intelhad_init_stream(struct snd_pcm_substream *substream)
1069{
1070 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream);
1071
1072 pr_debug("snd_intelhad_init_stream called\n");
1073
1074 pr_debug("setting buffer ptr param\n");
1075 intelhaddata->stream_info.period_elapsed = had_period_elapsed;
1076 intelhaddata->stream_info.had_substream = substream;
1077 intelhaddata->stream_info.buffer_ptr = 0;
1078 intelhaddata->stream_info.buffer_rendered = 0;
1079 intelhaddata->stream_info.sfreq = substream->runtime->rate;
1080 return 0;
1081}
1082
1083/**
1084 * snd_intelhad_close- to free parameteres when stream is stopped
1085 *
1086 * @substream: substream for which the function is called
1087 *
1088 * This function is called by ALSA framework when stream is stopped
1089 */
1090static int snd_intelhad_close(struct snd_pcm_substream *substream)
1091{
1092 struct snd_intelhad *intelhaddata;
1093 struct snd_pcm_runtime *runtime;
1094
1095 pr_debug("snd_intelhad_close called\n");
1096
1097 intelhaddata = snd_pcm_substream_chip(substream);
1098 runtime = substream->runtime;
1099
1100 if (!runtime->private_data) {
1101 pr_debug("close() might have called after failed open");
1102 return 0;
1103 }
1104
1105 intelhaddata->stream_info.buffer_rendered = 0;
1106 intelhaddata->stream_info.buffer_ptr = 0;
1107 intelhaddata->stream_info.str_id = 0;
1108 intelhaddata->stream_info.had_substream = NULL;
1109
1110 /* Check if following drv_status modification is required - VA */
1111 if (intelhaddata->drv_status != HAD_DRV_DISCONNECTED) {
1112 intelhaddata->drv_status = HAD_DRV_CONNECTED;
1113 pr_debug("%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1114 __func__, __LINE__);
1115 }
1116 kfree(runtime->private_data);
1117 runtime->private_data = NULL;
1118 pm_runtime_put(intelhaddata->dev);
1119 return 0;
1120}
1121
1122/**
1123 * snd_intelhad_hw_params- to setup the hardware parameters
1124 * like allocating the buffers
1125 *
1126 * @substream: substream for which the function is called
1127 * @hw_params: hardware parameters
1128 *
1129 * This function is called by ALSA framework when hardware params are set
1130 */
1131static int snd_intelhad_hw_params(struct snd_pcm_substream *substream,
1132 struct snd_pcm_hw_params *hw_params)
1133{
1134 unsigned long addr;
1135 int pages, buf_size, retval;
1136
1137 pr_debug("snd_intelhad_hw_params called\n");
1138
1139 if (!hw_params)
1140 return -EINVAL;
1141
1142 buf_size = params_buffer_bytes(hw_params);
1143 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1144 if (retval < 0)
1145 return retval;
1146 pr_debug("%s:allocated memory = %d\n", __func__, buf_size);
1147 /* mark the pages as uncached region */
1148 addr = (unsigned long) substream->runtime->dma_area;
1149 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1150 retval = set_memory_uc(addr, pages);
1151 if (retval) {
1152 pr_err("set_memory_uc failed.Error:%d\n", retval);
1153 return retval;
1154 }
1155 memset(substream->runtime->dma_area, 0, buf_size);
1156
1157 return retval;
1158}
1159
1160/**
1161 * snd_intelhad_hw_free- to release the resources allocated during
1162 * hardware params setup
1163 *
1164 * @substream: substream for which the function is called
1165 *
1166 * This function is called by ALSA framework before close callback.
1167 *
1168 */
1169static int snd_intelhad_hw_free(struct snd_pcm_substream *substream)
1170{
1171 unsigned long addr;
1172 u32 pages;
1173
1174 pr_debug("snd_intelhad_hw_free called\n");
1175
1176 /* mark back the pages as cached/writeback region before the free */
1177 if (substream->runtime->dma_area != NULL) {
1178 addr = (unsigned long) substream->runtime->dma_area;
1179 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1180 PAGE_SIZE;
1181 set_memory_wb(addr, pages);
1182 return snd_pcm_lib_free_pages(substream);
1183 }
1184 return 0;
1185}
1186
1187/**
1188 * snd_intelhad_pcm_trigger - stream activities are handled here
1189 * @substream:substream for which the stream function is called
1190 * @cmd:the stream commamd thats requested from upper layer
1191 * This function is called whenever an a stream activity is invoked
1192 */
1193static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream,
1194 int cmd)
1195{
da864809 1196 int retval = 0;
5dab11d8
JA		 1197 unsigned long flag_irq;
1198 struct snd_intelhad *intelhaddata;
1199 struct had_stream_pvt *stream;
5647aec2 1200 struct had_stream_data *had_stream;
5dab11d8
JA		 1201
1202 pr_debug("snd_intelhad_pcm_trigger called\n");
1203
1204 intelhaddata = snd_pcm_substream_chip(substream);
1205 stream = substream->runtime->private_data;
5647aec2 1206 had_stream = &intelhaddata->stream_data;
5dab11d8
JA		 1207
1208 switch (cmd) {
1209 case SNDRV_PCM_TRIGGER_START:
1210 pr_debug("Trigger Start\n");
1211
1212 /* Disable local INTRs till register prgmng is done */
1213 if (had_get_hwstate(intelhaddata)) {
1214 pr_err("_START: HDMI cable plugged-out\n");
1215 retval = -ENODEV;
1216 break;
1217 }
1218 stream->stream_status = STREAM_RUNNING;
1219
1220 had_stream->stream_type = HAD_RUNNING_STREAM;
1221
1222 /* Enable Audio */
da864809
TI		 1223 snd_intelhad_enable_audio_int(intelhaddata, true);
1224 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA		 1225
1226 pr_debug("Processed _Start\n");
1227
1228 break;
1229
1230 case SNDRV_PCM_TRIGGER_STOP:
1231 pr_debug("Trigger Stop\n");
1232 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irq);
1233 intelhaddata->stream_info.str_id = 0;
1234 intelhaddata->curr_buf = 0;
1235
1236 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers*/
1237
1238 had_stream->stream_type = HAD_INIT;
1239 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irq);
1240 /* Disable Audio */
da864809
TI		 1241 snd_intelhad_enable_audio_int(intelhaddata, false);
1242 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8 1243 /* Reset buffer pointers */
79dda75a
TI		 1244 snd_intelhad_reset_audio(intelhaddata, 1);
1245 snd_intelhad_reset_audio(intelhaddata, 0);
5dab11d8 1246 stream->stream_status = STREAM_DROPPED;
da864809 1247 snd_intelhad_enable_audio_int(intelhaddata, false);
5dab11d8
JA		 1248 break;
1249
1250 default:
1251 retval = -EINVAL;
1252 }
1253 return retval;
1254}
1255
1256/**
1257 * snd_intelhad_pcm_prepare- internal preparation before starting a stream
1258 *
1259 * @substream: substream for which the function is called
1260 *
1261 * This function is called when a stream is started for internal preparation.
1262 */
1263static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
1264{
1265 int retval;
1266 u32 disp_samp_freq, n_param;
964ca808 1267 u32 link_rate = 0;
5dab11d8
JA		 1268 struct snd_intelhad *intelhaddata;
1269 struct snd_pcm_runtime *runtime;
5647aec2 1270 struct had_stream_data *had_stream;
5dab11d8
JA		 1271
1272 pr_debug("snd_intelhad_pcm_prepare called\n");
1273
1274 intelhaddata = snd_pcm_substream_chip(substream);
1275 runtime = substream->runtime;
5647aec2 1276 had_stream = &intelhaddata->stream_data;
5dab11d8
JA		 1277
1278 if (had_get_hwstate(intelhaddata)) {
1279 pr_err("%s: HDMI cable plugged-out\n", __func__);
1280 retval = -ENODEV;
1281 goto prep_end;
1282 }
1283
1284 pr_debug("period_size=%d\n",
1285 (int)frames_to_bytes(runtime, runtime->period_size));
1286 pr_debug("periods=%d\n", runtime->periods);
1287 pr_debug("buffer_size=%d\n", (int)snd_pcm_lib_buffer_bytes(substream));
1288 pr_debug("rate=%d\n", runtime->rate);
1289 pr_debug("channels=%d\n", runtime->channels);
1290
1291 if (intelhaddata->stream_info.str_id) {
1292 pr_debug("_prepare is called for existing str_id#%d\n",
1293 intelhaddata->stream_info.str_id);
1294 retval = snd_intelhad_pcm_trigger(substream,
1295 SNDRV_PCM_TRIGGER_STOP);
1296 return retval;
1297 }
1298
1299 retval = snd_intelhad_init_stream(substream);
1300 if (retval)
1301 goto prep_end;
1302
1303
1304 /* Get N value in KHz */
da864809 1305 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1306
76296ef0
TI		 1307 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1308 intelhaddata);
5dab11d8
JA		 1309 if (retval) {
1310 pr_err("programming N value failed %#x\n", retval);
1311 goto prep_end;
1312 }
964ca808
PLB		 1313
1314 if (intelhaddata->dp_output)
da864809 1315 link_rate = intelhaddata->link_rate;
964ca808 1316
76296ef0
TI		 1317 snd_intelhad_prog_cts(substream->runtime->rate,
1318 disp_samp_freq, link_rate,
1319 n_param, intelhaddata);
5dab11d8 1320
76296ef0 1321 snd_intelhad_prog_dip(substream, intelhaddata);
5dab11d8 1322
76296ef0 1323 retval = snd_intelhad_audio_ctrl(substream, intelhaddata);
5dab11d8
JA		 1324
1325 /* Prog buffer address */
1326 retval = snd_intelhad_prog_buffer(intelhaddata,
1327 HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
1328
1329 /*
1330 * Program channel mapping in following order:
1331 * FL, FR, C, LFE, RL, RR
1332 */
1333
79dda75a 1334 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
5dab11d8
JA		 1335
1336prep_end:
1337 return retval;
1338}
1339
1340/**
1341 * snd_intelhad_pcm_pointer- to send the current buffer pointerprocessed by hw
1342 *
1343 * @substream: substream for which the function is called
1344 *
1345 * This function is called by ALSA framework to get the current hw buffer ptr
1346 * when a period is elapsed
1347 */
1348static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
1349 struct snd_pcm_substream *substream)
1350{
1351 struct snd_intelhad *intelhaddata;
1352 u32 bytes_rendered = 0;
1353 u32 t;
1354 int buf_id;
1355
1356 /* pr_debug("snd_intelhad_pcm_pointer called\n"); */
1357
1358 intelhaddata = snd_pcm_substream_chip(substream);
1359
1360 if (intelhaddata->flag_underrun) {
1361 intelhaddata->flag_underrun = 0;
1362 return SNDRV_PCM_POS_XRUN;
1363 }
1364
1365 /* Use a hw register to calculate sub-period position reports.
1366 * This makes PulseAudio happier.
1367 */
1368
1369 buf_id = intelhaddata->curr_buf % 4;
79dda75a
TI		 1370 had_read_register(intelhaddata,
1371 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
232892fb
JA		 1372
1373 if ((t == 0) || (t == ((u32)-1L))) {
6ddb3ab6 1374 intelhaddata->underrun_count++;
232892fb 1375 pr_debug("discovered buffer done for buf %d, count = %d\n",
6ddb3ab6 1376 buf_id, intelhaddata->underrun_count);
232892fb 1377
6ddb3ab6 1378 if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
232892fb 1379 pr_debug("assume audio_codec_reset, underrun = %d - do xrun\n",
6ddb3ab6
TI		 1380 intelhaddata->underrun_count);
1381 intelhaddata->underrun_count = 0;
232892fb
JA		 1382 return SNDRV_PCM_POS_XRUN;
1383 }
1384 } else {
1385 /* Reset Counter */
6ddb3ab6 1386 intelhaddata->underrun_count = 0;
5dab11d8 1387 }
232892fb 1388
5dab11d8
JA		 1389 t = intelhaddata->buf_info[buf_id].buf_size - t;
1390
1391 if (intelhaddata->stream_info.buffer_rendered)
1392 div_u64_rem(intelhaddata->stream_info.buffer_rendered,
1393 intelhaddata->stream_info.ring_buf_size,
1394 &(bytes_rendered));
1395
1396 intelhaddata->stream_info.buffer_ptr = bytes_to_frames(
1397 substream->runtime,
1398 bytes_rendered + t);
1399 return intelhaddata->stream_info.buffer_ptr;
1400}
1401
1402/**
1403 * snd_intelhad_pcm_mmap- mmaps a kernel buffer to user space for copying data
1404 *
1405 * @substream: substream for which the function is called
1406 * @vma: struct instance of memory VMM memory area
1407 *
1408 * This function is called by OS when a user space component
1409 * tries to get mmap memory from driver
1410 */
1411static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream,
1412 struct vm_area_struct *vma)
1413{
1414
1415 pr_debug("snd_intelhad_pcm_mmap called\n");
1416
1417 pr_debug("entry with prot:%s\n", __func__);
1418 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1419 return remap_pfn_range(vma, vma->vm_start,
1420 substream->dma_buffer.addr >> PAGE_SHIFT,
1421 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1422}
1423
da864809 1424static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata)
5dab11d8 1425{
da864809 1426 struct snd_pcm_substream *substream;
5dab11d8
JA		 1427 int retval = 0;
1428 u32 disp_samp_freq, n_param;
964ca808 1429 u32 link_rate = 0;
5dab11d8 1430
da864809
TI		 1431 substream = intelhaddata->stream_info.had_substream;
1432 if (!substream || !substream->runtime)
1433 return 0;
5dab11d8
JA		 1434
1435 /* Disable Audio */
da864809 1436 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8
JA		 1437
1438 /* Update CTS value */
da864809 1439 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1440
76296ef0
TI		 1441 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1442 intelhaddata);
5dab11d8
JA		 1443 if (retval) {
1444 pr_err("programming N value failed %#x\n", retval);
1445 goto out;
1446 }
964ca808
PLB		 1447
1448 if (intelhaddata->dp_output)
da864809 1449 link_rate = intelhaddata->link_rate;
964ca808 1450
76296ef0
TI		 1451 snd_intelhad_prog_cts(substream->runtime->rate,
1452 disp_samp_freq, link_rate,
1453 n_param, intelhaddata);
5dab11d8
JA		 1454
1455 /* Enable Audio */
da864809 1456 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA		 1457
1458out:
1459 return retval;
1460}
1461
1462/*PCM operations structure and the calls back for the same */
1463struct snd_pcm_ops snd_intelhad_playback_ops = {
1464 .open = snd_intelhad_open,
1465 .close = snd_intelhad_close,
1466 .ioctl = snd_pcm_lib_ioctl,
1467 .hw_params = snd_intelhad_hw_params,
1468 .hw_free = snd_intelhad_hw_free,
1469 .prepare = snd_intelhad_pcm_prepare,
1470 .trigger = snd_intelhad_pcm_trigger,
1471 .pointer = snd_intelhad_pcm_pointer,
1472 .mmap = snd_intelhad_pcm_mmap,
1473};
1474
5dab11d8
JA		 1475/**
1476 * snd_intelhad_pcm_free - to free the memory allocated
1477 *
1478 * @pcm: pointer to pcm instance
1479 * This function is called when the device is removed
1480 */
1481static void snd_intelhad_pcm_free(struct snd_pcm *pcm)
1482{
1483 pr_debug("Freeing PCM preallocated pages\n");
1484 snd_pcm_lib_preallocate_free_for_all(pcm);
1485}
1486
1487static int had_iec958_info(struct snd_kcontrol *kcontrol,
1488 struct snd_ctl_elem_info *uinfo)
1489{
1490 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1491 uinfo->count = 1;
1492 return 0;
1493}
1494
1495static int had_iec958_get(struct snd_kcontrol *kcontrol,
1496 struct snd_ctl_elem_value *ucontrol)
1497{
1498 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1499
1500 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1501 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1502 ucontrol->value.iec958.status[2] =
1503 (intelhaddata->aes_bits >> 16) & 0xff;
1504 ucontrol->value.iec958.status[3] =
1505 (intelhaddata->aes_bits >> 24) & 0xff;
1506 return 0;
1507}
1508static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1509 struct snd_ctl_elem_value *ucontrol)
1510{
1511 ucontrol->value.iec958.status[0] = 0xff;
1512 ucontrol->value.iec958.status[1] = 0xff;
1513 ucontrol->value.iec958.status[2] = 0xff;
1514 ucontrol->value.iec958.status[3] = 0xff;
1515 return 0;
1516}
1517static int had_iec958_put(struct snd_kcontrol *kcontrol,
1518 struct snd_ctl_elem_value *ucontrol)
1519{
1520 unsigned int val;
1521 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1522
1523 pr_debug("entered had_iec958_put\n");
1524 val = (ucontrol->value.iec958.status[0] << 0) |
1525 (ucontrol->value.iec958.status[1] << 8) |
1526 (ucontrol->value.iec958.status[2] << 16) |
1527 (ucontrol->value.iec958.status[3] << 24);
1528 if (intelhaddata->aes_bits != val) {
1529 intelhaddata->aes_bits = val;
1530 return 1;
1531 }
1532 return 1;
1533}
1534
1535static struct snd_kcontrol_new had_control_iec958_mask = {
1536 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1537 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1538 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1539 .info = had_iec958_info, /* shared */
1540 .get = had_iec958_mask_get,
1541};
1542
1543static struct snd_kcontrol_new had_control_iec958 = {
1544 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1545 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1546 .info = had_iec958_info,
1547 .get = had_iec958_get,
1548 .put = had_iec958_put
1549};
1550
da864809
TI		 1551static void _had_wq(struct work_struct *work)
1552{
1553 struct snd_intelhad *ctx =
1554 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1555
1556 had_process_hot_plug(ctx);
1557}
1558
1559static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1560{
1561 struct snd_intelhad *ctx = dev_id;
1562 u32 audio_stat, audio_reg;
1563
1564 audio_reg = AUD_HDMI_STATUS_v2;
1565 mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
1566
1567 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1568 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1569 had_process_buffer_underrun(ctx);
1570 }
1571
1572 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1573 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1574 had_process_buffer_done(ctx);
1575 }
1576
1577 return IRQ_HANDLED;
1578}
1579
1580static void notify_audio_lpe(struct platform_device *pdev)
1581{
1582 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1583 struct intel_hdmi_lpe_audio_pdata *pdata = pdev->dev.platform_data;
1584
1585 if (pdata->hdmi_connected != true) {
1586
1587 dev_dbg(&pdev->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1588 __func__);
1589
1590 if (ctx->state == hdmi_connector_status_connected) {
1591
1592 ctx->state = hdmi_connector_status_disconnected;
1593
1594 had_process_hot_unplug(ctx);
1595 } else
1596 dev_dbg(&pdev->dev, "%s: Already Unplugged!\n",
1597 __func__);
1598
1599 } else {
1600 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1601
1602 switch (eld->pipe_id) {
1603 case 0:
1604 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1605 break;
1606 case 1:
1607 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1608 break;
1609 case 2:
1610 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1611 break;
1612 default:
1613 dev_dbg(&pdev->dev, "Invalid pipe %d\n",
1614 eld->pipe_id);
1615 break;
1616 }
1617
1618 memcpy(&ctx->eld, eld->eld_data, sizeof(ctx->eld));
1619
1620 had_process_hot_plug(ctx);
1621
1622 ctx->state = hdmi_connector_status_connected;
1623
1624 dev_dbg(&pdev->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1625 __func__, eld->port_id, pdata->tmds_clock_speed);
1626
1627 if (pdata->tmds_clock_speed) {
1628 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1629 ctx->dp_output = pdata->dp_output;
1630 ctx->link_rate = pdata->link_rate;
1631
1632 /* Process mode change if stream is active */
1633 if (ctx->stream_data.stream_type == HAD_RUNNING_STREAM)
1634 hdmi_audio_mode_change(ctx);
1635 }
1636 }
1637}
1638
1639/* release resources */
1640static void hdmi_lpe_audio_free(struct snd_card *card)
1641{
1642 struct snd_intelhad *ctx = card->private_data;
1643
1644 if (ctx->mmio_start)
1645 iounmap(ctx->mmio_start);
1646 if (ctx->irq >= 0)
1647 free_irq(ctx->irq, ctx);
1648}
1649
79dda75a 1650/*
da864809 1651 * hdmi_lpe_audio_probe - start bridge with i915
5dab11d8 1652 *
da864809
TI		 1653 * This function is called when the i915 driver creates the
1654 * hdmi-lpe-audio platform device. Card creation is deferred until a
1655 * hot plug event is received
5dab11d8 1656 */
da864809 1657static int hdmi_lpe_audio_probe(struct platform_device *pdev)
5dab11d8 1658{
5dab11d8 1659 struct snd_card *card;
da864809
TI		 1660 struct snd_intelhad *ctx;
1661 struct snd_pcm *pcm;
1662 struct intel_hdmi_lpe_audio_pdata *pdata;
1663 int irq;
1664 struct resource *res_mmio;
1665 int ret;
1666 unsigned long flags;
1667
1668 dev_dbg(&pdev->dev, "Enter %s\n", __func__);
1669 dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask);
1670
1671 pdata = pdev->dev.platform_data;
1672 if (!pdata) {
1673 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1674 return -EINVAL;
1675 }
5dab11d8 1676
da864809
TI		 1677 /* get resources */
1678 irq = platform_get_irq(pdev, 0);
1679 if (irq < 0) {
1680 dev_err(&pdev->dev, "Could not get irq resource\n");
1681 return -ENODEV;
1682 }
1683
1684 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1685 if (!res_mmio) {
1686 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1687 return -ENXIO;
1688 }
5dab11d8 1689
5647aec2 1690 /* create a card instance with ALSA framework */
da864809
TI		 1691 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1692 THIS_MODULE, sizeof(*ctx), &card);
1693 if (ret)
1694 return ret;
1695
1696 ctx = card->private_data;
1697 spin_lock_init(&ctx->had_spinlock);
1698 ctx->drv_status = HAD_DRV_DISCONNECTED;
1699 ctx->dev = &pdev->dev;
1700 ctx->card = card;
1701 ctx->card_id = hdmi_card_id;
1702 ctx->card_index = card->number;
1703 ctx->flag_underrun = 0;
1704 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1705 strcpy(card->driver, INTEL_HAD);
1706 strcpy(card->shortname, INTEL_HAD);
1707
1708 ctx->irq = -1;
1709 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
1710 INIT_WORK(&ctx->hdmi_audio_wq, _had_wq);
1711 ctx->state = hdmi_connector_status_disconnected;
1712
1713 card->private_free = hdmi_lpe_audio_free;
1714
1715 /* assume pipe A as default */
1716 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1717
1718 platform_set_drvdata(pdev, ctx);
1719
1720 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1721 __func__, (unsigned int)res_mmio->start,
1722 (unsigned int)res_mmio->end);
1723
1724 ctx->mmio_start = ioremap_nocache(res_mmio->start,
1725 (size_t)(resource_size(res_mmio)));
1726 if (!ctx->mmio_start) {
1727 dev_err(&pdev->dev, "Could not get ioremap\n");
1728 ret = -EACCES;
1729 goto err;
1730 }
5dab11d8 1731
da864809
TI		 1732 /* setup interrupt handler */
1733 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1734 pdev->name, ctx);
1735 if (ret < 0) {
1736 dev_err(&pdev->dev, "request_irq failed\n");
1737 goto err;
1738 }
5dab11d8 1739
da864809
TI		 1740 ctx->irq = irq;
1741
1742 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1743 MAX_CAP_STREAMS, &pcm);
1744 if (ret)
5dab11d8
JA		 1745 goto err;
1746
1747 /* setup private data which can be retrieved when required */
da864809 1748 pcm->private_data = ctx;
5dab11d8
JA		 1749 pcm->private_free = snd_intelhad_pcm_free;
1750 pcm->info_flags = 0;
1751 strncpy(pcm->name, card->shortname, strlen(card->shortname));
da864809 1752 /* setup the ops for playabck */
5dab11d8
JA		 1753 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1754 &snd_intelhad_playback_ops);
1755 /* allocate dma pages for ALSA stream operations
1756 * memory allocated is based on size, not max value
1757 * thus using same argument for max & size
1758 */
da864809 1759 snd_pcm_lib_preallocate_pages_for_all(pcm,
5dab11d8
JA		 1760 SNDRV_DMA_TYPE_DEV, NULL,
1761 HAD_MAX_BUFFER, HAD_MAX_BUFFER);
5dab11d8 1762
5dab11d8 1763 /* IEC958 controls */
da864809
TI		 1764 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958_mask, ctx));
1765 if (ret < 0)
5dab11d8 1766 goto err;
da864809
TI		 1767 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958, ctx));
1768 if (ret < 0)
5dab11d8
JA		 1769 goto err;
1770
1771 init_channel_allocations();
1772
1773 /* Register channel map controls */
da864809
TI		 1774 ret = had_register_chmap_ctls(ctx, pcm);
1775 if (ret < 0)
5dab11d8
JA		 1776 goto err;
1777
da864809
TI		 1778 ret = snd_card_register(card);
1779 if (ret)
36ec0d99
TI		 1780 goto err;
1781
da864809
TI		 1782 spin_lock_irqsave(&pdata->lpe_audio_slock, flags);
1783 pdata->notify_audio_lpe = notify_audio_lpe;
1784 if (pdata->notify_pending) {
5dab11d8 1785
da864809
TI		 1786 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1787 notify_audio_lpe(pdev);
1788 pdata->notify_pending = false;
1789 }
1790 spin_unlock_irqrestore(&pdata->lpe_audio_slock, flags);
1791
1792 pm_runtime_set_active(&pdev->dev);
1793 pm_runtime_enable(&pdev->dev);
1794
1795 schedule_work(&ctx->hdmi_audio_wq);
5dab11d8 1796
79dda75a 1797 return 0;
5647aec2 1798
5dab11d8
JA		 1799err:
1800 snd_card_free(card);
da864809 1801 return ret;
5dab11d8
JA		 1802}
1803
79dda75a 1804/*
da864809 1805 * hdmi_lpe_audio_remove - stop bridge with i915
5dab11d8 1806 *
da864809
TI		 1807 * This function is called when the platform device is destroyed. The sound
1808 * card should have been removed on hot plug event.
5dab11d8 1809 */
da864809 1810static int hdmi_lpe_audio_remove(struct platform_device *pdev)
5dab11d8 1811{
da864809 1812 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
5dab11d8 1813
da864809 1814 dev_dbg(&pdev->dev, "Enter %s\n", __func__);
5dab11d8 1815
da864809
TI		 1816 if (ctx->drv_status != HAD_DRV_DISCONNECTED)
1817 snd_intelhad_enable_audio_int(ctx, false);
1818 snd_card_free(ctx->card);
5dab11d8
JA		 1819 return 0;
1820}
1821
da864809
TI		 1822static struct platform_driver hdmi_lpe_audio_driver = {
1823 .driver = {
1824 .name = "hdmi-lpe-audio",
1825 },
1826 .probe = hdmi_lpe_audio_probe,
1827 .remove = hdmi_lpe_audio_remove,
1828 .suspend = hdmi_lpe_audio_suspend,
1829 .resume = hdmi_lpe_audio_resume
1830};
1831
1832module_platform_driver(hdmi_lpe_audio_driver);
1833MODULE_ALIAS("platform:hdmi_lpe_audio");
1834
5dab11d8
JA		 1835MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1836MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1837MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1838MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1839MODULE_DESCRIPTION("Intel HDMI Audio driver");
1840MODULE_LICENSE("GPL v2");
1841MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
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