]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - sound/x86/intel_hdmi_audio.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: x86: Fix for CONFIG_PM=n
[mirror_ubuntu-bionic-kernel.git] / sound / x86 / intel_hdmi_audio.c
CommitLineData
5dab11d8
JA		 1/*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
5dab11d8
JA		 24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
da864809 28#include <linux/interrupt.h>
5dab11d8
JA		 29#include <linux/acpi.h>
30#include <asm/cacheflush.h>
31#include <sound/pcm.h>
32#include <sound/core.h>
33#include <sound/pcm_params.h>
34#include <sound/initval.h>
35#include <sound/control.h>
36#include <sound/initval.h>
da864809 37#include <drm/intel_lpe_audio.h>
5dab11d8
JA		 38#include "intel_hdmi_audio.h"
39
5dab11d8
JA		 40/*standard module options for ALSA. This module supports only one card*/
41static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
42static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
5dab11d8
JA		 43
44module_param_named(index, hdmi_card_index, int, 0444);
45MODULE_PARM_DESC(index,
46 "Index value for INTEL Intel HDMI Audio controller.");
47module_param_named(id, hdmi_card_id, charp, 0444);
48MODULE_PARM_DESC(id,
49 "ID string for INTEL Intel HDMI Audio controller.");
50
51/*
52 * ELD SA bits in the CEA Speaker Allocation data block
53 */
54static int eld_speaker_allocation_bits[] = {
55 [0] = FL | FR,
56 [1] = LFE,
57 [2] = FC,
58 [3] = RL | RR,
59 [4] = RC,
60 [5] = FLC | FRC,
61 [6] = RLC | RRC,
62 /* the following are not defined in ELD yet */
63 [7] = 0,
64};
65
66/*
67 * This is an ordered list!
68 *
69 * The preceding ones have better chances to be selected by
70 * hdmi_channel_allocation().
71 */
72static struct cea_channel_speaker_allocation channel_allocations[] = {
73/* channel: 7 6 5 4 3 2 1 0 */
74{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
75 /* 2.1 */
76{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
77 /* Dolby Surround */
78{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
79 /* surround40 */
80{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
81 /* surround41 */
82{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
83 /* surround50 */
84{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
85 /* surround51 */
86{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
87 /* 6.1 */
88{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
89 /* surround71 */
90{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
91
92{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
93{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
94{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
95{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
96{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
97{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
98{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
99{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
100{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
101{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
102{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
103{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
104{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
105{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
106{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
107{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
108{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
109{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
110{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
111{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
112{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
113{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
114{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
115};
116
117static struct channel_map_table map_tables[] = {
118 { SNDRV_CHMAP_FL, 0x00, FL },
119 { SNDRV_CHMAP_FR, 0x01, FR },
120 { SNDRV_CHMAP_RL, 0x04, RL },
121 { SNDRV_CHMAP_RR, 0x05, RR },
122 { SNDRV_CHMAP_LFE, 0x02, LFE },
123 { SNDRV_CHMAP_FC, 0x03, FC },
124 { SNDRV_CHMAP_RLC, 0x06, RLC },
125 { SNDRV_CHMAP_RRC, 0x07, RRC },
126 {} /* terminator */
127};
128
129/* hardware capability structure */
130static const struct snd_pcm_hardware snd_intel_hadstream = {
131 .info = (SNDRV_PCM_INFO_INTERLEAVED |
132 SNDRV_PCM_INFO_DOUBLE |
133 SNDRV_PCM_INFO_MMAP|
134 SNDRV_PCM_INFO_MMAP_VALID |
135 SNDRV_PCM_INFO_BATCH),
136 .formats = (SNDRV_PCM_FMTBIT_S24 |
137 SNDRV_PCM_FMTBIT_U24),
138 .rates = SNDRV_PCM_RATE_32000 |
139 SNDRV_PCM_RATE_44100 |
140 SNDRV_PCM_RATE_48000 |
141 SNDRV_PCM_RATE_88200 |
142 SNDRV_PCM_RATE_96000 |
143 SNDRV_PCM_RATE_176400 |
144 SNDRV_PCM_RATE_192000,
145 .rate_min = HAD_MIN_RATE,
146 .rate_max = HAD_MAX_RATE,
147 .channels_min = HAD_MIN_CHANNEL,
148 .channels_max = HAD_MAX_CHANNEL,
149 .buffer_bytes_max = HAD_MAX_BUFFER,
150 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
151 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
152 .periods_min = HAD_MIN_PERIODS,
153 .periods_max = HAD_MAX_PERIODS,
154 .fifo_size = HAD_FIFO_SIZE,
155};
156
157/* Register access functions */
372d855f 158static int had_get_hwstate(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 159{
160 /* Check for device presence -SW state */
c75b0476 161 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
5dab11d8 162 return -ENODEV;
5dab11d8
JA		 163
164 return 0;
165}
166
da864809
TI		 167static inline void
168mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
5dab11d8 169{
da864809 170 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 171}
172
da864809
TI		 173static inline void
174mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
5dab11d8 175{
da864809 176 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 177}
178
372d855f
TI		 179static int had_read_register(struct snd_intelhad *intelhaddata,
180 u32 offset, u32 *data)
5dab11d8
JA		 181{
182 int retval;
5dab11d8
JA		 183
184 retval = had_get_hwstate(intelhaddata);
da864809
TI		 185 if (retval)
186 return retval;
5dab11d8 187
da864809
TI		 188 mid_hdmi_audio_read(intelhaddata, offset, data);
189 return 0;
190}
191
192static void fixup_dp_config(struct snd_intelhad *intelhaddata,
193 u32 offset, u32 *data)
194{
195 if (intelhaddata->dp_output) {
196 if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
197 *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
198 }
5dab11d8
JA		 199}
200
372d855f
TI		 201static int had_write_register(struct snd_intelhad *intelhaddata,
202 u32 offset, u32 data)
5dab11d8
JA		 203{
204 int retval;
5dab11d8
JA		 205
206 retval = had_get_hwstate(intelhaddata);
da864809
TI		 207 if (retval)
208 return retval;
5dab11d8 209
da864809
TI		 210 fixup_dp_config(intelhaddata, offset, &data);
211 mid_hdmi_audio_write(intelhaddata, offset, data);
212 return 0;
5dab11d8
JA		 213}
214
372d855f
TI		 215static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
216 u32 data, u32 mask)
5dab11d8 217{
da864809 218 u32 val_tmp;
5dab11d8 219 int retval;
5dab11d8
JA		 220
221 retval = had_get_hwstate(intelhaddata);
da864809
TI		 222 if (retval)
223 return retval;
5dab11d8 224
da864809
TI		 225 mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
226 val_tmp &= ~mask;
227 val_tmp |= (data & mask);
228
229 fixup_dp_config(intelhaddata, offset, &val_tmp);
230 mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
231 return 0;
5dab11d8 232}
da864809
TI		 233
234/*
235 * function to read-modify AUD_CONFIG register on VLV2.
236 * The had_read_modify() function should not directly be used on VLV2 for
237 * updating AUD_CONFIG register.
5dab11d8
JA		 238 * This is because:
239 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
240 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
241 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
242 * register. This field should be 1xy binary for configuration with 6 or
243 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
244 * causes the "channels" field to be updated as 0xy binary resulting in
245 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
246 * appropriate value when doing read-modify of AUD_CONFIG register.
247 *
248 * @substream: the current substream or NULL if no active substream
249 * @data : data to be written
250 * @mask : mask
251 *
252 */
da864809 253static int had_read_modify_aud_config_v2(struct snd_intelhad *intelhaddata,
5dab11d8
JA		 254 u32 data, u32 mask)
255{
da864809 256 struct snd_pcm_substream *substream;
5dab11d8
JA		 257 union aud_cfg cfg_val = {.cfg_regval = 0};
258 u8 channels;
259
260 /*
261 * If substream is NULL, there is no active stream.
262 * In this case just set channels to 2
263 */
da864809
TI		 264 substream = intelhaddata->stream_info.had_substream;
265 if (substream && substream->runtime)
5dab11d8
JA		 266 channels = substream->runtime->channels;
267 else
268 channels = 2;
269 cfg_val.cfg_regx_v2.num_ch = channels - 2;
270
271 data = data | cfg_val.cfg_regval;
272 mask = mask | AUD_CONFIG_CH_MASK_V2;
273
c75b0476
TI		 274 dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n",
275 __func__, data, mask);
5dab11d8 276
79dda75a 277 return had_read_modify(intelhaddata, AUD_CONFIG, data, mask);
5dab11d8
JA		 278}
279
372d855f 280static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
da864809
TI		 281{
282 u32 status_reg;
283
284 if (enable) {
285 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
286 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
287 mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS_v2, status_reg);
288 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS_v2, &status_reg);
289 }
290}
291
372d855f
TI		 292static void snd_intelhad_enable_audio(struct snd_intelhad *intelhaddata,
293 bool enable)
5dab11d8 294{
da864809
TI		 295 had_read_modify_aud_config_v2(intelhaddata, enable ? BIT(0) : 0,
296 BIT(0));
5dab11d8
JA		 297}
298
79dda75a
TI		 299static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
300 u8 reset)
5dab11d8 301{
79dda75a 302 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, reset);
5dab11d8
JA		 303}
304
305/**
306 * initialize audio channel status registers
307 * This function is called in the prepare callback
308 */
309static int had_prog_status_reg(struct snd_pcm_substream *substream,
310 struct snd_intelhad *intelhaddata)
311{
312 union aud_cfg cfg_val = {.cfg_regval = 0};
313 union aud_ch_status_0 ch_stat0 = {.status_0_regval = 0};
314 union aud_ch_status_1 ch_stat1 = {.status_1_regval = 0};
315 int format;
316
5dab11d8
JA		 317 ch_stat0.status_0_regx.lpcm_id = (intelhaddata->aes_bits &
318 IEC958_AES0_NONAUDIO)>>1;
319 ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
320 IEC958_AES3_CON_CLOCK)>>4;
4812dcc4 321 cfg_val.cfg_regx_v2.val_bit = ch_stat0.status_0_regx.lpcm_id;
5dab11d8
JA		 322
323 switch (substream->runtime->rate) {
324 case AUD_SAMPLE_RATE_32:
325 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_32KHZ;
326 break;
327
328 case AUD_SAMPLE_RATE_44_1:
329 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_44KHZ;
330 break;
331 case AUD_SAMPLE_RATE_48:
332 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_48KHZ;
333 break;
334 case AUD_SAMPLE_RATE_88_2:
335 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_88KHZ;
336 break;
337 case AUD_SAMPLE_RATE_96:
338 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_96KHZ;
339 break;
340 case AUD_SAMPLE_RATE_176_4:
341 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_176KHZ;
342 break;
343 case AUD_SAMPLE_RATE_192:
344 ch_stat0.status_0_regx.samp_freq = CH_STATUS_MAP_192KHZ;
345 break;
346
347 default:
348 /* control should never come here */
349 return -EINVAL;
350 break;
351
352 }
79dda75a
TI		 353 had_write_register(intelhaddata,
354 AUD_CH_STATUS_0, ch_stat0.status_0_regval);
5dab11d8
JA		 355
356 format = substream->runtime->format;
357
358 if (format == SNDRV_PCM_FORMAT_S16_LE) {
359 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_20;
360 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_16BITS;
361 } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
362 ch_stat1.status_1_regx.max_wrd_len = MAX_SMPL_WIDTH_24;
363 ch_stat1.status_1_regx.wrd_len = SMPL_WIDTH_24BITS;
364 } else {
365 ch_stat1.status_1_regx.max_wrd_len = 0;
366 ch_stat1.status_1_regx.wrd_len = 0;
367 }
79dda75a
TI		 368 had_write_register(intelhaddata,
369 AUD_CH_STATUS_1, ch_stat1.status_1_regval);
5dab11d8
JA		 370 return 0;
371}
372
76296ef0 373/*
5dab11d8
JA		 374 * function to initialize audio
375 * registers and buffer confgiuration registers
376 * This function is called in the prepare callback
377 */
76296ef0
TI		 378static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
379 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 380{
381 union aud_cfg cfg_val = {.cfg_regval = 0};
382 union aud_buf_config buf_cfg = {.buf_cfgval = 0};
383 u8 channels;
384
385 had_prog_status_reg(substream, intelhaddata);
386
387 buf_cfg.buf_cfg_regx_v2.audio_fifo_watermark = FIFO_THRESHOLD;
388 buf_cfg.buf_cfg_regx_v2.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
389 buf_cfg.buf_cfg_regx_v2.aud_delay = 0;
79dda75a 390 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
5dab11d8
JA		 391
392 channels = substream->runtime->channels;
393 cfg_val.cfg_regx_v2.num_ch = channels - 2;
394 if (channels <= 2)
395 cfg_val.cfg_regx_v2.layout = LAYOUT0;
396 else
397 cfg_val.cfg_regx_v2.layout = LAYOUT1;
398
964ca808 399 cfg_val.cfg_regx_v2.val_bit = 1;
79dda75a 400 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.cfg_regval);
5dab11d8
JA		 401 return 0;
402}
403
5dab11d8
JA		 404/*
405 * Compute derived values in channel_allocations[].
406 */
407static void init_channel_allocations(void)
408{
409 int i, j;
410 struct cea_channel_speaker_allocation *p;
411
5dab11d8
JA		 412 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
413 p = channel_allocations + i;
414 p->channels = 0;
415 p->spk_mask = 0;
416 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
417 if (p->speakers[j]) {
418 p->channels++;
419 p->spk_mask |= p->speakers[j];
420 }
421 }
422}
423
424/*
425 * The transformation takes two steps:
426 *
427 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
428 * spk_mask => (channel_allocations[]) => ai->CA
429 *
430 * TODO: it could select the wrong CA from multiple candidates.
431 */
432static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata,
433 int channels)
434{
435 int i;
436 int ca = 0;
437 int spk_mask = 0;
438
439 /*
440 * CA defaults to 0 for basic stereo audio
441 */
442 if (channels <= 2)
443 return 0;
444
445 /*
446 * expand ELD's speaker allocation mask
447 *
448 * ELD tells the speaker mask in a compact(paired) form,
449 * expand ELD's notions to match the ones used by Audio InfoFrame.
450 */
451
452 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 453 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
JA		 454 spk_mask |= eld_speaker_allocation_bits[i];
455 }
456
457 /* search for the first working match in the CA table */
458 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
459 if (channels == channel_allocations[i].channels &&
460 (spk_mask & channel_allocations[i].spk_mask) ==
461 channel_allocations[i].spk_mask) {
462 ca = channel_allocations[i].ca_index;
463 break;
464 }
465 }
466
c75b0476 467 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
5dab11d8
JA		 468
469 return ca;
470}
471
472/* from speaker bit mask to ALSA API channel position */
473static int spk_to_chmap(int spk)
474{
475 struct channel_map_table *t = map_tables;
476
477 for (; t->map; t++) {
478 if (t->spk_mask == spk)
479 return t->map;
480 }
481 return 0;
482}
483
372d855f 484static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 485{
486 int i = 0, c = 0;
487 int spk_mask = 0;
488 struct snd_pcm_chmap_elem *chmap;
489 u8 eld_high, eld_high_mask = 0xF0;
490 u8 high_msb;
491
492 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
493 if (chmap == NULL) {
494 intelhaddata->chmap->chmap = NULL;
495 return;
496 }
497
c75b0476 498 dev_dbg(intelhaddata->dev, "eld.speaker_allocation_block = %x\n",
da864809 499 intelhaddata->eld.speaker_allocation_block);
5dab11d8
JA		 500
501 /* WA: Fix the max channel supported to 8 */
502
503 /*
504 * Sink may support more than 8 channels, if eld_high has more than
505 * one bit set. SOC supports max 8 channels.
506 * Refer eld_speaker_allocation_bits, for sink speaker allocation
507 */
508
509 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
da864809 510 eld_high = intelhaddata->eld.speaker_allocation_block & eld_high_mask;
5dab11d8
JA		 511 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
512 /* eld_high & (eld_high-1): if more than 1 bit set */
513 /* 0x1F: 7 channels */
514 for (i = 1; i < 4; i++) {
515 high_msb = eld_high & (0x80 >> i);
516 if (high_msb) {
da864809 517 intelhaddata->eld.speaker_allocation_block &=
5dab11d8
JA		 518 high_msb | 0xF;
519 break;
520 }
521 }
522 }
523
524 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
da864809 525 if (intelhaddata->eld.speaker_allocation_block & (1 << i))
5dab11d8
JA		 526 spk_mask |= eld_speaker_allocation_bits[i];
527 }
528
529 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
530 if (spk_mask == channel_allocations[i].spk_mask) {
531 for (c = 0; c < channel_allocations[i].channels; c++) {
532 chmap->map[c] = spk_to_chmap(
533 channel_allocations[i].speakers[
534 (MAX_SPEAKERS - 1)-c]);
535 }
536 chmap->channels = channel_allocations[i].channels;
537 intelhaddata->chmap->chmap = chmap;
538 break;
539 }
540 }
541 if (i >= ARRAY_SIZE(channel_allocations)) {
542 intelhaddata->chmap->chmap = NULL;
543 kfree(chmap);
544 }
545}
546
547/*
548 * ALSA API channel-map control callbacks
549 */
550static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
551 struct snd_ctl_elem_info *uinfo)
552{
553 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
554 struct snd_intelhad *intelhaddata = info->private_data;
555
556 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
557 return -ENODEV;
558 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
559 uinfo->count = HAD_MAX_CHANNEL;
560 uinfo->value.integer.min = 0;
561 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
562 return 0;
563}
564
565static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
566 struct snd_ctl_elem_value *ucontrol)
567{
568 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
569 struct snd_intelhad *intelhaddata = info->private_data;
570 int i = 0;
571 const struct snd_pcm_chmap_elem *chmap;
572
573 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
574 return -ENODEV;
575 if (intelhaddata->chmap->chmap == NULL)
576 return -ENODATA;
577 chmap = intelhaddata->chmap->chmap;
c75b0476 578 for (i = 0; i < chmap->channels; i++)
5dab11d8 579 ucontrol->value.integer.value[i] = chmap->map[i];
5dab11d8
JA		 580
581 return 0;
582}
583
584static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
585 struct snd_pcm *pcm)
586{
587 int err = 0;
588
589 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
590 NULL, 0, (unsigned long)intelhaddata,
591 &intelhaddata->chmap);
592 if (err < 0)
593 return err;
594
595 intelhaddata->chmap->private_data = intelhaddata;
596 intelhaddata->kctl = intelhaddata->chmap->kctl;
597 intelhaddata->kctl->info = had_chmap_ctl_info;
598 intelhaddata->kctl->get = had_chmap_ctl_get;
599 intelhaddata->chmap->chmap = NULL;
600 return 0;
601}
602
76296ef0
TI		 603/*
604 * snd_intelhad_prog_dip - to initialize Data Island Packets registers
5dab11d8
JA		 605 *
606 * @substream:substream for which the prepare function is called
607 * @intelhaddata:substream private data
608 *
609 * This function is called in the prepare callback
610 */
76296ef0
TI		 611static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream,
612 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 613{
614 int i;
615 union aud_ctrl_st ctrl_state = {.ctrl_val = 0};
616 union aud_info_frame2 frame2 = {.fr2_val = 0};
617 union aud_info_frame3 frame3 = {.fr3_val = 0};
618 u8 checksum = 0;
964ca808 619 u32 info_frame;
5dab11d8
JA		 620 int channels;
621
622 channels = substream->runtime->channels;
623
79dda75a 624 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8 625
964ca808
PLB		 626 if (intelhaddata->dp_output) {
627 info_frame = DP_INFO_FRAME_WORD1;
628 frame2.fr2_val = 1;
629 } else {
630 info_frame = HDMI_INFO_FRAME_WORD1;
631 frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
5dab11d8 632
964ca808
PLB		 633 frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
634 intelhaddata, channels);
5dab11d8 635
964ca808
PLB		 636 /*Calculte the byte wide checksum for all valid DIP words*/
637 for (i = 0; i < BYTES_PER_WORD; i++)
638 checksum += (info_frame >> i*BITS_PER_BYTE) & MASK_BYTE0;
639 for (i = 0; i < BYTES_PER_WORD; i++)
640 checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
641 for (i = 0; i < BYTES_PER_WORD; i++)
642 checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
5dab11d8 643
964ca808
PLB		 644 frame2.fr2_regx.chksum = -(checksum);
645 }
5dab11d8 646
79dda75a
TI		 647 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, info_frame);
648 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame2.fr2_val);
649 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, frame3.fr3_val);
5dab11d8
JA		 650
651 /* program remaining DIP words with zero */
652 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
79dda75a 653 had_write_register(intelhaddata, AUD_HDMIW_INFOFR_v2, 0x0);
5dab11d8
JA		 654
655 ctrl_state.ctrl_regx.dip_freq = 1;
656 ctrl_state.ctrl_regx.dip_en_sta = 1;
79dda75a 657 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.ctrl_val);
5dab11d8
JA		 658}
659
660/**
661 * snd_intelhad_prog_buffer - programs buffer
662 * address and length registers
663 *
664 * @substream:substream for which the prepare function is called
665 * @intelhaddata:substream private data
666 *
667 * This function programs ring buffer address and length into registers.
668 */
372d855f 669static int snd_intelhad_prog_buffer(struct snd_intelhad *intelhaddata,
5dab11d8
JA		 670 int start, int end)
671{
672 u32 ring_buf_addr, ring_buf_size, period_bytes;
673 u8 i, num_periods;
674 struct snd_pcm_substream *substream;
675
676 substream = intelhaddata->stream_info.had_substream;
c75b0476 677 if (WARN_ON(!substream))
5dab11d8 678 return 0;
5dab11d8
JA		 679
680 ring_buf_addr = substream->runtime->dma_addr;
681 ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
682 intelhaddata->stream_info.ring_buf_size = ring_buf_size;
683 period_bytes = frames_to_bytes(substream->runtime,
684 substream->runtime->period_size);
685 num_periods = substream->runtime->periods;
686
687 /*
688 * buffer addr should be 64 byte aligned, period bytes
689 * will be used to calculate addr offset
690 */
691 period_bytes &= ~0x3F;
692
693 /* Hardware supports MAX_PERIODS buffers */
694 if (end >= HAD_MAX_PERIODS)
695 return -EINVAL;
696
697 for (i = start; i <= end; i++) {
698 /* Program the buf registers with addr and len */
699 intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
700 (i * period_bytes);
701 if (i < num_periods-1)
702 intelhaddata->buf_info[i].buf_size = period_bytes;
703 else
704 intelhaddata->buf_info[i].buf_size = ring_buf_size -
705 (period_bytes*i);
706
79dda75a
TI		 707 had_write_register(intelhaddata,
708 AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
5dab11d8
JA		 709 intelhaddata->buf_info[i].buf_addr |
710 BIT(0) | BIT(1));
79dda75a
TI		 711 had_write_register(intelhaddata,
712 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
5dab11d8
JA		 713 period_bytes);
714 intelhaddata->buf_info[i].is_valid = true;
715 }
c75b0476
TI		 716 dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n",
717 __func__, start, end,
718 intelhaddata->buf_info[start].buf_addr,
719 intelhaddata->buf_info[start].buf_size);
5dab11d8
JA		 720 intelhaddata->valid_buf_cnt = num_periods;
721 return 0;
722}
723
372d855f 724static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 725{
726 int i, retval = 0;
727 u32 len[4];
728
729 for (i = 0; i < 4 ; i++) {
79dda75a
TI		 730 had_read_register(intelhaddata,
731 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
732 &len[i]);
5dab11d8
JA		 733 if (!len[i])
734 retval++;
735 }
736 if (retval != 1) {
737 for (i = 0; i < 4 ; i++)
c75b0476
TI		 738 dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n",
739 i, len[i]);
5dab11d8
JA		 740 }
741
742 return retval;
743}
744
964ca808
PLB		 745static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
746{
747 u32 maud_val;
748
749 /* Select maud according to DP 1.2 spec*/
750 if (link_rate == DP_2_7_GHZ) {
751 switch (aud_samp_freq) {
752 case AUD_SAMPLE_RATE_32:
753 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
754 break;
755
756 case AUD_SAMPLE_RATE_44_1:
757 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
758 break;
759
760 case AUD_SAMPLE_RATE_48:
761 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
762 break;
763
764 case AUD_SAMPLE_RATE_88_2:
765 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
766 break;
767
768 case AUD_SAMPLE_RATE_96:
769 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
770 break;
771
772 case AUD_SAMPLE_RATE_176_4:
773 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
774 break;
775
776 case HAD_MAX_RATE:
777 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
778 break;
779
780 default:
781 maud_val = -EINVAL;
782 break;
783 }
784 } else if (link_rate == DP_1_62_GHZ) {
785 switch (aud_samp_freq) {
786 case AUD_SAMPLE_RATE_32:
787 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
788 break;
789
790 case AUD_SAMPLE_RATE_44_1:
791 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
792 break;
793
794 case AUD_SAMPLE_RATE_48:
795 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
796 break;
797
798 case AUD_SAMPLE_RATE_88_2:
799 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
800 break;
801
802 case AUD_SAMPLE_RATE_96:
803 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
804 break;
805
806 case AUD_SAMPLE_RATE_176_4:
807 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
808 break;
809
810 case HAD_MAX_RATE:
811 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
812 break;
813
814 default:
815 maud_val = -EINVAL;
816 break;
817 }
818 } else
819 maud_val = -EINVAL;
820
821 return maud_val;
822}
823
76296ef0
TI		 824/*
825 * snd_intelhad_prog_cts - Program HDMI audio CTS value
5dab11d8
JA		 826 *
827 * @aud_samp_freq: sampling frequency of audio data
828 * @tmds: sampling frequency of the display data
829 * @n_param: N value, depends on aud_samp_freq
830 * @intelhaddata:substream private data
831 *
832 * Program CTS register based on the audio and display sampling frequency
833 */
76296ef0
TI		 834static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds,
835 u32 link_rate, u32 n_param,
836 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 837{
838 u32 cts_val;
839 u64 dividend, divisor;
840
964ca808
PLB		 841 if (intelhaddata->dp_output) {
842 /* Substitute cts_val with Maud according to DP 1.2 spec*/
843 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
844 } else {
845 /* Calculate CTS according to HDMI 1.3a spec*/
846 dividend = (u64)tmds * n_param*1000;
847 divisor = 128 * aud_samp_freq;
848 cts_val = div64_u64(dividend, divisor);
849 }
c75b0476 850 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
964ca808 851 tmds, n_param, cts_val);
79dda75a 852 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
5dab11d8
JA		 853}
854
855static int had_calculate_n_value(u32 aud_samp_freq)
856{
857 s32 n_val;
858
859 /* Select N according to HDMI 1.3a spec*/
860 switch (aud_samp_freq) {
861 case AUD_SAMPLE_RATE_32:
862 n_val = 4096;
863 break;
864
865 case AUD_SAMPLE_RATE_44_1:
866 n_val = 6272;
867 break;
868
869 case AUD_SAMPLE_RATE_48:
870 n_val = 6144;
871 break;
872
873 case AUD_SAMPLE_RATE_88_2:
874 n_val = 12544;
875 break;
876
877 case AUD_SAMPLE_RATE_96:
878 n_val = 12288;
879 break;
880
881 case AUD_SAMPLE_RATE_176_4:
882 n_val = 25088;
883 break;
884
885 case HAD_MAX_RATE:
886 n_val = 24576;
887 break;
888
889 default:
890 n_val = -EINVAL;
891 break;
892 }
893 return n_val;
894}
895
76296ef0
TI		 896/*
897 * snd_intelhad_prog_n - Program HDMI audio N value
5dab11d8
JA		 898 *
899 * @aud_samp_freq: sampling frequency of audio data
900 * @n_param: N value, depends on aud_samp_freq
901 * @intelhaddata:substream private data
902 *
903 * This function is called in the prepare callback.
904 * It programs based on the audio and display sampling frequency
905 */
76296ef0
TI		 906static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param,
907 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 908{
909 s32 n_val;
910
964ca808
PLB		 911 if (intelhaddata->dp_output) {
912 /*
913 * According to DP specs, Maud and Naud values hold
914 * a relationship, which is stated as:
915 * Maud/Naud = 512 * fs / f_LS_Clk
916 * where, fs is the sampling frequency of the audio stream
917 * and Naud is 32768 for Async clock.
918 */
919
920 n_val = DP_NAUD_VAL;
921 } else
922 n_val = had_calculate_n_value(aud_samp_freq);
5dab11d8
JA		 923
924 if (n_val < 0)
925 return n_val;
926
79dda75a 927 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
5dab11d8
JA		 928 *n_param = n_val;
929 return 0;
930}
931
372d855f 932static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 933{
934 u32 hdmi_status, i = 0;
935
936 /* Handle Underrun interrupt within Audio Unit */
79dda75a 937 had_write_register(intelhaddata, AUD_CONFIG, 0);
5dab11d8 938 /* Reset buffer pointers */
79dda75a
TI		 939 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 1);
940 had_write_register(intelhaddata, AUD_HDMI_STATUS_v2, 0);
5dab11d8
JA		 941 /**
942 * The interrupt status 'sticky' bits might not be cleared by
943 * setting '1' to that bit once...
944 */
945 do { /* clear bit30, 31 AUD_HDMI_STATUS */
79dda75a
TI		 946 had_read_register(intelhaddata, AUD_HDMI_STATUS_v2,
947 &hdmi_status);
c75b0476 948 dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
5dab11d8
JA		 949 if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
950 i++;
79dda75a
TI		 951 had_write_register(intelhaddata,
952 AUD_HDMI_STATUS_v2, hdmi_status);
5dab11d8
JA		 953 } else
954 break;
955 } while (i < MAX_CNT);
956 if (i >= MAX_CNT)
c75b0476 957 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
5dab11d8
JA		 958}
959
960/**
961 * snd_intelhad_open - stream initializations are done here
962 * @substream:substream for which the stream function is called
963 *
964 * This function is called whenever a PCM stream is opened
965 */
966static int snd_intelhad_open(struct snd_pcm_substream *substream)
967{
968 struct snd_intelhad *intelhaddata;
969 struct snd_pcm_runtime *runtime;
970 struct had_stream_pvt *stream;
5647aec2 971 struct had_stream_data *had_stream;
5dab11d8
JA		 972 int retval;
973
5dab11d8 974 intelhaddata = snd_pcm_substream_chip(substream);
5647aec2 975 had_stream = &intelhaddata->stream_data;
5dab11d8 976 runtime = substream->runtime;
6ddb3ab6 977 intelhaddata->underrun_count = 0;
5dab11d8
JA		 978
979 pm_runtime_get(intelhaddata->dev);
980
981 if (had_get_hwstate(intelhaddata)) {
c75b0476
TI		 982 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
983 __func__);
5dab11d8
JA		 984 retval = -ENODEV;
985 goto exit_put_handle;
986 }
987
988 /* Check, if device already in use */
989 if (runtime->private_data) {
c75b0476 990 dev_dbg(intelhaddata->dev, "Device already in use\n");
5dab11d8
JA		 991 retval = -EBUSY;
992 goto exit_put_handle;
993 }
994
995 /* set the runtime hw parameter with local snd_pcm_hardware struct */
996 runtime->hw = snd_intel_hadstream;
997
998 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
999 if (!stream) {
1000 retval = -ENOMEM;
1001 goto exit_put_handle;
1002 }
1003 stream->stream_status = STREAM_INIT;
1004 runtime->private_data = stream;
1005
1006 retval = snd_pcm_hw_constraint_integer(runtime,
1007 SNDRV_PCM_HW_PARAM_PERIODS);
1008 if (retval < 0)
1009 goto exit_err;
1010
1011 /* Make sure, that the period size is always aligned
1012 * 64byte boundary
1013 */
1014 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1015 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1016 if (retval < 0) {
c75b0476
TI		 1017 dev_dbg(intelhaddata->dev, "%s:step_size=64 failed,err=%d\n",
1018 __func__, retval);
5dab11d8
JA		 1019 goto exit_err;
1020 }
1021
1022 return retval;
1023exit_err:
1024 kfree(stream);
1025exit_put_handle:
1026 pm_runtime_put(intelhaddata->dev);
1027 runtime->private_data = NULL;
1028 return retval;
1029}
1030
1031/**
1032 * had_period_elapsed - updates the hardware pointer status
1033 * @had_substream:substream for which the stream function is called
1034 *
1035 */
1036static void had_period_elapsed(void *had_substream)
1037{
1038 struct snd_pcm_substream *substream = had_substream;
1039 struct had_stream_pvt *stream;
1040
5dab11d8
JA		 1041 if (!substream || !substream->runtime)
1042 return;
1043 stream = substream->runtime->private_data;
1044 if (!stream)
1045 return;
1046
1047 if (stream->stream_status != STREAM_RUNNING)
1048 return;
1049 snd_pcm_period_elapsed(substream);
1050}
1051
1052/**
1053 * snd_intelhad_init_stream - internal function to initialize stream info
1054 * @substream:substream for which the stream function is called
1055 *
1056 */
1057static int snd_intelhad_init_stream(struct snd_pcm_substream *substream)
1058{
1059 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream);
1060
5dab11d8
JA		 1061 intelhaddata->stream_info.period_elapsed = had_period_elapsed;
1062 intelhaddata->stream_info.had_substream = substream;
1063 intelhaddata->stream_info.buffer_ptr = 0;
1064 intelhaddata->stream_info.buffer_rendered = 0;
1065 intelhaddata->stream_info.sfreq = substream->runtime->rate;
1066 return 0;
1067}
1068
1069/**
1070 * snd_intelhad_close- to free parameteres when stream is stopped
1071 *
1072 * @substream: substream for which the function is called
1073 *
1074 * This function is called by ALSA framework when stream is stopped
1075 */
1076static int snd_intelhad_close(struct snd_pcm_substream *substream)
1077{
1078 struct snd_intelhad *intelhaddata;
1079 struct snd_pcm_runtime *runtime;
1080
5dab11d8
JA		 1081 intelhaddata = snd_pcm_substream_chip(substream);
1082 runtime = substream->runtime;
1083
c75b0476 1084 if (WARN_ON(!runtime->private_data))
5dab11d8 1085 return 0;
5dab11d8
JA		 1086
1087 intelhaddata->stream_info.buffer_rendered = 0;
1088 intelhaddata->stream_info.buffer_ptr = 0;
1089 intelhaddata->stream_info.str_id = 0;
1090 intelhaddata->stream_info.had_substream = NULL;
1091
1092 /* Check if following drv_status modification is required - VA */
1093 if (intelhaddata->drv_status != HAD_DRV_DISCONNECTED) {
1094 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI		 1095 dev_dbg(intelhaddata->dev,
1096 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
5dab11d8
JA		 1097 __func__, __LINE__);
1098 }
1099 kfree(runtime->private_data);
1100 runtime->private_data = NULL;
1101 pm_runtime_put(intelhaddata->dev);
1102 return 0;
1103}
1104
1105/**
1106 * snd_intelhad_hw_params- to setup the hardware parameters
1107 * like allocating the buffers
1108 *
1109 * @substream: substream for which the function is called
1110 * @hw_params: hardware parameters
1111 *
1112 * This function is called by ALSA framework when hardware params are set
1113 */
1114static int snd_intelhad_hw_params(struct snd_pcm_substream *substream,
1115 struct snd_pcm_hw_params *hw_params)
1116{
c75b0476 1117 struct snd_intelhad *intelhaddata;
5dab11d8
JA		 1118 unsigned long addr;
1119 int pages, buf_size, retval;
1120
5dab11d8
JA		 1121 if (!hw_params)
1122 return -EINVAL;
1123
c75b0476 1124 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1125 buf_size = params_buffer_bytes(hw_params);
1126 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1127 if (retval < 0)
1128 return retval;
c75b0476
TI		 1129 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1130 __func__, buf_size);
5dab11d8
JA		 1131 /* mark the pages as uncached region */
1132 addr = (unsigned long) substream->runtime->dma_area;
1133 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1134 retval = set_memory_uc(addr, pages);
1135 if (retval) {
c75b0476
TI		 1136 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1137 retval);
5dab11d8
JA		 1138 return retval;
1139 }
1140 memset(substream->runtime->dma_area, 0, buf_size);
1141
1142 return retval;
1143}
1144
1145/**
1146 * snd_intelhad_hw_free- to release the resources allocated during
1147 * hardware params setup
1148 *
1149 * @substream: substream for which the function is called
1150 *
1151 * This function is called by ALSA framework before close callback.
1152 *
1153 */
1154static int snd_intelhad_hw_free(struct snd_pcm_substream *substream)
1155{
1156 unsigned long addr;
1157 u32 pages;
1158
5dab11d8
JA		 1159 /* mark back the pages as cached/writeback region before the free */
1160 if (substream->runtime->dma_area != NULL) {
1161 addr = (unsigned long) substream->runtime->dma_area;
1162 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1163 PAGE_SIZE;
1164 set_memory_wb(addr, pages);
1165 return snd_pcm_lib_free_pages(substream);
1166 }
1167 return 0;
1168}
1169
1170/**
1171 * snd_intelhad_pcm_trigger - stream activities are handled here
1172 * @substream:substream for which the stream function is called
1173 * @cmd:the stream commamd thats requested from upper layer
1174 * This function is called whenever an a stream activity is invoked
1175 */
1176static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream,
1177 int cmd)
1178{
da864809 1179 int retval = 0;
5dab11d8
JA		 1180 unsigned long flag_irq;
1181 struct snd_intelhad *intelhaddata;
1182 struct had_stream_pvt *stream;
5647aec2 1183 struct had_stream_data *had_stream;
5dab11d8 1184
5dab11d8
JA		 1185 intelhaddata = snd_pcm_substream_chip(substream);
1186 stream = substream->runtime->private_data;
5647aec2 1187 had_stream = &intelhaddata->stream_data;
5dab11d8
JA		 1188
1189 switch (cmd) {
1190 case SNDRV_PCM_TRIGGER_START:
5dab11d8
JA		 1191 /* Disable local INTRs till register prgmng is done */
1192 if (had_get_hwstate(intelhaddata)) {
c75b0476
TI		 1193 dev_dbg(intelhaddata->dev,
1194 "_START: HDMI cable plugged-out\n");
5dab11d8
JA		 1195 retval = -ENODEV;
1196 break;
1197 }
1198 stream->stream_status = STREAM_RUNNING;
1199
1200 had_stream->stream_type = HAD_RUNNING_STREAM;
1201
1202 /* Enable Audio */
da864809
TI		 1203 snd_intelhad_enable_audio_int(intelhaddata, true);
1204 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA		 1205 break;
1206
1207 case SNDRV_PCM_TRIGGER_STOP:
5dab11d8
JA		 1208 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irq);
1209 intelhaddata->stream_info.str_id = 0;
1210 intelhaddata->curr_buf = 0;
1211
c75b0476 1212 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
5dab11d8
JA		 1213
1214 had_stream->stream_type = HAD_INIT;
1215 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irq);
1216 /* Disable Audio */
da864809
TI		 1217 snd_intelhad_enable_audio_int(intelhaddata, false);
1218 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8 1219 /* Reset buffer pointers */
79dda75a
TI		 1220 snd_intelhad_reset_audio(intelhaddata, 1);
1221 snd_intelhad_reset_audio(intelhaddata, 0);
5dab11d8 1222 stream->stream_status = STREAM_DROPPED;
da864809 1223 snd_intelhad_enable_audio_int(intelhaddata, false);
5dab11d8
JA		 1224 break;
1225
1226 default:
1227 retval = -EINVAL;
1228 }
1229 return retval;
1230}
1231
1232/**
1233 * snd_intelhad_pcm_prepare- internal preparation before starting a stream
1234 *
1235 * @substream: substream for which the function is called
1236 *
1237 * This function is called when a stream is started for internal preparation.
1238 */
1239static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
1240{
1241 int retval;
1242 u32 disp_samp_freq, n_param;
964ca808 1243 u32 link_rate = 0;
5dab11d8
JA		 1244 struct snd_intelhad *intelhaddata;
1245 struct snd_pcm_runtime *runtime;
5647aec2 1246 struct had_stream_data *had_stream;
5dab11d8 1247
5dab11d8
JA		 1248 intelhaddata = snd_pcm_substream_chip(substream);
1249 runtime = substream->runtime;
5647aec2 1250 had_stream = &intelhaddata->stream_data;
5dab11d8
JA		 1251
1252 if (had_get_hwstate(intelhaddata)) {
c75b0476
TI		 1253 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1254 __func__);
5dab11d8
JA		 1255 retval = -ENODEV;
1256 goto prep_end;
1257 }
1258
c75b0476 1259 dev_dbg(intelhaddata->dev, "period_size=%d\n",
5dab11d8 1260 (int)frames_to_bytes(runtime, runtime->period_size));
c75b0476
TI		 1261 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1262 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1263 (int)snd_pcm_lib_buffer_bytes(substream));
1264 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1265 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
5dab11d8
JA		 1266
1267 if (intelhaddata->stream_info.str_id) {
c75b0476
TI		 1268 dev_dbg(intelhaddata->dev,
1269 "_prepare is called for existing str_id#%d\n",
5dab11d8
JA		 1270 intelhaddata->stream_info.str_id);
1271 retval = snd_intelhad_pcm_trigger(substream,
1272 SNDRV_PCM_TRIGGER_STOP);
1273 return retval;
1274 }
1275
1276 retval = snd_intelhad_init_stream(substream);
1277 if (retval)
1278 goto prep_end;
1279
1280
1281 /* Get N value in KHz */
da864809 1282 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1283
76296ef0
TI		 1284 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1285 intelhaddata);
5dab11d8 1286 if (retval) {
c75b0476
TI		 1287 dev_err(intelhaddata->dev,
1288 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1289 goto prep_end;
1290 }
964ca808
PLB		 1291
1292 if (intelhaddata->dp_output)
da864809 1293 link_rate = intelhaddata->link_rate;
964ca808 1294
76296ef0
TI		 1295 snd_intelhad_prog_cts(substream->runtime->rate,
1296 disp_samp_freq, link_rate,
1297 n_param, intelhaddata);
5dab11d8 1298
76296ef0 1299 snd_intelhad_prog_dip(substream, intelhaddata);
5dab11d8 1300
76296ef0 1301 retval = snd_intelhad_audio_ctrl(substream, intelhaddata);
5dab11d8
JA		 1302
1303 /* Prog buffer address */
1304 retval = snd_intelhad_prog_buffer(intelhaddata,
1305 HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
1306
1307 /*
1308 * Program channel mapping in following order:
1309 * FL, FR, C, LFE, RL, RR
1310 */
1311
79dda75a 1312 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
5dab11d8
JA		 1313
1314prep_end:
1315 return retval;
1316}
1317
1318/**
1319 * snd_intelhad_pcm_pointer- to send the current buffer pointerprocessed by hw
1320 *
1321 * @substream: substream for which the function is called
1322 *
1323 * This function is called by ALSA framework to get the current hw buffer ptr
1324 * when a period is elapsed
1325 */
1326static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
1327 struct snd_pcm_substream *substream)
1328{
1329 struct snd_intelhad *intelhaddata;
1330 u32 bytes_rendered = 0;
1331 u32 t;
1332 int buf_id;
1333
5dab11d8
JA		 1334 intelhaddata = snd_pcm_substream_chip(substream);
1335
1336 if (intelhaddata->flag_underrun) {
1337 intelhaddata->flag_underrun = 0;
1338 return SNDRV_PCM_POS_XRUN;
1339 }
1340
1341 /* Use a hw register to calculate sub-period position reports.
1342 * This makes PulseAudio happier.
1343 */
1344
1345 buf_id = intelhaddata->curr_buf % 4;
79dda75a
TI		 1346 had_read_register(intelhaddata,
1347 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
232892fb
JA		 1348
1349 if ((t == 0) || (t == ((u32)-1L))) {
6ddb3ab6 1350 intelhaddata->underrun_count++;
c75b0476
TI		 1351 dev_dbg(intelhaddata->dev,
1352 "discovered buffer done for buf %d, count = %d\n",
6ddb3ab6 1353 buf_id, intelhaddata->underrun_count);
232892fb 1354
6ddb3ab6 1355 if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
c75b0476
TI		 1356 dev_dbg(intelhaddata->dev,
1357 "assume audio_codec_reset, underrun = %d - do xrun\n",
6ddb3ab6
TI		 1358 intelhaddata->underrun_count);
1359 intelhaddata->underrun_count = 0;
232892fb
JA		 1360 return SNDRV_PCM_POS_XRUN;
1361 }
1362 } else {
1363 /* Reset Counter */
6ddb3ab6 1364 intelhaddata->underrun_count = 0;
5dab11d8 1365 }
232892fb 1366
5dab11d8
JA		 1367 t = intelhaddata->buf_info[buf_id].buf_size - t;
1368
1369 if (intelhaddata->stream_info.buffer_rendered)
1370 div_u64_rem(intelhaddata->stream_info.buffer_rendered,
1371 intelhaddata->stream_info.ring_buf_size,
1372 &(bytes_rendered));
1373
1374 intelhaddata->stream_info.buffer_ptr = bytes_to_frames(
1375 substream->runtime,
1376 bytes_rendered + t);
1377 return intelhaddata->stream_info.buffer_ptr;
1378}
1379
1380/**
1381 * snd_intelhad_pcm_mmap- mmaps a kernel buffer to user space for copying data
1382 *
1383 * @substream: substream for which the function is called
1384 * @vma: struct instance of memory VMM memory area
1385 *
1386 * This function is called by OS when a user space component
1387 * tries to get mmap memory from driver
1388 */
1389static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream,
1390 struct vm_area_struct *vma)
1391{
5dab11d8
JA		 1392 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1393 return remap_pfn_range(vma, vma->vm_start,
1394 substream->dma_buffer.addr >> PAGE_SHIFT,
1395 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1396}
1397
da864809 1398static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata)
5dab11d8 1399{
da864809 1400 struct snd_pcm_substream *substream;
5dab11d8
JA		 1401 int retval = 0;
1402 u32 disp_samp_freq, n_param;
964ca808 1403 u32 link_rate = 0;
5dab11d8 1404
da864809
TI		 1405 substream = intelhaddata->stream_info.had_substream;
1406 if (!substream || !substream->runtime)
1407 return 0;
5dab11d8
JA		 1408
1409 /* Disable Audio */
da864809 1410 snd_intelhad_enable_audio(intelhaddata, false);
5dab11d8
JA		 1411
1412 /* Update CTS value */
da864809 1413 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1414
76296ef0
TI		 1415 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1416 intelhaddata);
5dab11d8 1417 if (retval) {
c75b0476
TI		 1418 dev_err(intelhaddata->dev,
1419 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1420 goto out;
1421 }
964ca808
PLB		 1422
1423 if (intelhaddata->dp_output)
da864809 1424 link_rate = intelhaddata->link_rate;
964ca808 1425
76296ef0
TI		 1426 snd_intelhad_prog_cts(substream->runtime->rate,
1427 disp_samp_freq, link_rate,
1428 n_param, intelhaddata);
5dab11d8
JA		 1429
1430 /* Enable Audio */
da864809 1431 snd_intelhad_enable_audio(intelhaddata, true);
5dab11d8
JA		 1432
1433out:
1434 return retval;
1435}
1436
372d855f
TI		 1437/*
1438 * hdmi_lpe_audio_suspend - power management suspend function
1439 *
1440 * @pdev: platform device
1441 *
1442 * This function is called by client driver to suspend the
1443 * hdmi audio.
1444 */
1445static int hdmi_lpe_audio_suspend(struct platform_device *pdev,
1446 pm_message_t state)
1447{
1448 struct had_stream_data *had_stream;
1449 unsigned long flag_irqs;
1450 struct snd_pcm_substream *substream;
1451 struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
1452
372d855f
TI		 1453 had_stream = &intelhaddata->stream_data;
1454 substream = intelhaddata->stream_info.had_substream;
1455
e29c0f96 1456 if (!pm_runtime_status_suspended(intelhaddata->dev)) {
c75b0476 1457 dev_err(intelhaddata->dev, "audio stream is active\n");
372d855f
TI		 1458 return -EAGAIN;
1459 }
1460
1461
1462 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1463 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
1464 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476 1465 dev_dbg(intelhaddata->dev, "had not connected\n");
372d855f
TI		 1466 return 0;
1467 }
1468
1469 if (intelhaddata->drv_status == HAD_DRV_SUSPENDED) {
1470 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476 1471 dev_dbg(intelhaddata->dev, "had already suspended\n");
372d855f
TI		 1472 return 0;
1473 }
1474
1475 intelhaddata->drv_status = HAD_DRV_SUSPENDED;
c75b0476
TI		 1476 dev_dbg(intelhaddata->dev,
1477 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_SUSPENDED\n",
372d855f
TI		 1478 __func__, __LINE__);
1479
1480 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1481 snd_intelhad_enable_audio_int(intelhaddata, false);
372d855f
TI		 1482 return 0;
1483}
1484
1485/*
1486 * hdmi_lpe_audio_resume - power management resume function
1487 *
1488 *@pdev: platform device
1489 *
1490 * This function is called by client driver to resume the
1491 * hdmi audio.
1492 */
1493static int hdmi_lpe_audio_resume(struct platform_device *pdev)
1494{
1495 struct snd_intelhad *intelhaddata = platform_get_drvdata(pdev);
1496 unsigned long flag_irqs;
1497
372d855f
TI		 1498 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1499 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
1500 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476 1501 dev_dbg(intelhaddata->dev, "had not connected\n");
372d855f
TI		 1502 return 0;
1503 }
1504
1505 if (intelhaddata->drv_status != HAD_DRV_SUSPENDED) {
1506 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476 1507 dev_err(intelhaddata->dev, "had is not in suspended state\n");
372d855f
TI		 1508 return 0;
1509 }
1510
1511 if (had_get_hwstate(intelhaddata)) {
1512 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476
TI		 1513 dev_err(intelhaddata->dev,
1514 "Failed to resume. Device not accessible\n");
372d855f
TI		 1515 return -ENODEV;
1516 }
1517
1518 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI		 1519 dev_dbg(intelhaddata->dev,
1520 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f
TI		 1521 __func__, __LINE__);
1522 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1523 snd_intelhad_enable_audio_int(intelhaddata, true);
372d855f
TI		 1524 return 0;
1525}
1526
1527static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata,
1528 enum intel_had_aud_buf_type buf_id)
1529{
1530 int i, intr_count = 0;
1531 enum intel_had_aud_buf_type buff_done;
1532 u32 buf_size, buf_addr;
1533 struct had_stream_data *had_stream;
1534 unsigned long flag_irqs;
1535
1536 had_stream = &intelhaddata->stream_data;
1537
1538 buff_done = buf_id;
1539
1540 intr_count = snd_intelhad_read_len(intelhaddata);
1541 if (intr_count > 1) {
1542 /* In case of active playback */
c75b0476
TI		 1543 dev_err(intelhaddata->dev,
1544 "Driver detected %d missed buffer done interrupt(s)\n",
1545 (intr_count - 1));
372d855f
TI		 1546 if (intr_count > 3)
1547 return intr_count;
1548
1549 buf_id += (intr_count - 1);
1550 /* Reprogram registers*/
1551 for (i = buff_done; i < buf_id; i++) {
1552 int j = i % 4;
1553
1554 buf_size = intelhaddata->buf_info[j].buf_size;
1555 buf_addr = intelhaddata->buf_info[j].buf_addr;
1556 had_write_register(intelhaddata,
1557 AUD_BUF_A_LENGTH +
1558 (j * HAD_REG_WIDTH), buf_size);
1559 had_write_register(intelhaddata,
1560 AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH),
1561 (buf_addr | BIT(0) | BIT(1)));
1562 }
1563 buf_id = buf_id % 4;
1564 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1565 intelhaddata->buff_done = buf_id;
1566 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1567 }
1568
1569 return intr_count;
1570}
1571
1572static int had_process_buffer_done(struct snd_intelhad *intelhaddata)
1573{
1574 u32 len = 1;
1575 enum intel_had_aud_buf_type buf_id;
1576 enum intel_had_aud_buf_type buff_done;
1577 struct pcm_stream_info *stream;
1578 u32 buf_size;
1579 struct had_stream_data *had_stream;
1580 int intr_count;
1581 enum had_status_stream stream_type;
1582 unsigned long flag_irqs;
1583
1584 had_stream = &intelhaddata->stream_data;
1585 stream = &intelhaddata->stream_info;
1586 intr_count = 1;
1587
1588 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1589 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
1590 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
c75b0476
TI		 1591 dev_dbg(intelhaddata->dev,
1592 "%s:Device already disconnected\n", __func__);
372d855f
TI		 1593 return 0;
1594 }
1595 buf_id = intelhaddata->curr_buf;
1596 intelhaddata->buff_done = buf_id;
1597 buff_done = intelhaddata->buff_done;
1598 buf_size = intelhaddata->buf_info[buf_id].buf_size;
1599 stream_type = had_stream->stream_type;
1600
372d855f
TI		 1601 /* Every debug statement has an implication
1602 * of ~5msec. Thus, avoid having >3 debug statements
1603 * for each buffer_done handling.
1604 */
1605
1606 /* Check for any intr_miss in case of active playback */
1607 if (had_stream->stream_type == HAD_RUNNING_STREAM) {
1608 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1609 intr_count = had_chk_intrmiss(intelhaddata, buf_id);
1610 if (!intr_count || (intr_count > 3)) {
c75b0476
TI		 1611 dev_err(intelhaddata->dev,
1612 "HAD SW state in non-recoverable mode\n");
372d855f
TI		 1613 return 0;
1614 }
1615 buf_id += (intr_count - 1);
1616 buf_id = buf_id % 4;
1617 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1618 }
1619
1620 intelhaddata->buf_info[buf_id].is_valid = true;
1621 if (intelhaddata->valid_buf_cnt-1 == buf_id) {
1622 if (had_stream->stream_type >= HAD_RUNNING_STREAM)
1623 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1624 } else
1625 intelhaddata->curr_buf = buf_id + 1;
1626
1627 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1628
1629 if (had_get_hwstate(intelhaddata)) {
c75b0476 1630 dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n");
372d855f
TI		 1631 return 0;
1632 }
1633
1634 /*Reprogram the registers with addr and length*/
1635 had_write_register(intelhaddata,
1636 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1637 buf_size);
1638 had_write_register(intelhaddata,
1639 AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH),
1640 intelhaddata->buf_info[buf_id].buf_addr |
1641 BIT(0) | BIT(1));
1642
1643 had_read_register(intelhaddata,
1644 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1645 &len);
c75b0476 1646 dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id);
372d855f
TI		 1647
1648 /* In case of actual data,
1649 * report buffer_done to above ALSA layer
1650 */
1651 buf_size = intelhaddata->buf_info[buf_id].buf_size;
1652 if (stream_type >= HAD_RUNNING_STREAM) {
1653 intelhaddata->stream_info.buffer_rendered +=
1654 (intr_count * buf_size);
1655 stream->period_elapsed(stream->had_substream);
1656 }
1657
1658 return 0;
1659}
1660
1661static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1662{
1663 enum intel_had_aud_buf_type buf_id;
1664 struct pcm_stream_info *stream;
1665 struct had_stream_data *had_stream;
1666 enum had_status_stream stream_type;
1667 unsigned long flag_irqs;
1668 int drv_status;
1669
1670 had_stream = &intelhaddata->stream_data;
1671 stream = &intelhaddata->stream_info;
1672
1673 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1674 buf_id = intelhaddata->curr_buf;
1675 stream_type = had_stream->stream_type;
1676 intelhaddata->buff_done = buf_id;
1677 drv_status = intelhaddata->drv_status;
1678 if (stream_type == HAD_RUNNING_STREAM)
1679 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1680
1681 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1682
c75b0476 1683 dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_type=%d\n",
372d855f
TI		 1684 __func__, buf_id, stream_type);
1685
1686 snd_intelhad_handle_underrun(intelhaddata);
1687
1688 if (drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI		 1689 dev_dbg(intelhaddata->dev,
1690 "%s:Device already disconnected\n", __func__);
372d855f
TI		 1691 return 0;
1692 }
1693
1694 if (stream_type == HAD_RUNNING_STREAM) {
1695 /* Report UNDERRUN error to above layers */
1696 intelhaddata->flag_underrun = 1;
1697 stream->period_elapsed(stream->had_substream);
1698 }
1699
1700 return 0;
1701}
1702
1703static int had_process_hot_plug(struct snd_intelhad *intelhaddata)
1704{
1705 enum intel_had_aud_buf_type buf_id;
1706 struct snd_pcm_substream *substream;
1707 struct had_stream_data *had_stream;
1708 unsigned long flag_irqs;
1709
372d855f
TI		 1710 substream = intelhaddata->stream_info.had_substream;
1711 had_stream = &intelhaddata->stream_data;
1712
1713 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1714 if (intelhaddata->drv_status == HAD_DRV_CONNECTED) {
c75b0476 1715 dev_dbg(intelhaddata->dev, "Device already connected\n");
372d855f
TI		 1716 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1717 return 0;
1718 }
1719 buf_id = intelhaddata->curr_buf;
1720 intelhaddata->buff_done = buf_id;
1721 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI		 1722 dev_dbg(intelhaddata->dev,
1723 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
372d855f
TI		 1724 __func__, __LINE__);
1725 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1726
c75b0476
TI		 1727 dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n",
1728 buf_id);
372d855f
TI		 1729
1730 /* Safety check */
1731 if (substream) {
c75b0476
TI		 1732 dev_dbg(intelhaddata->dev,
1733 "Force to stop the active stream by disconnection\n");
372d855f
TI		 1734 /* Set runtime->state to hw_params done */
1735 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1736 }
1737
1738 had_build_channel_allocation_map(intelhaddata);
1739
1740 return 0;
1741}
1742
1743static int had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1744{
1745 enum intel_had_aud_buf_type buf_id;
1746 struct had_stream_data *had_stream;
1747 unsigned long flag_irqs;
1748
372d855f
TI		 1749 had_stream = &intelhaddata->stream_data;
1750 buf_id = intelhaddata->curr_buf;
1751
1752 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1753
1754 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476 1755 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
372d855f
TI		 1756 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1757 return 0;
1758
1759 } else {
1760 /* Disable Audio */
1761 snd_intelhad_enable_audio_int(intelhaddata, false);
1762 snd_intelhad_enable_audio(intelhaddata, false);
1763 }
1764
1765 intelhaddata->drv_status = HAD_DRV_DISCONNECTED;
c75b0476
TI		 1766 dev_dbg(intelhaddata->dev,
1767 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f
TI		 1768 __func__, __LINE__);
1769
1770 /* Report to above ALSA layer */
1771 if (intelhaddata->stream_info.had_substream != NULL) {
1772 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
372d855f
TI		 1773 snd_pcm_stop(intelhaddata->stream_info.had_substream,
1774 SNDRV_PCM_STATE_SETUP);
1775 spin_lock_irqsave(&intelhaddata->had_spinlock, flag_irqs);
1776 }
1777
1778 had_stream->stream_type = HAD_INIT;
1779 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flag_irqs);
1780 kfree(intelhaddata->chmap->chmap);
1781 intelhaddata->chmap->chmap = NULL;
1782 intelhaddata->audio_reg_base = NULL;
372d855f
TI		 1783
1784 return 0;
1785}
1786
1787/* PCM operations structure and the calls back for the same */
1788static struct snd_pcm_ops snd_intelhad_playback_ops = {
5dab11d8
JA		 1789 .open = snd_intelhad_open,
1790 .close = snd_intelhad_close,
1791 .ioctl = snd_pcm_lib_ioctl,
1792 .hw_params = snd_intelhad_hw_params,
1793 .hw_free = snd_intelhad_hw_free,
1794 .prepare = snd_intelhad_pcm_prepare,
1795 .trigger = snd_intelhad_pcm_trigger,
1796 .pointer = snd_intelhad_pcm_pointer,
1797 .mmap = snd_intelhad_pcm_mmap,
1798};
1799
372d855f 1800/*
5dab11d8
JA		 1801 * snd_intelhad_pcm_free - to free the memory allocated
1802 *
1803 * @pcm: pointer to pcm instance
1804 * This function is called when the device is removed
1805 */
1806static void snd_intelhad_pcm_free(struct snd_pcm *pcm)
1807{
5dab11d8
JA		 1808 snd_pcm_lib_preallocate_free_for_all(pcm);
1809}
1810
1811static int had_iec958_info(struct snd_kcontrol *kcontrol,
1812 struct snd_ctl_elem_info *uinfo)
1813{
1814 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1815 uinfo->count = 1;
1816 return 0;
1817}
1818
1819static int had_iec958_get(struct snd_kcontrol *kcontrol,
1820 struct snd_ctl_elem_value *ucontrol)
1821{
1822 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1823
1824 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1825 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1826 ucontrol->value.iec958.status[2] =
1827 (intelhaddata->aes_bits >> 16) & 0xff;
1828 ucontrol->value.iec958.status[3] =
1829 (intelhaddata->aes_bits >> 24) & 0xff;
1830 return 0;
1831}
372d855f 1832
5dab11d8
JA		 1833static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1834 struct snd_ctl_elem_value *ucontrol)
1835{
1836 ucontrol->value.iec958.status[0] = 0xff;
1837 ucontrol->value.iec958.status[1] = 0xff;
1838 ucontrol->value.iec958.status[2] = 0xff;
1839 ucontrol->value.iec958.status[3] = 0xff;
1840 return 0;
1841}
372d855f 1842
5dab11d8
JA		 1843static int had_iec958_put(struct snd_kcontrol *kcontrol,
1844 struct snd_ctl_elem_value *ucontrol)
1845{
1846 unsigned int val;
1847 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1848
5dab11d8
JA		 1849 val = (ucontrol->value.iec958.status[0] << 0) |
1850 (ucontrol->value.iec958.status[1] << 8) |
1851 (ucontrol->value.iec958.status[2] << 16) |
1852 (ucontrol->value.iec958.status[3] << 24);
1853 if (intelhaddata->aes_bits != val) {
1854 intelhaddata->aes_bits = val;
1855 return 1;
1856 }
1857 return 1;
1858}
1859
1860static struct snd_kcontrol_new had_control_iec958_mask = {
1861 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1862 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1863 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1864 .info = had_iec958_info, /* shared */
1865 .get = had_iec958_mask_get,
1866};
1867
1868static struct snd_kcontrol_new had_control_iec958 = {
1869 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1870 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1871 .info = had_iec958_info,
1872 .get = had_iec958_get,
1873 .put = had_iec958_put
1874};
1875
da864809
TI		 1876static void _had_wq(struct work_struct *work)
1877{
1878 struct snd_intelhad *ctx =
1879 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1880
1881 had_process_hot_plug(ctx);
1882}
1883
1884static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1885{
1886 struct snd_intelhad *ctx = dev_id;
1887 u32 audio_stat, audio_reg;
1888
1889 audio_reg = AUD_HDMI_STATUS_v2;
1890 mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
1891
1892 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1893 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1894 had_process_buffer_underrun(ctx);
1895 }
1896
1897 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1898 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1899 had_process_buffer_done(ctx);
1900 }
1901
1902 return IRQ_HANDLED;
1903}
1904
1905static void notify_audio_lpe(struct platform_device *pdev)
1906{
1907 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1908 struct intel_hdmi_lpe_audio_pdata *pdata = pdev->dev.platform_data;
1909
1910 if (pdata->hdmi_connected != true) {
1911
1912 dev_dbg(&pdev->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1913 __func__);
1914
1915 if (ctx->state == hdmi_connector_status_connected) {
1916
1917 ctx->state = hdmi_connector_status_disconnected;
1918
1919 had_process_hot_unplug(ctx);
1920 } else
1921 dev_dbg(&pdev->dev, "%s: Already Unplugged!\n",
1922 __func__);
1923
1924 } else {
1925 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1926
1927 switch (eld->pipe_id) {
1928 case 0:
1929 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1930 break;
1931 case 1:
1932 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1933 break;
1934 case 2:
1935 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1936 break;
1937 default:
1938 dev_dbg(&pdev->dev, "Invalid pipe %d\n",
1939 eld->pipe_id);
1940 break;
1941 }
1942
1943 memcpy(&ctx->eld, eld->eld_data, sizeof(ctx->eld));
1944
1945 had_process_hot_plug(ctx);
1946
1947 ctx->state = hdmi_connector_status_connected;
1948
1949 dev_dbg(&pdev->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1950 __func__, eld->port_id, pdata->tmds_clock_speed);
1951
1952 if (pdata->tmds_clock_speed) {
1953 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1954 ctx->dp_output = pdata->dp_output;
1955 ctx->link_rate = pdata->link_rate;
1956
1957 /* Process mode change if stream is active */
1958 if (ctx->stream_data.stream_type == HAD_RUNNING_STREAM)
1959 hdmi_audio_mode_change(ctx);
1960 }
1961 }
1962}
1963
1964/* release resources */
1965static void hdmi_lpe_audio_free(struct snd_card *card)
1966{
1967 struct snd_intelhad *ctx = card->private_data;
1968
1969 if (ctx->mmio_start)
1970 iounmap(ctx->mmio_start);
1971 if (ctx->irq >= 0)
1972 free_irq(ctx->irq, ctx);
1973}
1974
79dda75a 1975/*
da864809 1976 * hdmi_lpe_audio_probe - start bridge with i915
5dab11d8 1977 *
da864809
TI		 1978 * This function is called when the i915 driver creates the
1979 * hdmi-lpe-audio platform device. Card creation is deferred until a
1980 * hot plug event is received
5dab11d8 1981 */
da864809 1982static int hdmi_lpe_audio_probe(struct platform_device *pdev)
5dab11d8 1983{
5dab11d8 1984 struct snd_card *card;
da864809
TI		 1985 struct snd_intelhad *ctx;
1986 struct snd_pcm *pcm;
1987 struct intel_hdmi_lpe_audio_pdata *pdata;
1988 int irq;
1989 struct resource *res_mmio;
1990 int ret;
1991 unsigned long flags;
1992
da864809
TI		 1993 dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask);
1994
1995 pdata = pdev->dev.platform_data;
1996 if (!pdata) {
1997 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1998 return -EINVAL;
1999 }
5dab11d8 2000
da864809
TI		 2001 /* get resources */
2002 irq = platform_get_irq(pdev, 0);
2003 if (irq < 0) {
2004 dev_err(&pdev->dev, "Could not get irq resource\n");
2005 return -ENODEV;
2006 }
2007
2008 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2009 if (!res_mmio) {
2010 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
2011 return -ENXIO;
2012 }
5dab11d8 2013
5647aec2 2014 /* create a card instance with ALSA framework */
da864809
TI		 2015 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
2016 THIS_MODULE, sizeof(*ctx), &card);
2017 if (ret)
2018 return ret;
2019
2020 ctx = card->private_data;
2021 spin_lock_init(&ctx->had_spinlock);
2022 ctx->drv_status = HAD_DRV_DISCONNECTED;
2023 ctx->dev = &pdev->dev;
2024 ctx->card = card;
2025 ctx->card_id = hdmi_card_id;
2026 ctx->card_index = card->number;
2027 ctx->flag_underrun = 0;
2028 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
2029 strcpy(card->driver, INTEL_HAD);
2030 strcpy(card->shortname, INTEL_HAD);
2031
2032 ctx->irq = -1;
2033 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
2034 INIT_WORK(&ctx->hdmi_audio_wq, _had_wq);
2035 ctx->state = hdmi_connector_status_disconnected;
2036
2037 card->private_free = hdmi_lpe_audio_free;
2038
2039 /* assume pipe A as default */
2040 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
2041
2042 platform_set_drvdata(pdev, ctx);
2043
2044 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
2045 __func__, (unsigned int)res_mmio->start,
2046 (unsigned int)res_mmio->end);
2047
2048 ctx->mmio_start = ioremap_nocache(res_mmio->start,
2049 (size_t)(resource_size(res_mmio)));
2050 if (!ctx->mmio_start) {
2051 dev_err(&pdev->dev, "Could not get ioremap\n");
2052 ret = -EACCES;
2053 goto err;
2054 }
5dab11d8 2055
da864809
TI		 2056 /* setup interrupt handler */
2057 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
2058 pdev->name, ctx);
2059 if (ret < 0) {
2060 dev_err(&pdev->dev, "request_irq failed\n");
2061 goto err;
2062 }
5dab11d8 2063
da864809
TI		 2064 ctx->irq = irq;
2065
2066 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
2067 MAX_CAP_STREAMS, &pcm);
2068 if (ret)
5dab11d8
JA		 2069 goto err;
2070
2071 /* setup private data which can be retrieved when required */
da864809 2072 pcm->private_data = ctx;
5dab11d8
JA		 2073 pcm->private_free = snd_intelhad_pcm_free;
2074 pcm->info_flags = 0;
2075 strncpy(pcm->name, card->shortname, strlen(card->shortname));
da864809 2076 /* setup the ops for playabck */
5dab11d8
JA		 2077 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
2078 &snd_intelhad_playback_ops);
2079 /* allocate dma pages for ALSA stream operations
2080 * memory allocated is based on size, not max value
2081 * thus using same argument for max & size
2082 */
da864809 2083 snd_pcm_lib_preallocate_pages_for_all(pcm,
5dab11d8
JA		 2084 SNDRV_DMA_TYPE_DEV, NULL,
2085 HAD_MAX_BUFFER, HAD_MAX_BUFFER);
5dab11d8 2086
5dab11d8 2087 /* IEC958 controls */
da864809
TI		 2088 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958_mask, ctx));
2089 if (ret < 0)
5dab11d8 2090 goto err;
da864809
TI		 2091 ret = snd_ctl_add(card, snd_ctl_new1(&had_control_iec958, ctx));
2092 if (ret < 0)
5dab11d8
JA		 2093 goto err;
2094
2095 init_channel_allocations();
2096
2097 /* Register channel map controls */
da864809
TI		 2098 ret = had_register_chmap_ctls(ctx, pcm);
2099 if (ret < 0)
5dab11d8
JA		 2100 goto err;
2101
da864809
TI		 2102 ret = snd_card_register(card);
2103 if (ret)
36ec0d99
TI		 2104 goto err;
2105
da864809
TI		 2106 spin_lock_irqsave(&pdata->lpe_audio_slock, flags);
2107 pdata->notify_audio_lpe = notify_audio_lpe;
2108 if (pdata->notify_pending) {
5dab11d8 2109
da864809
TI		 2110 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
2111 notify_audio_lpe(pdev);
2112 pdata->notify_pending = false;
2113 }
2114 spin_unlock_irqrestore(&pdata->lpe_audio_slock, flags);
2115
2116 pm_runtime_set_active(&pdev->dev);
2117 pm_runtime_enable(&pdev->dev);
2118
2119 schedule_work(&ctx->hdmi_audio_wq);
5dab11d8 2120
79dda75a 2121 return 0;
5647aec2 2122
5dab11d8
JA		 2123err:
2124 snd_card_free(card);
da864809 2125 return ret;
5dab11d8
JA		 2126}
2127
79dda75a 2128/*
da864809 2129 * hdmi_lpe_audio_remove - stop bridge with i915
5dab11d8 2130 *
da864809
TI		 2131 * This function is called when the platform device is destroyed. The sound
2132 * card should have been removed on hot plug event.
5dab11d8 2133 */
da864809 2134static int hdmi_lpe_audio_remove(struct platform_device *pdev)
5dab11d8 2135{
da864809 2136 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
5dab11d8 2137
da864809
TI		 2138 if (ctx->drv_status != HAD_DRV_DISCONNECTED)
2139 snd_intelhad_enable_audio_int(ctx, false);
2140 snd_card_free(ctx->card);
5dab11d8
JA		 2141 return 0;
2142}
2143
da864809
TI		 2144static struct platform_driver hdmi_lpe_audio_driver = {
2145 .driver = {
2146 .name = "hdmi-lpe-audio",
2147 },
2148 .probe = hdmi_lpe_audio_probe,
2149 .remove = hdmi_lpe_audio_remove,
2150 .suspend = hdmi_lpe_audio_suspend,
2151 .resume = hdmi_lpe_audio_resume
2152};
2153
2154module_platform_driver(hdmi_lpe_audio_driver);
2155MODULE_ALIAS("platform:hdmi_lpe_audio");
2156
5dab11d8
JA		 2157MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
2158MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
2159MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
2160MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
2161MODULE_DESCRIPTION("Intel HDMI Audio driver");
2162MODULE_LICENSE("GPL v2");
2163MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
ubuntu-bionic-kernel mirror