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1 | // Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M) |
2 | // | |
3 | // This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single | |
4 | // precision) floating point operations to hardware instructions. | |
5 | // | |
6 | // Additionally, this target uses the "hard" floating convention (ABI) where floating point values | |
7 | // are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.). | |
8 | // | |
416331ca | 9 | // To opt into double precision hardware support, use the `-C target-feature=+fp64` flag. |
c30ab7b3 | 10 | |
9fa01778 | 11 | use crate::spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult}; |
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12 | |
13 | pub fn target() -> TargetResult { | |
14 | Ok(Target { | |
15 | llvm_target: "thumbv7em-none-eabihf".to_string(), | |
16 | target_endian: "little".to_string(), | |
17 | target_pointer_width: "32".to_string(), | |
ea8adc8c | 18 | target_c_int_width: "32".to_string(), |
416331ca | 19 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(), |
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20 | arch: "arm".to_string(), |
21 | target_os: "none".to_string(), | |
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22 | target_env: String::new(), |
23 | target_vendor: String::new(), | |
24 | linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld), | |
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25 | |
26 | options: TargetOptions { | |
27 | // `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the | |
28 | // Cortex-M7 (vfp5) | |
416331ca | 29 | // `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers |
c30ab7b3 | 30 | // available |
416331ca | 31 | // `-fp64` The Cortex-M4 only supports single precision floating point operations |
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32 | // whereas in the Cortex-M7 double precision is optional |
33 | // | |
34 | // Reference: | |
35 | // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension | |
416331ca | 36 | features: "+vfp4,-d32,-fp64".to_string(), |
c30ab7b3 | 37 | max_atomic_width: Some(32), |
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38 | ..super::thumb_base::opts() |
39 | }, | |
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40 | }) |
41 | } |