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0731742a XL |
1 | // Targets the Cortex-M33 processor (Armv8-M Mainline architecture profile), |
2 | // with the Floating Point extension. | |
3 | ||
9fa01778 | 4 | use crate::spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult}; |
0731742a XL |
5 | |
6 | pub fn target() -> TargetResult { | |
7 | Ok(Target { | |
8 | llvm_target: "thumbv8m.main-none-eabihf".to_string(), | |
9 | target_endian: "little".to_string(), | |
10 | target_pointer_width: "32".to_string(), | |
11 | target_c_int_width: "32".to_string(), | |
416331ca | 12 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(), |
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13 | arch: "arm".to_string(), |
14 | target_os: "none".to_string(), | |
15 | target_env: String::new(), | |
16 | target_vendor: String::new(), | |
17 | linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld), | |
18 | ||
19 | options: TargetOptions { | |
20 | // If the Floating Point extension is implemented in the Cortex-M33 | |
21 | // processor, the Cortex-M33 Technical Reference Manual states that | |
22 | // the FPU uses the FPv5 architecture, single-precision instructions | |
23 | // and 16 D registers. | |
24 | // These parameters map to the following LLVM features. | |
416331ca | 25 | features: "+fp-armv8,-fp64,-d32".to_string(), |
0731742a | 26 | max_atomic_width: Some(32), |
dfeec247 | 27 | ..super::thumb_base::opts() |
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28 | }, |
29 | }) | |
30 | } |