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223e47cc LB |
1 | //===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file declares the CCState and CCValAssign classes, used for lowering | |
11 | // and implementing calling conventions. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H | |
16 | #define LLVM_CODEGEN_CALLINGCONVLOWER_H | |
17 | ||
18 | #include "llvm/ADT/SmallVector.h" | |
970d7e83 | 19 | #include "llvm/CodeGen/MachineFrameInfo.h" |
223e47cc | 20 | #include "llvm/CodeGen/MachineFunction.h" |
970d7e83 | 21 | #include "llvm/IR/CallingConv.h" |
223e47cc | 22 | #include "llvm/Target/TargetCallingConv.h" |
223e47cc LB |
23 | |
24 | namespace llvm { | |
1a4d82fc JJ |
25 | class CCState; |
26 | class MVT; | |
27 | class TargetMachine; | |
28 | class TargetRegisterInfo; | |
223e47cc LB |
29 | |
30 | /// CCValAssign - Represent assignment of one arg/retval to a location. | |
31 | class CCValAssign { | |
32 | public: | |
33 | enum LocInfo { | |
1a4d82fc JJ |
34 | Full, // The value fills the full location. |
35 | SExt, // The value is sign extended in the location. | |
36 | ZExt, // The value is zero extended in the location. | |
37 | AExt, // The value is extended with undefined upper bits. | |
38 | SExtUpper, // The value is in the upper bits of the location and should be | |
39 | // sign extended when retrieved. | |
40 | ZExtUpper, // The value is in the upper bits of the location and should be | |
41 | // zero extended when retrieved. | |
42 | AExtUpper, // The value is in the upper bits of the location and should be | |
43 | // extended with undefined upper bits when retrieved. | |
44 | BCvt, // The value is bit-converted in the location. | |
45 | VExt, // The value is vector-widened in the location. | |
46 | // FIXME: Not implemented yet. Code that uses AExt to mean | |
47 | // vector-widen should be fixed to use VExt instead. | |
48 | FPExt, // The floating-point value is fp-extended in the location. | |
49 | Indirect // The location contains pointer to the value. | |
223e47cc LB |
50 | // TODO: a subset of the value is in the location. |
51 | }; | |
1a4d82fc | 52 | |
223e47cc LB |
53 | private: |
54 | /// ValNo - This is the value number begin assigned (e.g. an argument number). | |
55 | unsigned ValNo; | |
56 | ||
57 | /// Loc is either a stack offset or a register number. | |
58 | unsigned Loc; | |
59 | ||
60 | /// isMem - True if this is a memory loc, false if it is a register loc. | |
970d7e83 | 61 | unsigned isMem : 1; |
223e47cc LB |
62 | |
63 | /// isCustom - True if this arg/retval requires special handling. | |
970d7e83 | 64 | unsigned isCustom : 1; |
223e47cc LB |
65 | |
66 | /// Information about how the value is assigned. | |
67 | LocInfo HTP : 6; | |
68 | ||
69 | /// ValVT - The type of the value being assigned. | |
70 | MVT ValVT; | |
71 | ||
72 | /// LocVT - The type of the location being assigned to. | |
73 | MVT LocVT; | |
74 | public: | |
75 | ||
76 | static CCValAssign getReg(unsigned ValNo, MVT ValVT, | |
77 | unsigned RegNo, MVT LocVT, | |
78 | LocInfo HTP) { | |
79 | CCValAssign Ret; | |
80 | Ret.ValNo = ValNo; | |
81 | Ret.Loc = RegNo; | |
82 | Ret.isMem = false; | |
83 | Ret.isCustom = false; | |
84 | Ret.HTP = HTP; | |
85 | Ret.ValVT = ValVT; | |
86 | Ret.LocVT = LocVT; | |
87 | return Ret; | |
88 | } | |
89 | ||
90 | static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, | |
91 | unsigned RegNo, MVT LocVT, | |
92 | LocInfo HTP) { | |
93 | CCValAssign Ret; | |
94 | Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP); | |
95 | Ret.isCustom = true; | |
96 | return Ret; | |
97 | } | |
98 | ||
99 | static CCValAssign getMem(unsigned ValNo, MVT ValVT, | |
100 | unsigned Offset, MVT LocVT, | |
101 | LocInfo HTP) { | |
102 | CCValAssign Ret; | |
103 | Ret.ValNo = ValNo; | |
104 | Ret.Loc = Offset; | |
105 | Ret.isMem = true; | |
106 | Ret.isCustom = false; | |
107 | Ret.HTP = HTP; | |
108 | Ret.ValVT = ValVT; | |
109 | Ret.LocVT = LocVT; | |
110 | return Ret; | |
111 | } | |
112 | ||
113 | static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, | |
114 | unsigned Offset, MVT LocVT, | |
115 | LocInfo HTP) { | |
116 | CCValAssign Ret; | |
117 | Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP); | |
118 | Ret.isCustom = true; | |
119 | return Ret; | |
120 | } | |
121 | ||
1a4d82fc JJ |
122 | // There is no need to differentiate between a pending CCValAssign and other |
123 | // kinds, as they are stored in a different list. | |
124 | static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, | |
125 | LocInfo HTP) { | |
126 | return getReg(ValNo, ValVT, 0, LocVT, HTP); | |
127 | } | |
128 | ||
129 | void convertToReg(unsigned RegNo) { | |
130 | Loc = RegNo; | |
131 | isMem = false; | |
132 | } | |
133 | ||
134 | void convertToMem(unsigned Offset) { | |
135 | Loc = Offset; | |
136 | isMem = true; | |
137 | } | |
138 | ||
223e47cc LB |
139 | unsigned getValNo() const { return ValNo; } |
140 | MVT getValVT() const { return ValVT; } | |
141 | ||
142 | bool isRegLoc() const { return !isMem; } | |
143 | bool isMemLoc() const { return isMem; } | |
144 | ||
145 | bool needsCustom() const { return isCustom; } | |
146 | ||
147 | unsigned getLocReg() const { assert(isRegLoc()); return Loc; } | |
148 | unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } | |
149 | MVT getLocVT() const { return LocVT; } | |
150 | ||
151 | LocInfo getLocInfo() const { return HTP; } | |
152 | bool isExtInLoc() const { | |
153 | return (HTP == AExt || HTP == SExt || HTP == ZExt); | |
154 | } | |
155 | ||
1a4d82fc JJ |
156 | bool isUpperBitsInLoc() const { |
157 | return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper; | |
158 | } | |
223e47cc LB |
159 | }; |
160 | ||
85aaf69f SL |
161 | /// Describes a register that needs to be forwarded from the prologue to a |
162 | /// musttail call. | |
163 | struct ForwardedRegister { | |
164 | ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) | |
165 | : VReg(VReg), PReg(PReg), VT(VT) {} | |
166 | unsigned VReg; | |
167 | MCPhysReg PReg; | |
168 | MVT VT; | |
169 | }; | |
170 | ||
223e47cc LB |
171 | /// CCAssignFn - This function assigns a location for Val, updating State to |
172 | /// reflect the change. It returns 'true' if it failed to handle Val. | |
173 | typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, | |
174 | MVT LocVT, CCValAssign::LocInfo LocInfo, | |
175 | ISD::ArgFlagsTy ArgFlags, CCState &State); | |
176 | ||
177 | /// CCCustomFn - This function assigns a location for Val, possibly updating | |
178 | /// all args to reflect changes and indicates if it handled it. It must set | |
179 | /// isCustom if it handles the arg and returns true. | |
180 | typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT, | |
181 | MVT &LocVT, CCValAssign::LocInfo &LocInfo, | |
182 | ISD::ArgFlagsTy &ArgFlags, CCState &State); | |
183 | ||
184 | /// ParmContext - This enum tracks whether calling convention lowering is in | |
185 | /// the context of prologue or call generation. Not all backends make use of | |
186 | /// this information. | |
187 | typedef enum { Unknown, Prologue, Call } ParmContext; | |
188 | ||
189 | /// CCState - This class holds information needed while lowering arguments and | |
190 | /// return values. It captures which registers are already assigned and which | |
191 | /// stack slots are used. It provides accessors to allocate these values. | |
192 | class CCState { | |
193 | private: | |
194 | CallingConv::ID CallingConv; | |
195 | bool IsVarArg; | |
196 | MachineFunction &MF; | |
223e47cc | 197 | const TargetRegisterInfo &TRI; |
1a4d82fc | 198 | SmallVectorImpl<CCValAssign> &Locs; |
223e47cc LB |
199 | LLVMContext &Context; |
200 | ||
201 | unsigned StackOffset; | |
202 | SmallVector<uint32_t, 16> UsedRegs; | |
1a4d82fc JJ |
203 | SmallVector<CCValAssign, 4> PendingLocs; |
204 | ||
205 | // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs: | |
206 | // | |
207 | // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers | |
208 | // tracking. | |
209 | // Or, in another words it tracks byval parameters that are stored in | |
210 | // general purpose registers. | |
211 | // | |
212 | // For 4 byte stack alignment, | |
213 | // instance index means byval parameter number in formal | |
214 | // arguments set. Assume, we have some "struct_type" with size = 4 bytes, | |
215 | // then, for function "foo": | |
216 | // | |
217 | // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t) | |
218 | // | |
219 | // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2) | |
220 | // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4). | |
221 | // | |
222 | // In case of 8 bytes stack alignment, | |
223 | // ByValRegs may also contain information about wasted registers. | |
224 | // In function shown above, r3 would be wasted according to AAPCS rules. | |
225 | // And in that case ByValRegs[1].Waste would be "true". | |
226 | // ByValRegs vector size still would be 2, | |
227 | // while "%t" goes to the stack: it wouldn't be described in ByValRegs. | |
228 | // | |
229 | // Supposed use-case for this collection: | |
85aaf69f | 230 | // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0. |
1a4d82fc JJ |
231 | // 2. HandleByVal fillups ByValRegs. |
232 | // 3. Argument analysis (LowerFormatArguments, for example). After | |
85aaf69f | 233 | // some byval argument was analyzed, InRegsParamsProcessed is increased. |
1a4d82fc JJ |
234 | struct ByValInfo { |
235 | ByValInfo(unsigned B, unsigned E, bool IsWaste = false) : | |
236 | Begin(B), End(E), Waste(IsWaste) {} | |
237 | // First register allocated for current parameter. | |
238 | unsigned Begin; | |
239 | ||
240 | // First after last register allocated for current parameter. | |
241 | unsigned End; | |
242 | ||
243 | // Means that current range of registers doesn't belong to any | |
244 | // parameters. It was wasted due to stack alignment rules. | |
245 | // For more information see: | |
246 | // AAPCS, 5.5 Parameter Passing, Stage C, C.3. | |
247 | bool Waste; | |
248 | }; | |
249 | SmallVector<ByValInfo, 4 > ByValRegs; | |
250 | ||
85aaf69f | 251 | // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed |
1a4d82fc | 252 | // during argument analysis. |
85aaf69f | 253 | unsigned InRegsParamsProcessed; |
223e47cc LB |
254 | |
255 | protected: | |
256 | ParmContext CallOrPrologue; | |
257 | ||
258 | public: | |
259 | CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, | |
1a4d82fc | 260 | SmallVectorImpl<CCValAssign> &locs, LLVMContext &C); |
223e47cc LB |
261 | |
262 | void addLoc(const CCValAssign &V) { | |
263 | Locs.push_back(V); | |
264 | } | |
265 | ||
266 | LLVMContext &getContext() const { return Context; } | |
223e47cc LB |
267 | MachineFunction &getMachineFunction() const { return MF; } |
268 | CallingConv::ID getCallingConv() const { return CallingConv; } | |
269 | bool isVarArg() const { return IsVarArg; } | |
270 | ||
271 | unsigned getNextStackOffset() const { return StackOffset; } | |
272 | ||
273 | /// isAllocated - Return true if the specified register (or an alias) is | |
274 | /// allocated. | |
275 | bool isAllocated(unsigned Reg) const { | |
276 | return UsedRegs[Reg/32] & (1 << (Reg&31)); | |
277 | } | |
278 | ||
279 | /// AnalyzeFormalArguments - Analyze an array of argument values, | |
280 | /// incorporating info about the formals into this state. | |
281 | void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, | |
282 | CCAssignFn Fn); | |
283 | ||
284 | /// AnalyzeReturn - Analyze the returned values of a return, | |
285 | /// incorporating info about the result values into this state. | |
286 | void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, | |
287 | CCAssignFn Fn); | |
288 | ||
289 | /// CheckReturn - Analyze the return values of a function, returning | |
290 | /// true if the return can be performed without sret-demotion, and | |
291 | /// false otherwise. | |
292 | bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, | |
293 | CCAssignFn Fn); | |
294 | ||
295 | /// AnalyzeCallOperands - Analyze the outgoing arguments to a call, | |
296 | /// incorporating info about the passed values into this state. | |
297 | void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, | |
298 | CCAssignFn Fn); | |
299 | ||
300 | /// AnalyzeCallOperands - Same as above except it takes vectors of types | |
301 | /// and argument flags. | |
302 | void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, | |
303 | SmallVectorImpl<ISD::ArgFlagsTy> &Flags, | |
304 | CCAssignFn Fn); | |
305 | ||
306 | /// AnalyzeCallResult - Analyze the return values of a call, | |
307 | /// incorporating info about the passed values into this state. | |
308 | void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, | |
309 | CCAssignFn Fn); | |
310 | ||
311 | /// AnalyzeCallResult - Same as above except it's specialized for calls which | |
312 | /// produce a single value. | |
313 | void AnalyzeCallResult(MVT VT, CCAssignFn Fn); | |
314 | ||
315 | /// getFirstUnallocated - Return the first unallocated register in the set, or | |
316 | /// NumRegs if they are all allocated. | |
1a4d82fc | 317 | unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const { |
223e47cc LB |
318 | for (unsigned i = 0; i != NumRegs; ++i) |
319 | if (!isAllocated(Regs[i])) | |
320 | return i; | |
321 | return NumRegs; | |
322 | } | |
323 | ||
324 | /// AllocateReg - Attempt to allocate one register. If it is not available, | |
325 | /// return zero. Otherwise, return the register, marking it and any aliases | |
326 | /// as allocated. | |
327 | unsigned AllocateReg(unsigned Reg) { | |
328 | if (isAllocated(Reg)) return 0; | |
329 | MarkAllocated(Reg); | |
330 | return Reg; | |
331 | } | |
332 | ||
333 | /// Version of AllocateReg with extra register to be shadowed. | |
334 | unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { | |
335 | if (isAllocated(Reg)) return 0; | |
336 | MarkAllocated(Reg); | |
337 | MarkAllocated(ShadowReg); | |
338 | return Reg; | |
339 | } | |
340 | ||
341 | /// AllocateReg - Attempt to allocate one of the specified registers. If none | |
342 | /// are available, return zero. Otherwise, return the first one available, | |
343 | /// marking it and any aliases as allocated. | |
1a4d82fc | 344 | unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) { |
223e47cc LB |
345 | unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); |
346 | if (FirstUnalloc == NumRegs) | |
347 | return 0; // Didn't find the reg. | |
348 | ||
349 | // Mark the register and any aliases as allocated. | |
350 | unsigned Reg = Regs[FirstUnalloc]; | |
351 | MarkAllocated(Reg); | |
352 | return Reg; | |
353 | } | |
354 | ||
1a4d82fc JJ |
355 | /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive |
356 | /// registers. If this is not possible, return zero. Otherwise, return the first | |
357 | /// register of the block that were allocated, marking the entire block as allocated. | |
85aaf69f SL |
358 | unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) { |
359 | if (RegsRequired > Regs.size()) | |
360 | return 0; | |
361 | ||
362 | for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired; | |
363 | ++StartIdx) { | |
1a4d82fc JJ |
364 | bool BlockAvailable = true; |
365 | // Check for already-allocated regs in this block | |
366 | for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) { | |
367 | if (isAllocated(Regs[StartIdx + BlockIdx])) { | |
368 | BlockAvailable = false; | |
369 | break; | |
370 | } | |
371 | } | |
372 | if (BlockAvailable) { | |
373 | // Mark the entire block as allocated | |
374 | for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) { | |
375 | MarkAllocated(Regs[StartIdx + BlockIdx]); | |
376 | } | |
377 | return Regs[StartIdx]; | |
378 | } | |
379 | } | |
380 | // No block was available | |
381 | return 0; | |
382 | } | |
383 | ||
223e47cc | 384 | /// Version of AllocateReg with list of registers to be shadowed. |
1a4d82fc | 385 | unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs, |
223e47cc LB |
386 | unsigned NumRegs) { |
387 | unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); | |
388 | if (FirstUnalloc == NumRegs) | |
389 | return 0; // Didn't find the reg. | |
390 | ||
391 | // Mark the register and any aliases as allocated. | |
392 | unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; | |
393 | MarkAllocated(Reg); | |
394 | MarkAllocated(ShadowReg); | |
395 | return Reg; | |
396 | } | |
397 | ||
398 | /// AllocateStack - Allocate a chunk of stack space with the specified size | |
399 | /// and alignment. | |
400 | unsigned AllocateStack(unsigned Size, unsigned Align) { | |
1a4d82fc JJ |
401 | assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2. |
402 | StackOffset = ((StackOffset + Align - 1) & ~(Align - 1)); | |
223e47cc LB |
403 | unsigned Result = StackOffset; |
404 | StackOffset += Size; | |
970d7e83 | 405 | MF.getFrameInfo()->ensureMaxAlignment(Align); |
223e47cc LB |
406 | return Result; |
407 | } | |
408 | ||
409 | /// Version of AllocateStack with extra register to be shadowed. | |
410 | unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) { | |
411 | MarkAllocated(ShadowReg); | |
412 | return AllocateStack(Size, Align); | |
413 | } | |
414 | ||
1a4d82fc JJ |
415 | /// Version of AllocateStack with list of extra registers to be shadowed. |
416 | /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers. | |
417 | unsigned AllocateStack(unsigned Size, unsigned Align, | |
418 | const MCPhysReg *ShadowRegs, unsigned NumShadowRegs) { | |
419 | for (unsigned i = 0; i < NumShadowRegs; ++i) | |
420 | MarkAllocated(ShadowRegs[i]); | |
421 | return AllocateStack(Size, Align); | |
422 | } | |
423 | ||
223e47cc LB |
424 | // HandleByVal - Allocate a stack slot large enough to pass an argument by |
425 | // value. The size and alignment information of the argument is encoded in its | |
426 | // parameter attribute. | |
427 | void HandleByVal(unsigned ValNo, MVT ValVT, | |
428 | MVT LocVT, CCValAssign::LocInfo LocInfo, | |
429 | int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags); | |
430 | ||
1a4d82fc JJ |
431 | // Returns count of byval arguments that are to be stored (even partly) |
432 | // in registers. | |
433 | unsigned getInRegsParamsCount() const { return ByValRegs.size(); } | |
434 | ||
435 | // Returns count of byval in-regs arguments proceed. | |
85aaf69f | 436 | unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; } |
1a4d82fc JJ |
437 | |
438 | // Get information about N-th byval parameter that is stored in registers. | |
439 | // Here "ByValParamIndex" is N. | |
440 | void getInRegsParamInfo(unsigned InRegsParamRecordIndex, | |
441 | unsigned& BeginReg, unsigned& EndReg) const { | |
442 | assert(InRegsParamRecordIndex < ByValRegs.size() && | |
443 | "Wrong ByVal parameter index"); | |
444 | ||
445 | const ByValInfo& info = ByValRegs[InRegsParamRecordIndex]; | |
446 | BeginReg = info.Begin; | |
447 | EndReg = info.End; | |
448 | } | |
449 | ||
450 | // Add information about parameter that is kept in registers. | |
451 | void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) { | |
452 | ByValRegs.push_back(ByValInfo(RegBegin, RegEnd)); | |
453 | } | |
454 | ||
455 | // Goes either to next byval parameter (excluding "waste" record), or | |
456 | // to the end of collection. | |
457 | // Returns false, if end is reached. | |
458 | bool nextInRegsParam() { | |
459 | unsigned e = ByValRegs.size(); | |
85aaf69f SL |
460 | if (InRegsParamsProcessed < e) |
461 | ++InRegsParamsProcessed; | |
462 | return InRegsParamsProcessed < e; | |
1a4d82fc JJ |
463 | } |
464 | ||
465 | // Clear byval registers tracking info. | |
466 | void clearByValRegsInfo() { | |
85aaf69f | 467 | InRegsParamsProcessed = 0; |
1a4d82fc JJ |
468 | ByValRegs.clear(); |
469 | } | |
470 | ||
471 | // Rewind byval registers tracking info. | |
472 | void rewindByValRegsInfo() { | |
85aaf69f | 473 | InRegsParamsProcessed = 0; |
1a4d82fc | 474 | } |
223e47cc LB |
475 | |
476 | ParmContext getCallOrPrologue() const { return CallOrPrologue; } | |
477 | ||
1a4d82fc JJ |
478 | // Get list of pending assignments |
479 | SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() { | |
480 | return PendingLocs; | |
481 | } | |
482 | ||
85aaf69f SL |
483 | /// Compute the remaining unused register parameters that would be used for |
484 | /// the given value type. This is useful when varargs are passed in the | |
485 | /// registers that normal prototyped parameters would be passed in, or for | |
486 | /// implementing perfect forwarding. | |
487 | void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT, | |
488 | CCAssignFn Fn); | |
489 | ||
490 | /// Compute the set of registers that need to be preserved and forwarded to | |
491 | /// any musttail calls. | |
492 | void analyzeMustTailForwardedRegisters( | |
493 | SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes, | |
494 | CCAssignFn Fn); | |
495 | ||
223e47cc LB |
496 | private: |
497 | /// MarkAllocated - Mark a register and all of its aliases as allocated. | |
498 | void MarkAllocated(unsigned Reg); | |
499 | }; | |
500 | ||
501 | ||
502 | ||
503 | } // end namespace llvm | |
504 | ||
505 | #endif |