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1 | //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file defines all of the AARCH64-specific intrinsics. | |
11 | // | |
12 | //===----------------------------------------------------------------------===// | |
13 | ||
14 | let TargetPrefix = "aarch64" in { | |
15 | ||
16 | def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; | |
17 | def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; | |
18 | def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; | |
19 | def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; | |
20 | ||
21 | def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; | |
22 | def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; | |
23 | def int_aarch64_stxp : Intrinsic<[llvm_i32_ty], | |
24 | [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; | |
25 | def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty], | |
26 | [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; | |
27 | ||
28 | def int_aarch64_clrex : Intrinsic<[]>; | |
29 | ||
30 | def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, | |
31 | LLVMMatchType<0>], [IntrNoMem]>; | |
32 | def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, | |
33 | LLVMMatchType<0>], [IntrNoMem]>; | |
34 | ||
35 | //===----------------------------------------------------------------------===// | |
36 | // HINT | |
37 | ||
38 | def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>; | |
39 | ||
40 | //===----------------------------------------------------------------------===// | |
41 | // RBIT | |
42 | ||
43 | def int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], | |
44 | [IntrNoMem]>; | |
45 | ||
46 | //===----------------------------------------------------------------------===// | |
47 | // Data Barrier Instructions | |
48 | ||
49 | def int_aarch64_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>; | |
50 | def int_aarch64_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>; | |
51 | def int_aarch64_isb : GCCBuiltin<"__builtin_arm_isb">, Intrinsic<[], [llvm_i32_ty]>; | |
52 | ||
53 | } | |
54 | ||
55 | //===----------------------------------------------------------------------===// | |
56 | // Advanced SIMD (NEON) | |
57 | ||
58 | let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". | |
59 | class AdvSIMD_2Scalar_Float_Intrinsic | |
60 | : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], | |
61 | [IntrNoMem]>; | |
62 | ||
63 | class AdvSIMD_FPToIntRounding_Intrinsic | |
64 | : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; | |
65 | ||
66 | class AdvSIMD_1IntArg_Intrinsic | |
67 | : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; | |
68 | class AdvSIMD_1FloatArg_Intrinsic | |
69 | : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; | |
70 | class AdvSIMD_1VectorArg_Intrinsic | |
71 | : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; | |
72 | class AdvSIMD_1VectorArg_Expand_Intrinsic | |
73 | : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; | |
74 | class AdvSIMD_1VectorArg_Long_Intrinsic | |
75 | : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; | |
76 | class AdvSIMD_1IntArg_Narrow_Intrinsic | |
77 | : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>; | |
78 | class AdvSIMD_1VectorArg_Narrow_Intrinsic | |
79 | : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>; | |
80 | class AdvSIMD_1VectorArg_Int_Across_Intrinsic | |
81 | : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>; | |
82 | class AdvSIMD_1VectorArg_Float_Across_Intrinsic | |
83 | : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>; | |
84 | ||
85 | class AdvSIMD_2IntArg_Intrinsic | |
86 | : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], | |
87 | [IntrNoMem]>; | |
88 | class AdvSIMD_2FloatArg_Intrinsic | |
89 | : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], | |
90 | [IntrNoMem]>; | |
91 | class AdvSIMD_2VectorArg_Intrinsic | |
92 | : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], | |
93 | [IntrNoMem]>; | |
94 | class AdvSIMD_2VectorArg_Compare_Intrinsic | |
95 | : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], | |
96 | [IntrNoMem]>; | |
97 | class AdvSIMD_2Arg_FloatCompare_Intrinsic | |
98 | : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>], | |
99 | [IntrNoMem]>; | |
100 | class AdvSIMD_2VectorArg_Long_Intrinsic | |
101 | : Intrinsic<[llvm_anyvector_ty], | |
102 | [LLVMTruncatedType<0>, LLVMTruncatedType<0>], | |
103 | [IntrNoMem]>; | |
104 | class AdvSIMD_2VectorArg_Wide_Intrinsic | |
105 | : Intrinsic<[llvm_anyvector_ty], | |
106 | [LLVMMatchType<0>, LLVMTruncatedType<0>], | |
107 | [IntrNoMem]>; | |
108 | class AdvSIMD_2VectorArg_Narrow_Intrinsic | |
109 | : Intrinsic<[llvm_anyvector_ty], | |
110 | [LLVMExtendedType<0>, LLVMExtendedType<0>], | |
111 | [IntrNoMem]>; | |
112 | class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic | |
113 | : Intrinsic<[llvm_anyint_ty], | |
114 | [LLVMExtendedType<0>, llvm_i32_ty], | |
115 | [IntrNoMem]>; | |
116 | class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic | |
117 | : Intrinsic<[llvm_anyvector_ty], | |
118 | [llvm_anyvector_ty], | |
119 | [IntrNoMem]>; | |
120 | class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic | |
121 | : Intrinsic<[llvm_anyvector_ty], | |
122 | [LLVMTruncatedType<0>], | |
123 | [IntrNoMem]>; | |
124 | class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic | |
125 | : Intrinsic<[llvm_anyvector_ty], | |
126 | [LLVMTruncatedType<0>, llvm_i32_ty], | |
127 | [IntrNoMem]>; | |
128 | class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic | |
129 | : Intrinsic<[llvm_anyvector_ty], | |
130 | [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty], | |
131 | [IntrNoMem]>; | |
132 | ||
133 | class AdvSIMD_3VectorArg_Intrinsic | |
134 | : Intrinsic<[llvm_anyvector_ty], | |
135 | [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], | |
136 | [IntrNoMem]>; | |
137 | class AdvSIMD_3VectorArg_Scalar_Intrinsic | |
138 | : Intrinsic<[llvm_anyvector_ty], | |
139 | [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], | |
140 | [IntrNoMem]>; | |
141 | class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic | |
142 | : Intrinsic<[llvm_anyvector_ty], | |
143 | [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, | |
144 | LLVMMatchType<1>], [IntrNoMem]>; | |
145 | class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic | |
146 | : Intrinsic<[llvm_anyvector_ty], | |
147 | [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty], | |
148 | [IntrNoMem]>; | |
149 | class AdvSIMD_CvtFxToFP_Intrinsic | |
150 | : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], | |
151 | [IntrNoMem]>; | |
152 | class AdvSIMD_CvtFPToFx_Intrinsic | |
153 | : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], | |
154 | [IntrNoMem]>; | |
155 | } | |
156 | ||
157 | // Arithmetic ops | |
158 | ||
159 | let Properties = [IntrNoMem] in { | |
160 | // Vector Add Across Lanes | |
161 | def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
162 | def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
163 | def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; | |
164 | ||
165 | // Vector Long Add Across Lanes | |
166 | def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
167 | def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
168 | ||
169 | // Vector Halving Add | |
170 | def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic; | |
171 | def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic; | |
172 | ||
173 | // Vector Rounding Halving Add | |
174 | def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic; | |
175 | def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic; | |
176 | ||
177 | // Vector Saturating Add | |
178 | def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic; | |
179 | def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic; | |
180 | def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic; | |
181 | def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic; | |
182 | ||
183 | // Vector Add High-Half | |
184 | // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that | |
185 | // header is no longer supported. | |
186 | def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; | |
187 | ||
188 | // Vector Rounding Add High-Half | |
189 | def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; | |
190 | ||
191 | // Vector Saturating Doubling Multiply High | |
192 | def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic; | |
193 | ||
194 | // Vector Saturating Rounding Doubling Multiply High | |
195 | def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic; | |
196 | ||
197 | // Vector Polynominal Multiply | |
198 | def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic; | |
199 | ||
200 | // Vector Long Multiply | |
201 | def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic; | |
202 | def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic; | |
203 | def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic; | |
204 | ||
205 | // 64-bit polynomial multiply really returns an i128, which is not legal. Fake | |
206 | // it with a v16i8. | |
207 | def int_aarch64_neon_pmull64 : | |
208 | Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; | |
209 | ||
210 | // Vector Extending Multiply | |
211 | def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic { | |
212 | let Properties = [IntrNoMem, Commutative]; | |
213 | } | |
214 | ||
215 | // Vector Saturating Doubling Long Multiply | |
216 | def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic; | |
217 | def int_aarch64_neon_sqdmulls_scalar | |
218 | : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; | |
219 | ||
220 | // Vector Halving Subtract | |
221 | def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic; | |
222 | def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic; | |
223 | ||
224 | // Vector Saturating Subtract | |
225 | def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic; | |
226 | def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic; | |
227 | ||
228 | // Vector Subtract High-Half | |
229 | // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that | |
230 | // header is no longer supported. | |
231 | def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; | |
232 | ||
233 | // Vector Rounding Subtract High-Half | |
234 | def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; | |
235 | ||
236 | // Vector Compare Absolute Greater-than-or-equal | |
237 | def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic; | |
238 | ||
239 | // Vector Compare Absolute Greater-than | |
240 | def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic; | |
241 | ||
242 | // Vector Absolute Difference | |
243 | def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic; | |
244 | def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic; | |
245 | def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic; | |
246 | ||
247 | // Scalar Absolute Difference | |
248 | def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic; | |
249 | ||
250 | // Vector Max | |
251 | def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic; | |
252 | def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic; | |
253 | def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic; | |
254 | def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic; | |
255 | ||
256 | // Vector Max Across Lanes | |
257 | def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
258 | def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
259 | def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; | |
260 | def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; | |
261 | ||
262 | // Vector Min | |
263 | def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic; | |
264 | def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic; | |
265 | def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic; | |
266 | def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic; | |
267 | ||
268 | // Vector Min/Max Number | |
269 | def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic; | |
270 | def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic; | |
271 | ||
272 | // Vector Min Across Lanes | |
273 | def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
274 | def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; | |
275 | def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; | |
276 | def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; | |
277 | ||
278 | // Pairwise Add | |
279 | def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic; | |
280 | ||
281 | // Long Pairwise Add | |
282 | // FIXME: In theory, we shouldn't need intrinsics for saddlp or | |
283 | // uaddlp, but tblgen's type inference currently can't handle the | |
284 | // pattern fragments this ends up generating. | |
285 | def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; | |
286 | def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; | |
287 | ||
288 | // Folding Maximum | |
289 | def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic; | |
290 | def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic; | |
291 | def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic; | |
292 | ||
293 | // Folding Minimum | |
294 | def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic; | |
295 | def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic; | |
296 | def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic; | |
297 | ||
298 | // Reciprocal Estimate/Step | |
299 | def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic; | |
300 | def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic; | |
301 | ||
302 | // Reciprocal Exponent | |
303 | def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic; | |
304 | ||
305 | // Vector Saturating Shift Left | |
306 | def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic; | |
307 | def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic; | |
308 | ||
309 | // Vector Rounding Shift Left | |
310 | def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic; | |
311 | def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic; | |
312 | ||
313 | // Vector Saturating Rounding Shift Left | |
314 | def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic; | |
315 | def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic; | |
316 | ||
317 | // Vector Signed->Unsigned Shift Left by Constant | |
318 | def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic; | |
319 | ||
320 | // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant | |
321 | def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
322 | ||
323 | // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const | |
324 | def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
325 | ||
326 | // Vector Narrowing Shift Right by Constant | |
327 | def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
328 | def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
329 | ||
330 | // Vector Rounding Narrowing Shift Right by Constant | |
331 | def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
332 | ||
333 | // Vector Rounding Narrowing Saturating Shift Right by Constant | |
334 | def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
335 | def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; | |
336 | ||
337 | // Vector Shift Left | |
338 | def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic; | |
339 | def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic; | |
340 | ||
341 | // Vector Widening Shift Left by Constant | |
342 | def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic; | |
343 | def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; | |
344 | def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; | |
345 | ||
346 | // Vector Shift Right by Constant and Insert | |
347 | def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic; | |
348 | ||
349 | // Vector Shift Left by Constant and Insert | |
350 | def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic; | |
351 | ||
352 | // Vector Saturating Narrow | |
353 | def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic; | |
354 | def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic; | |
355 | def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; | |
356 | def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; | |
357 | ||
358 | // Vector Saturating Extract and Unsigned Narrow | |
359 | def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic; | |
360 | def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic; | |
361 | ||
362 | // Vector Absolute Value | |
363 | def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic; | |
364 | ||
365 | // Vector Saturating Absolute Value | |
366 | def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic; | |
367 | ||
368 | // Vector Saturating Negation | |
369 | def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic; | |
370 | ||
371 | // Vector Count Leading Sign Bits | |
372 | def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic; | |
373 | ||
374 | // Vector Reciprocal Estimate | |
375 | def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic; | |
376 | def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic; | |
377 | ||
378 | // Vector Square Root Estimate | |
379 | def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic; | |
380 | def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic; | |
381 | ||
382 | // Vector Bitwise Reverse | |
383 | def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic; | |
384 | ||
385 | // Vector Conversions Between Half-Precision and Single-Precision. | |
386 | def int_aarch64_neon_vcvtfp2hf | |
387 | : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; | |
388 | def int_aarch64_neon_vcvthf2fp | |
389 | : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; | |
390 | ||
391 | // Vector Conversions Between Floating-point and Fixed-point. | |
392 | def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic; | |
393 | def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic; | |
394 | def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic; | |
395 | def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic; | |
396 | ||
397 | // Vector FP->Int Conversions | |
398 | def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic; | |
399 | def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic; | |
400 | def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic; | |
401 | def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic; | |
402 | def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic; | |
403 | def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic; | |
404 | def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic; | |
405 | def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic; | |
406 | def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic; | |
407 | def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic; | |
408 | ||
409 | // Vector FP Rounding: only ties to even is unrepresented by a normal | |
410 | // intrinsic. | |
411 | def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic; | |
412 | ||
413 | // Scalar FP->Int conversions | |
414 | ||
415 | // Vector FP Inexact Narrowing | |
416 | def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic; | |
417 | ||
418 | // Scalar FP Inexact Narrowing | |
419 | def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty], | |
420 | [IntrNoMem]>; | |
421 | } | |
422 | ||
423 | let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". | |
424 | class AdvSIMD_2Vector2Index_Intrinsic | |
425 | : Intrinsic<[llvm_anyvector_ty], | |
426 | [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty], | |
427 | [IntrNoMem]>; | |
428 | } | |
429 | ||
430 | // Vector element to element moves | |
431 | def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic; | |
432 | ||
433 | let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". | |
434 | class AdvSIMD_1Vec_Load_Intrinsic | |
435 | : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>], | |
436 | [IntrReadArgMem]>; | |
437 | class AdvSIMD_1Vec_Store_Lane_Intrinsic | |
438 | : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], | |
439 | [IntrReadWriteArgMem, NoCapture<2>]>; | |
440 | ||
441 | class AdvSIMD_2Vec_Load_Intrinsic | |
442 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], | |
443 | [LLVMAnyPointerType<LLVMMatchType<0>>], | |
444 | [IntrReadArgMem]>; | |
445 | class AdvSIMD_2Vec_Load_Lane_Intrinsic | |
446 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], | |
447 | [LLVMMatchType<0>, LLVMMatchType<0>, | |
448 | llvm_i64_ty, llvm_anyptr_ty], | |
449 | [IntrReadArgMem]>; | |
450 | class AdvSIMD_2Vec_Store_Intrinsic | |
451 | : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, | |
452 | LLVMAnyPointerType<LLVMMatchType<0>>], | |
453 | [IntrReadWriteArgMem, NoCapture<2>]>; | |
454 | class AdvSIMD_2Vec_Store_Lane_Intrinsic | |
455 | : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, | |
456 | llvm_i64_ty, llvm_anyptr_ty], | |
457 | [IntrReadWriteArgMem, NoCapture<3>]>; | |
458 | ||
459 | class AdvSIMD_3Vec_Load_Intrinsic | |
460 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>], | |
461 | [LLVMAnyPointerType<LLVMMatchType<0>>], | |
462 | [IntrReadArgMem]>; | |
463 | class AdvSIMD_3Vec_Load_Lane_Intrinsic | |
464 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>], | |
465 | [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, | |
466 | llvm_i64_ty, llvm_anyptr_ty], | |
467 | [IntrReadArgMem]>; | |
468 | class AdvSIMD_3Vec_Store_Intrinsic | |
469 | : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, | |
470 | LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>], | |
471 | [IntrReadWriteArgMem, NoCapture<3>]>; | |
472 | class AdvSIMD_3Vec_Store_Lane_Intrinsic | |
473 | : Intrinsic<[], [llvm_anyvector_ty, | |
474 | LLVMMatchType<0>, LLVMMatchType<0>, | |
475 | llvm_i64_ty, llvm_anyptr_ty], | |
476 | [IntrReadWriteArgMem, NoCapture<4>]>; | |
477 | ||
478 | class AdvSIMD_4Vec_Load_Intrinsic | |
479 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, | |
480 | LLVMMatchType<0>, LLVMMatchType<0>], | |
481 | [LLVMAnyPointerType<LLVMMatchType<0>>], | |
482 | [IntrReadArgMem]>; | |
483 | class AdvSIMD_4Vec_Load_Lane_Intrinsic | |
484 | : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, | |
485 | LLVMMatchType<0>, LLVMMatchType<0>], | |
486 | [LLVMMatchType<0>, LLVMMatchType<0>, | |
487 | LLVMMatchType<0>, LLVMMatchType<0>, | |
488 | llvm_i64_ty, llvm_anyptr_ty], | |
489 | [IntrReadArgMem]>; | |
490 | class AdvSIMD_4Vec_Store_Intrinsic | |
491 | : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, | |
492 | LLVMMatchType<0>, LLVMMatchType<0>, | |
493 | LLVMAnyPointerType<LLVMMatchType<0>>], | |
494 | [IntrReadWriteArgMem, NoCapture<4>]>; | |
495 | class AdvSIMD_4Vec_Store_Lane_Intrinsic | |
496 | : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, | |
497 | LLVMMatchType<0>, LLVMMatchType<0>, | |
498 | llvm_i64_ty, llvm_anyptr_ty], | |
499 | [IntrReadWriteArgMem, NoCapture<5>]>; | |
500 | } | |
501 | ||
502 | // Memory ops | |
503 | ||
504 | def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic; | |
505 | def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic; | |
506 | def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic; | |
507 | ||
508 | def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic; | |
509 | def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic; | |
510 | def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic; | |
511 | ||
512 | def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic; | |
513 | def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic; | |
514 | def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic; | |
515 | ||
516 | def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic; | |
517 | def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic; | |
518 | def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic; | |
519 | ||
520 | def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic; | |
521 | def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic; | |
522 | def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic; | |
523 | ||
524 | def int_aarch64_neon_st2 : AdvSIMD_2Vec_Store_Intrinsic; | |
525 | def int_aarch64_neon_st3 : AdvSIMD_3Vec_Store_Intrinsic; | |
526 | def int_aarch64_neon_st4 : AdvSIMD_4Vec_Store_Intrinsic; | |
527 | ||
528 | def int_aarch64_neon_st2lane : AdvSIMD_2Vec_Store_Lane_Intrinsic; | |
529 | def int_aarch64_neon_st3lane : AdvSIMD_3Vec_Store_Lane_Intrinsic; | |
530 | def int_aarch64_neon_st4lane : AdvSIMD_4Vec_Store_Lane_Intrinsic; | |
531 | ||
532 | let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". | |
533 | class AdvSIMD_Tbl1_Intrinsic | |
534 | : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>], | |
535 | [IntrNoMem]>; | |
536 | class AdvSIMD_Tbl2_Intrinsic | |
537 | : Intrinsic<[llvm_anyvector_ty], | |
538 | [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; | |
539 | class AdvSIMD_Tbl3_Intrinsic | |
540 | : Intrinsic<[llvm_anyvector_ty], | |
541 | [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, | |
542 | LLVMMatchType<0>], | |
543 | [IntrNoMem]>; | |
544 | class AdvSIMD_Tbl4_Intrinsic | |
545 | : Intrinsic<[llvm_anyvector_ty], | |
546 | [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, | |
547 | LLVMMatchType<0>], | |
548 | [IntrNoMem]>; | |
549 | ||
550 | class AdvSIMD_Tbx1_Intrinsic | |
551 | : Intrinsic<[llvm_anyvector_ty], | |
552 | [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>], | |
553 | [IntrNoMem]>; | |
554 | class AdvSIMD_Tbx2_Intrinsic | |
555 | : Intrinsic<[llvm_anyvector_ty], | |
556 | [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, | |
557 | LLVMMatchType<0>], | |
558 | [IntrNoMem]>; | |
559 | class AdvSIMD_Tbx3_Intrinsic | |
560 | : Intrinsic<[llvm_anyvector_ty], | |
561 | [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, | |
562 | llvm_v16i8_ty, LLVMMatchType<0>], | |
563 | [IntrNoMem]>; | |
564 | class AdvSIMD_Tbx4_Intrinsic | |
565 | : Intrinsic<[llvm_anyvector_ty], | |
566 | [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, | |
567 | llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], | |
568 | [IntrNoMem]>; | |
569 | } | |
570 | def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic; | |
571 | def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic; | |
572 | def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic; | |
573 | def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic; | |
574 | ||
575 | def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic; | |
576 | def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic; | |
577 | def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic; | |
578 | def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic; | |
579 | ||
580 | let TargetPrefix = "aarch64" in { | |
581 | class Crypto_AES_DataKey_Intrinsic | |
582 | : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; | |
583 | ||
584 | class Crypto_AES_Data_Intrinsic | |
585 | : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; | |
586 | ||
587 | // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule | |
588 | // (v4i32). | |
589 | class Crypto_SHA_5Hash4Schedule_Intrinsic | |
590 | : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], | |
591 | [IntrNoMem]>; | |
592 | ||
593 | // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule | |
594 | // (v4i32). | |
595 | class Crypto_SHA_1Hash_Intrinsic | |
596 | : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; | |
597 | ||
598 | // SHA intrinsic taking 8 words of the schedule | |
599 | class Crypto_SHA_8Schedule_Intrinsic | |
600 | : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; | |
601 | ||
602 | // SHA intrinsic taking 12 words of the schedule | |
603 | class Crypto_SHA_12Schedule_Intrinsic | |
604 | : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], | |
605 | [IntrNoMem]>; | |
606 | ||
607 | // SHA intrinsic taking 8 words of the hash and 4 of the schedule. | |
608 | class Crypto_SHA_8Hash4Schedule_Intrinsic | |
609 | : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], | |
610 | [IntrNoMem]>; | |
611 | } | |
612 | ||
613 | // AES | |
614 | def int_aarch64_crypto_aese : Crypto_AES_DataKey_Intrinsic; | |
615 | def int_aarch64_crypto_aesd : Crypto_AES_DataKey_Intrinsic; | |
616 | def int_aarch64_crypto_aesmc : Crypto_AES_Data_Intrinsic; | |
617 | def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic; | |
618 | ||
619 | // SHA1 | |
620 | def int_aarch64_crypto_sha1c : Crypto_SHA_5Hash4Schedule_Intrinsic; | |
621 | def int_aarch64_crypto_sha1p : Crypto_SHA_5Hash4Schedule_Intrinsic; | |
622 | def int_aarch64_crypto_sha1m : Crypto_SHA_5Hash4Schedule_Intrinsic; | |
623 | def int_aarch64_crypto_sha1h : Crypto_SHA_1Hash_Intrinsic; | |
624 | ||
625 | def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic; | |
626 | def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic; | |
627 | ||
628 | // SHA256 | |
629 | def int_aarch64_crypto_sha256h : Crypto_SHA_8Hash4Schedule_Intrinsic; | |
630 | def int_aarch64_crypto_sha256h2 : Crypto_SHA_8Hash4Schedule_Intrinsic; | |
631 | def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic; | |
632 | def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic; | |
633 | ||
634 | //===----------------------------------------------------------------------===// | |
635 | // CRC32 | |
636 | ||
637 | let TargetPrefix = "aarch64" in { | |
638 | ||
639 | def int_aarch64_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
640 | [IntrNoMem]>; | |
641 | def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
642 | [IntrNoMem]>; | |
643 | def int_aarch64_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
644 | [IntrNoMem]>; | |
645 | def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
646 | [IntrNoMem]>; | |
647 | def int_aarch64_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
648 | [IntrNoMem]>; | |
649 | def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | |
650 | [IntrNoMem]>; | |
651 | def int_aarch64_crc32x : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], | |
652 | [IntrNoMem]>; | |
653 | def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], | |
654 | [IntrNoMem]>; | |
655 | } |