]>
Commit | Line | Data |
---|---|---|
223e47cc LB |
1 | //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file describes an abstract interface used to get information about a | |
11 | // target machines register file. This information is used for a variety of | |
12 | // purposed, especially register allocation. | |
13 | // | |
14 | //===----------------------------------------------------------------------===// | |
15 | ||
16 | #ifndef LLVM_MC_MCREGISTERINFO_H | |
17 | #define LLVM_MC_MCREGISTERINFO_H | |
18 | ||
19 | #include "llvm/ADT/DenseMap.h" | |
20 | #include "llvm/Support/ErrorHandling.h" | |
21 | #include <cassert> | |
22 | ||
23 | namespace llvm { | |
24 | ||
970d7e83 LB |
25 | /// An unsigned integer type large enough to represent all physical registers, |
26 | /// but not necessarily virtual registers. | |
27 | typedef uint16_t MCPhysReg; | |
28 | ||
223e47cc LB |
29 | /// MCRegisterClass - Base class of TargetRegisterClass. |
30 | class MCRegisterClass { | |
31 | public: | |
970d7e83 LB |
32 | typedef const MCPhysReg* iterator; |
33 | typedef const MCPhysReg* const_iterator; | |
223e47cc | 34 | |
223e47cc LB |
35 | const iterator RegsBegin; |
36 | const uint8_t *const RegSet; | |
85aaf69f | 37 | const uint32_t NameIdx; |
223e47cc LB |
38 | const uint16_t RegsSize; |
39 | const uint16_t RegSetSize; | |
40 | const uint16_t ID; | |
41 | const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes | |
42 | const int8_t CopyCost; | |
43 | const bool Allocatable; | |
44 | ||
45 | /// getID() - Return the register class ID number. | |
46 | /// | |
47 | unsigned getID() const { return ID; } | |
48 | ||
223e47cc LB |
49 | /// begin/end - Return all of the registers in this class. |
50 | /// | |
51 | iterator begin() const { return RegsBegin; } | |
52 | iterator end() const { return RegsBegin + RegsSize; } | |
53 | ||
54 | /// getNumRegs - Return the number of registers in this class. | |
55 | /// | |
56 | unsigned getNumRegs() const { return RegsSize; } | |
57 | ||
58 | /// getRegister - Return the specified register in the class. | |
59 | /// | |
60 | unsigned getRegister(unsigned i) const { | |
61 | assert(i < getNumRegs() && "Register number out of range!"); | |
62 | return RegsBegin[i]; | |
63 | } | |
64 | ||
65 | /// contains - Return true if the specified register is included in this | |
66 | /// register class. This does not include virtual registers. | |
67 | bool contains(unsigned Reg) const { | |
68 | unsigned InByte = Reg % 8; | |
69 | unsigned Byte = Reg / 8; | |
70 | if (Byte >= RegSetSize) | |
71 | return false; | |
72 | return (RegSet[Byte] & (1 << InByte)) != 0; | |
73 | } | |
74 | ||
75 | /// contains - Return true if both registers are in this class. | |
76 | bool contains(unsigned Reg1, unsigned Reg2) const { | |
77 | return contains(Reg1) && contains(Reg2); | |
78 | } | |
79 | ||
80 | /// getSize - Return the size of the register in bytes, which is also the size | |
81 | /// of a stack slot allocated to hold a spilled copy of this register. | |
82 | unsigned getSize() const { return RegSize; } | |
83 | ||
84 | /// getAlignment - Return the minimum required alignment for a register of | |
85 | /// this class. | |
86 | unsigned getAlignment() const { return Alignment; } | |
87 | ||
88 | /// getCopyCost - Return the cost of copying a value between two registers in | |
89 | /// this class. A negative number means the register class is very expensive | |
90 | /// to copy e.g. status flag register classes. | |
91 | int getCopyCost() const { return CopyCost; } | |
92 | ||
93 | /// isAllocatable - Return true if this register class may be used to create | |
94 | /// virtual registers. | |
95 | bool isAllocatable() const { return Allocatable; } | |
96 | }; | |
97 | ||
1a4d82fc JJ |
98 | /// MCRegisterDesc - This record contains information about a particular |
99 | /// register. The SubRegs field is a zero terminated array of registers that | |
100 | /// are sub-registers of the specific register, e.g. AL, AH are sub-registers | |
101 | /// of AX. The SuperRegs field is a zero terminated array of registers that are | |
102 | /// super-registers of the specific register, e.g. RAX, EAX, are | |
103 | /// super-registers of AX. | |
223e47cc LB |
104 | /// |
105 | struct MCRegisterDesc { | |
106 | uint32_t Name; // Printable name for the reg (for debugging) | |
223e47cc LB |
107 | uint32_t SubRegs; // Sub-register set, described above |
108 | uint32_t SuperRegs; // Super-register set, described above | |
109 | ||
110 | // Offset into MCRI::SubRegIndices of a list of sub-register indices for each | |
111 | // sub-register in SubRegs. | |
112 | uint32_t SubRegIndices; | |
113 | ||
114 | // RegUnits - Points to the list of register units. The low 4 bits holds the | |
115 | // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. | |
116 | uint32_t RegUnits; | |
85aaf69f SL |
117 | |
118 | /// Index into list with lane mask sequences. The sequence contains a lanemask | |
119 | /// for every register unit. | |
120 | uint16_t RegUnitLaneMasks; | |
223e47cc LB |
121 | }; |
122 | ||
123 | /// MCRegisterInfo base class - We assume that the target defines a static | |
124 | /// array of MCRegisterDesc objects that represent all of the machine | |
125 | /// registers that the target has. As such, we simply have to track a pointer | |
126 | /// to this array so that we can turn register number into a register | |
127 | /// descriptor. | |
128 | /// | |
129 | /// Note this class is designed to be a base class of TargetRegisterInfo, which | |
130 | /// is the interface used by codegen. However, specific targets *should never* | |
131 | /// specialize this class. MCRegisterInfo should only contain getters to access | |
132 | /// TableGen generated physical register data. It must not be extended with | |
133 | /// virtual methods. | |
134 | /// | |
135 | class MCRegisterInfo { | |
136 | public: | |
137 | typedef const MCRegisterClass *regclass_iterator; | |
138 | ||
139 | /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be | |
140 | /// performed with a binary search. | |
141 | struct DwarfLLVMRegPair { | |
142 | unsigned FromReg; | |
143 | unsigned ToReg; | |
144 | ||
145 | bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } | |
146 | }; | |
1a4d82fc JJ |
147 | |
148 | /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg | |
149 | /// index, -1 in any being invalid. | |
150 | struct SubRegCoveredBits { | |
151 | uint16_t Offset; | |
152 | uint16_t Size; | |
153 | }; | |
223e47cc LB |
154 | private: |
155 | const MCRegisterDesc *Desc; // Pointer to the descriptor array | |
156 | unsigned NumRegs; // Number of entries in the array | |
157 | unsigned RAReg; // Return address register | |
970d7e83 | 158 | unsigned PCReg; // Program counter register |
223e47cc LB |
159 | const MCRegisterClass *Classes; // Pointer to the regclass array |
160 | unsigned NumClasses; // Number of entries in the array | |
161 | unsigned NumRegUnits; // Number of regunits. | |
1a4d82fc | 162 | const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. |
970d7e83 | 163 | const MCPhysReg *DiffLists; // Pointer to the difflists array |
85aaf69f SL |
164 | const unsigned *RegUnitMaskSequences; // Pointer to lane mask sequences |
165 | // for register units. | |
223e47cc | 166 | const char *RegStrings; // Pointer to the string table. |
85aaf69f | 167 | const char *RegClassStrings; // Pointer to the class strings. |
223e47cc LB |
168 | const uint16_t *SubRegIndices; // Pointer to the subreg lookup |
169 | // array. | |
1a4d82fc JJ |
170 | const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered |
171 | // bit ranges array. | |
223e47cc LB |
172 | unsigned NumSubRegIndices; // Number of subreg indices. |
173 | const uint16_t *RegEncodingTable; // Pointer to array of register | |
174 | // encodings. | |
175 | ||
176 | unsigned L2DwarfRegsSize; | |
177 | unsigned EHL2DwarfRegsSize; | |
178 | unsigned Dwarf2LRegsSize; | |
179 | unsigned EHDwarf2LRegsSize; | |
180 | const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping | |
181 | const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH | |
182 | const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping | |
183 | const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH | |
184 | DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping | |
185 | ||
186 | public: | |
187 | /// DiffListIterator - Base iterator class that can traverse the | |
188 | /// differentially encoded register and regunit lists in DiffLists. | |
189 | /// Don't use this class directly, use one of the specialized sub-classes | |
190 | /// defined below. | |
191 | class DiffListIterator { | |
192 | uint16_t Val; | |
970d7e83 | 193 | const MCPhysReg *List; |
223e47cc LB |
194 | |
195 | protected: | |
196 | /// Create an invalid iterator. Call init() to point to something useful. | |
1a4d82fc | 197 | DiffListIterator() : Val(0), List(nullptr) {} |
223e47cc LB |
198 | |
199 | /// init - Point the iterator to InitVal, decoding subsequent values from | |
200 | /// DiffList. The iterator will initially point to InitVal, sub-classes are | |
201 | /// responsible for skipping the seed value if it is not part of the list. | |
970d7e83 | 202 | void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { |
223e47cc LB |
203 | Val = InitVal; |
204 | List = DiffList; | |
205 | } | |
206 | ||
207 | /// advance - Move to the next list position, return the applied | |
208 | /// differential. This function does not detect the end of the list, that | |
209 | /// is the caller's responsibility (by checking for a 0 return value). | |
210 | unsigned advance() { | |
211 | assert(isValid() && "Cannot move off the end of the list."); | |
970d7e83 | 212 | MCPhysReg D = *List++; |
223e47cc LB |
213 | Val += D; |
214 | return D; | |
215 | } | |
216 | ||
217 | public: | |
218 | ||
219 | /// isValid - returns true if this iterator is not yet at the end. | |
220 | bool isValid() const { return List; } | |
221 | ||
222 | /// Dereference the iterator to get the value at the current position. | |
223 | unsigned operator*() const { return Val; } | |
224 | ||
225 | /// Pre-increment to move to the next position. | |
226 | void operator++() { | |
227 | // The end of the list is encoded as a 0 differential. | |
228 | if (!advance()) | |
1a4d82fc | 229 | List = nullptr; |
223e47cc LB |
230 | } |
231 | }; | |
232 | ||
233 | // These iterators are allowed to sub-class DiffListIterator and access | |
234 | // internal list pointers. | |
235 | friend class MCSubRegIterator; | |
85aaf69f | 236 | friend class MCSubRegIndexIterator; |
223e47cc | 237 | friend class MCSuperRegIterator; |
223e47cc | 238 | friend class MCRegUnitIterator; |
85aaf69f | 239 | friend class MCRegUnitMaskIterator; |
223e47cc LB |
240 | friend class MCRegUnitRootIterator; |
241 | ||
970d7e83 | 242 | /// \brief Initialize MCRegisterInfo, called by TableGen |
223e47cc LB |
243 | /// auto-generated routines. *DO NOT USE*. |
244 | void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, | |
970d7e83 | 245 | unsigned PC, |
223e47cc | 246 | const MCRegisterClass *C, unsigned NC, |
1a4d82fc | 247 | const MCPhysReg (*RURoots)[2], |
223e47cc | 248 | unsigned NRU, |
970d7e83 | 249 | const MCPhysReg *DL, |
85aaf69f | 250 | const unsigned *RUMS, |
223e47cc | 251 | const char *Strings, |
85aaf69f | 252 | const char *ClassStrings, |
223e47cc LB |
253 | const uint16_t *SubIndices, |
254 | unsigned NumIndices, | |
1a4d82fc | 255 | const SubRegCoveredBits *SubIdxRanges, |
223e47cc LB |
256 | const uint16_t *RET) { |
257 | Desc = D; | |
258 | NumRegs = NR; | |
259 | RAReg = RA; | |
970d7e83 | 260 | PCReg = PC; |
223e47cc LB |
261 | Classes = C; |
262 | DiffLists = DL; | |
85aaf69f | 263 | RegUnitMaskSequences = RUMS; |
223e47cc | 264 | RegStrings = Strings; |
85aaf69f | 265 | RegClassStrings = ClassStrings; |
223e47cc LB |
266 | NumClasses = NC; |
267 | RegUnitRoots = RURoots; | |
268 | NumRegUnits = NRU; | |
269 | SubRegIndices = SubIndices; | |
270 | NumSubRegIndices = NumIndices; | |
1a4d82fc | 271 | SubRegIdxRanges = SubIdxRanges; |
223e47cc LB |
272 | RegEncodingTable = RET; |
273 | } | |
274 | ||
970d7e83 | 275 | /// \brief Used to initialize LLVM register to Dwarf |
223e47cc LB |
276 | /// register number mapping. Called by TableGen auto-generated routines. |
277 | /// *DO NOT USE*. | |
278 | void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, | |
279 | bool isEH) { | |
280 | if (isEH) { | |
281 | EHL2DwarfRegs = Map; | |
282 | EHL2DwarfRegsSize = Size; | |
283 | } else { | |
284 | L2DwarfRegs = Map; | |
285 | L2DwarfRegsSize = Size; | |
286 | } | |
287 | } | |
288 | ||
970d7e83 | 289 | /// \brief Used to initialize Dwarf register to LLVM |
223e47cc LB |
290 | /// register number mapping. Called by TableGen auto-generated routines. |
291 | /// *DO NOT USE*. | |
292 | void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, | |
293 | bool isEH) { | |
294 | if (isEH) { | |
295 | EHDwarf2LRegs = Map; | |
296 | EHDwarf2LRegsSize = Size; | |
297 | } else { | |
298 | Dwarf2LRegs = Map; | |
299 | Dwarf2LRegsSize = Size; | |
300 | } | |
301 | } | |
302 | ||
303 | /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register | |
304 | /// number mapping. By default the SEH register number is just the same | |
305 | /// as the LLVM register number. | |
306 | /// FIXME: TableGen these numbers. Currently this requires target specific | |
307 | /// initialization code. | |
308 | void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { | |
309 | L2SEHRegs[LLVMReg] = SEHReg; | |
310 | } | |
311 | ||
970d7e83 | 312 | /// \brief This method should return the register where the return |
223e47cc LB |
313 | /// address can be found. |
314 | unsigned getRARegister() const { | |
315 | return RAReg; | |
316 | } | |
317 | ||
970d7e83 LB |
318 | /// Return the register which is the program counter. |
319 | unsigned getProgramCounter() const { | |
320 | return PCReg; | |
321 | } | |
322 | ||
223e47cc LB |
323 | const MCRegisterDesc &operator[](unsigned RegNo) const { |
324 | assert(RegNo < NumRegs && | |
325 | "Attempting to access record for invalid register number!"); | |
326 | return Desc[RegNo]; | |
327 | } | |
328 | ||
970d7e83 | 329 | /// \brief Provide a get method, equivalent to [], but more useful with a |
223e47cc | 330 | /// pointer to this object. |
223e47cc LB |
331 | const MCRegisterDesc &get(unsigned RegNo) const { |
332 | return operator[](RegNo); | |
333 | } | |
334 | ||
970d7e83 | 335 | /// \brief Returns the physical register number of sub-register "Index" |
223e47cc LB |
336 | /// for physical register RegNo. Return zero if the sub-register does not |
337 | /// exist. | |
338 | unsigned getSubReg(unsigned Reg, unsigned Idx) const; | |
339 | ||
970d7e83 | 340 | /// \brief Return a super-register of the specified register |
223e47cc LB |
341 | /// Reg so its sub-register of index SubIdx is Reg. |
342 | unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, | |
343 | const MCRegisterClass *RC) const; | |
344 | ||
970d7e83 | 345 | /// \brief For a given register pair, return the sub-register index |
223e47cc LB |
346 | /// if the second register is a sub-register of the first. Return zero |
347 | /// otherwise. | |
348 | unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; | |
349 | ||
1a4d82fc JJ |
350 | /// \brief Get the size of the bit range covered by a sub-register index. |
351 | /// If the index isn't continuous, return the sum of the sizes of its parts. | |
352 | /// If the index is used to access subregisters of different sizes, return -1. | |
353 | unsigned getSubRegIdxSize(unsigned Idx) const; | |
354 | ||
355 | /// \brief Get the offset of the bit range covered by a sub-register index. | |
356 | /// If an Offset doesn't make sense (the index isn't continuous, or is used to | |
357 | /// access sub-registers at different offsets), return -1. | |
358 | unsigned getSubRegIdxOffset(unsigned Idx) const; | |
359 | ||
970d7e83 | 360 | /// \brief Return the human-readable symbolic target-specific name for the |
223e47cc LB |
361 | /// specified physical register. |
362 | const char *getName(unsigned RegNo) const { | |
363 | return RegStrings + get(RegNo).Name; | |
364 | } | |
365 | ||
970d7e83 | 366 | /// \brief Return the number of registers this target has (useful for |
223e47cc LB |
367 | /// sizing arrays holding per register information) |
368 | unsigned getNumRegs() const { | |
369 | return NumRegs; | |
370 | } | |
371 | ||
970d7e83 | 372 | /// \brief Return the number of sub-register indices |
223e47cc LB |
373 | /// understood by the target. Index 0 is reserved for the no-op sub-register, |
374 | /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. | |
375 | unsigned getNumSubRegIndices() const { | |
376 | return NumSubRegIndices; | |
377 | } | |
378 | ||
970d7e83 | 379 | /// \brief Return the number of (native) register units in the |
223e47cc LB |
380 | /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They |
381 | /// can be accessed through MCRegUnitIterator defined below. | |
382 | unsigned getNumRegUnits() const { | |
383 | return NumRegUnits; | |
384 | } | |
385 | ||
970d7e83 | 386 | /// \brief Map a target register to an equivalent dwarf register |
223e47cc LB |
387 | /// number. Returns -1 if there is no equivalent value. The second |
388 | /// parameter allows targets to use different numberings for EH info and | |
389 | /// debugging info. | |
390 | int getDwarfRegNum(unsigned RegNum, bool isEH) const; | |
391 | ||
970d7e83 | 392 | /// \brief Map a dwarf register back to a target register. |
223e47cc LB |
393 | int getLLVMRegNum(unsigned RegNum, bool isEH) const; |
394 | ||
970d7e83 | 395 | /// \brief Map a target register to an equivalent SEH register |
223e47cc LB |
396 | /// number. Returns LLVM register number if there is no equivalent value. |
397 | int getSEHRegNum(unsigned RegNum) const; | |
398 | ||
399 | regclass_iterator regclass_begin() const { return Classes; } | |
400 | regclass_iterator regclass_end() const { return Classes+NumClasses; } | |
401 | ||
402 | unsigned getNumRegClasses() const { | |
403 | return (unsigned)(regclass_end()-regclass_begin()); | |
404 | } | |
405 | ||
970d7e83 | 406 | /// \brief Returns the register class associated with the enumeration |
223e47cc | 407 | /// value. See class MCOperandInfo. |
970d7e83 | 408 | const MCRegisterClass& getRegClass(unsigned i) const { |
223e47cc LB |
409 | assert(i < getNumRegClasses() && "Register Class ID out of range"); |
410 | return Classes[i]; | |
411 | } | |
412 | ||
85aaf69f SL |
413 | const char *getRegClassName(const MCRegisterClass *Class) const { |
414 | return RegClassStrings + Class->NameIdx; | |
415 | } | |
416 | ||
970d7e83 | 417 | /// \brief Returns the encoding for RegNo |
223e47cc LB |
418 | uint16_t getEncodingValue(unsigned RegNo) const { |
419 | assert(RegNo < NumRegs && | |
420 | "Attempting to get encoding for invalid register number!"); | |
421 | return RegEncodingTable[RegNo]; | |
422 | } | |
423 | ||
970d7e83 LB |
424 | /// \brief Returns true if RegB is a sub-register of RegA. |
425 | bool isSubRegister(unsigned RegA, unsigned RegB) const { | |
426 | return isSuperRegister(RegB, RegA); | |
427 | } | |
428 | ||
429 | /// \brief Returns true if RegB is a super-register of RegA. | |
430 | bool isSuperRegister(unsigned RegA, unsigned RegB) const; | |
431 | ||
432 | /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA. | |
433 | bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { | |
434 | return isSuperRegisterEq(RegB, RegA); | |
435 | } | |
436 | ||
437 | /// \brief Returns true if RegB is a super-register of RegA or if | |
438 | /// RegB == RegA. | |
439 | bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { | |
440 | return RegA == RegB || isSuperRegister(RegA, RegB); | |
441 | } | |
442 | ||
223e47cc LB |
443 | }; |
444 | ||
445 | //===----------------------------------------------------------------------===// | |
446 | // Register List Iterators | |
447 | //===----------------------------------------------------------------------===// | |
448 | ||
449 | // MCRegisterInfo provides lists of super-registers, sub-registers, and | |
450 | // aliasing registers. Use these iterator classes to traverse the lists. | |
451 | ||
452 | /// MCSubRegIterator enumerates all sub-registers of Reg. | |
1a4d82fc | 453 | /// If IncludeSelf is set, Reg itself is included in the list. |
223e47cc LB |
454 | class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { |
455 | public: | |
1a4d82fc JJ |
456 | MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, |
457 | bool IncludeSelf = false) { | |
223e47cc | 458 | init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); |
1a4d82fc JJ |
459 | // Initially, the iterator points to Reg itself. |
460 | if (!IncludeSelf) | |
461 | ++*this; | |
223e47cc LB |
462 | } |
463 | }; | |
464 | ||
85aaf69f SL |
465 | /// Iterator that enumerates the sub-registers of a Reg and the associated |
466 | /// sub-register indices. | |
467 | class MCSubRegIndexIterator { | |
468 | MCSubRegIterator SRIter; | |
469 | const uint16_t *SRIndex; | |
470 | public: | |
471 | /// Constructs an iterator that traverses subregisters and their | |
472 | /// associated subregister indices. | |
473 | MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) | |
474 | : SRIter(Reg, MCRI) { | |
475 | SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; | |
476 | } | |
477 | ||
478 | /// Returns current sub-register. | |
479 | unsigned getSubReg() const { | |
480 | return *SRIter; | |
481 | } | |
482 | /// Returns sub-register index of the current sub-register. | |
483 | unsigned getSubRegIndex() const { | |
484 | return *SRIndex; | |
485 | } | |
486 | ||
487 | /// Returns true if this iterator is not yet at the end. | |
488 | bool isValid() const { return SRIter.isValid(); } | |
489 | ||
490 | /// Moves to the next position. | |
491 | void operator++() { | |
492 | ++SRIter; | |
493 | ++SRIndex; | |
494 | } | |
495 | }; | |
496 | ||
223e47cc | 497 | /// MCSuperRegIterator enumerates all super-registers of Reg. |
1a4d82fc | 498 | /// If IncludeSelf is set, Reg itself is included in the list. |
223e47cc LB |
499 | class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { |
500 | public: | |
1a4d82fc JJ |
501 | MCSuperRegIterator() {} |
502 | MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, | |
503 | bool IncludeSelf = false) { | |
223e47cc | 504 | init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); |
223e47cc LB |
505 | // Initially, the iterator points to Reg itself. |
506 | if (!IncludeSelf) | |
507 | ++*this; | |
508 | } | |
509 | }; | |
510 | ||
970d7e83 LB |
511 | // Definition for isSuperRegister. Put it down here since it needs the |
512 | // iterator defined above in addition to the MCRegisterInfo class itself. | |
513 | inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ | |
514 | for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) | |
515 | if (*I == RegB) | |
516 | return true; | |
517 | return false; | |
518 | } | |
519 | ||
223e47cc LB |
520 | //===----------------------------------------------------------------------===// |
521 | // Register Units | |
522 | //===----------------------------------------------------------------------===// | |
523 | ||
524 | // Register units are used to compute register aliasing. Every register has at | |
525 | // least one register unit, but it can have more. Two registers overlap if and | |
526 | // only if they have a common register unit. | |
527 | // | |
528 | // A target with a complicated sub-register structure will typically have many | |
529 | // fewer register units than actual registers. MCRI::getNumRegUnits() returns | |
530 | // the number of register units in the target. | |
531 | ||
532 | // MCRegUnitIterator enumerates a list of register units for Reg. The list is | |
533 | // in ascending numerical order. | |
534 | class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { | |
535 | public: | |
536 | /// MCRegUnitIterator - Create an iterator that traverses the register units | |
537 | /// in Reg. | |
1a4d82fc | 538 | MCRegUnitIterator() {} |
223e47cc | 539 | MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { |
970d7e83 | 540 | assert(Reg && "Null register has no regunits"); |
223e47cc LB |
541 | // Decode the RegUnits MCRegisterDesc field. |
542 | unsigned RU = MCRI->get(Reg).RegUnits; | |
543 | unsigned Scale = RU & 15; | |
544 | unsigned Offset = RU >> 4; | |
545 | ||
546 | // Initialize the iterator to Reg * Scale, and the List pointer to | |
547 | // DiffLists + Offset. | |
548 | init(Reg * Scale, MCRI->DiffLists + Offset); | |
549 | ||
550 | // That may not be a valid unit, we need to advance by one to get the real | |
551 | // unit number. The first differential can be 0 which would normally | |
552 | // terminate the list, but since we know every register has at least one | |
553 | // unit, we can allow a 0 differential here. | |
554 | advance(); | |
555 | } | |
556 | }; | |
557 | ||
85aaf69f SL |
558 | /// MCRegUnitIterator enumerates a list of register units and their associated |
559 | /// lane masks for Reg. The register units are in ascending numerical order. | |
560 | class MCRegUnitMaskIterator { | |
561 | MCRegUnitIterator RUIter; | |
562 | const unsigned *MaskListIter; | |
563 | public: | |
564 | MCRegUnitMaskIterator() {} | |
565 | /// Constructs an iterator that traverses the register units and their | |
566 | /// associated LaneMasks in Reg. | |
567 | MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI) | |
568 | : RUIter(Reg, MCRI) { | |
569 | uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; | |
570 | MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; | |
571 | } | |
572 | ||
573 | /// Returns a (RegUnit, LaneMask) pair. | |
574 | std::pair<unsigned,unsigned> operator*() const { | |
575 | return std::make_pair(*RUIter, *MaskListIter); | |
576 | } | |
577 | ||
578 | /// Returns true if this iterator is not yet at the end. | |
579 | bool isValid() const { return RUIter.isValid(); } | |
580 | ||
581 | /// Moves to the next position. | |
582 | void operator++() { | |
583 | ++MaskListIter; | |
584 | ++RUIter; | |
585 | } | |
586 | }; | |
587 | ||
223e47cc LB |
588 | // Each register unit has one or two root registers. The complete set of |
589 | // registers containing a register unit is the union of the roots and their | |
590 | // super-registers. All registers aliasing Unit can be visited like this: | |
591 | // | |
592 | // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { | |
1a4d82fc | 593 | // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) |
223e47cc LB |
594 | // visit(*SI); |
595 | // } | |
596 | ||
597 | /// MCRegUnitRootIterator enumerates the root registers of a register unit. | |
598 | class MCRegUnitRootIterator { | |
599 | uint16_t Reg0; | |
600 | uint16_t Reg1; | |
601 | public: | |
1a4d82fc | 602 | MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} |
223e47cc LB |
603 | MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { |
604 | assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); | |
605 | Reg0 = MCRI->RegUnitRoots[RegUnit][0]; | |
606 | Reg1 = MCRI->RegUnitRoots[RegUnit][1]; | |
607 | } | |
608 | ||
970d7e83 | 609 | /// \brief Dereference to get the current root register. |
223e47cc LB |
610 | unsigned operator*() const { |
611 | return Reg0; | |
612 | } | |
613 | ||
970d7e83 | 614 | /// \brief Check if the iterator is at the end of the list. |
223e47cc LB |
615 | bool isValid() const { |
616 | return Reg0; | |
617 | } | |
618 | ||
970d7e83 | 619 | /// \brief Preincrement to move to the next root register. |
223e47cc LB |
620 | void operator++() { |
621 | assert(isValid() && "Cannot move off the end of the list."); | |
622 | Reg0 = Reg1; | |
623 | Reg1 = 0; | |
624 | } | |
625 | }; | |
626 | ||
1a4d82fc JJ |
627 | /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is |
628 | /// set, Reg itself is included in the list. This iterator does not guarantee | |
629 | /// any ordering or that entries are unique. | |
630 | class MCRegAliasIterator { | |
631 | private: | |
632 | unsigned Reg; | |
633 | const MCRegisterInfo *MCRI; | |
634 | bool IncludeSelf; | |
635 | ||
636 | MCRegUnitIterator RI; | |
637 | MCRegUnitRootIterator RRI; | |
638 | MCSuperRegIterator SI; | |
639 | public: | |
640 | MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, | |
641 | bool IncludeSelf) | |
642 | : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { | |
643 | ||
644 | // Initialize the iterators. | |
645 | for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { | |
646 | for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { | |
647 | for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { | |
648 | if (!(!IncludeSelf && Reg == *SI)) | |
649 | return; | |
650 | } | |
651 | } | |
652 | } | |
653 | } | |
654 | ||
655 | bool isValid() const { | |
656 | return RI.isValid(); | |
657 | } | |
658 | ||
659 | unsigned operator*() const { | |
660 | assert (SI.isValid() && "Cannot dereference an invalid iterator."); | |
661 | return *SI; | |
662 | } | |
663 | ||
664 | void advance() { | |
665 | // Assuming SI is valid. | |
666 | ++SI; | |
667 | if (SI.isValid()) return; | |
668 | ||
669 | ++RRI; | |
670 | if (RRI.isValid()) { | |
671 | SI = MCSuperRegIterator(*RRI, MCRI, true); | |
672 | return; | |
673 | } | |
674 | ||
675 | ++RI; | |
676 | if (RI.isValid()) { | |
677 | RRI = MCRegUnitRootIterator(*RI, MCRI); | |
678 | SI = MCSuperRegIterator(*RRI, MCRI, true); | |
679 | } | |
680 | } | |
681 | ||
682 | void operator++() { | |
683 | assert(isValid() && "Cannot move off the end of the list."); | |
684 | do advance(); | |
685 | while (!IncludeSelf && isValid() && *SI == Reg); | |
686 | } | |
687 | }; | |
688 | ||
223e47cc LB |
689 | } // End llvm namespace |
690 | ||
691 | #endif |