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1 | //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file defines the target-independent interfaces which should be | |
11 | // implemented by each target which is using a TableGen based code generator. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | // Include all information about LLVM intrinsics. | |
970d7e83 | 16 | include "llvm/IR/Intrinsics.td" |
223e47cc LB |
17 | |
18 | //===----------------------------------------------------------------------===// | |
19 | // Register file description - These classes are used to fill in the target | |
20 | // description classes. | |
21 | ||
22 | class RegisterClass; // Forward def | |
23 | ||
24 | // SubRegIndex - Use instances of SubRegIndex to identify subregisters. | |
1a4d82fc | 25 | class SubRegIndex<int size, int offset = 0> { |
223e47cc LB |
26 | string Namespace = ""; |
27 | ||
1a4d82fc JJ |
28 | // Size - Size (in bits) of the sub-registers represented by this index. |
29 | int Size = size; | |
30 | ||
31 | // Offset - Offset of the first bit that is part of this sub-register index. | |
32 | // Set it to -1 if the same index is used to represent sub-registers that can | |
33 | // be at different offsets (for example when using an index to access an | |
34 | // element in a register tuple). | |
35 | int Offset = offset; | |
36 | ||
223e47cc LB |
37 | // ComposedOf - A list of two SubRegIndex instances, [A, B]. |
38 | // This indicates that this SubRegIndex is the result of composing A and B. | |
1a4d82fc JJ |
39 | // See ComposedSubRegIndex. |
40 | list<SubRegIndex> ComposedOf = []; | |
223e47cc LB |
41 | |
42 | // CoveringSubRegIndices - A list of two or more sub-register indexes that | |
43 | // cover this sub-register. | |
44 | // | |
45 | // This field should normally be left blank as TableGen can infer it. | |
46 | // | |
47 | // TableGen automatically detects sub-registers that straddle the registers | |
48 | // in the SubRegs field of a Register definition. For example: | |
49 | // | |
50 | // Q0 = dsub_0 -> D0, dsub_1 -> D1 | |
51 | // Q1 = dsub_0 -> D2, dsub_1 -> D3 | |
52 | // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 | |
53 | // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 | |
54 | // | |
55 | // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given | |
56 | // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with | |
57 | // CoveringSubRegIndices = [dsub_1, dsub_2]. | |
58 | list<SubRegIndex> CoveringSubRegIndices = []; | |
59 | } | |
60 | ||
1a4d82fc JJ |
61 | // ComposedSubRegIndex - A sub-register that is the result of composing A and B. |
62 | // Offset is set to the sum of A and B's Offsets. Size is set to B's Size. | |
63 | class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> | |
64 | : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, | |
65 | !if(!eq(B.Offset, -1), -1, | |
66 | !add(A.Offset, B.Offset)))> { | |
67 | // See SubRegIndex. | |
68 | let ComposedOf = [A, B]; | |
69 | } | |
70 | ||
223e47cc LB |
71 | // RegAltNameIndex - The alternate name set to use for register operands of |
72 | // this register class when printing. | |
73 | class RegAltNameIndex { | |
74 | string Namespace = ""; | |
75 | } | |
76 | def NoRegAltName : RegAltNameIndex; | |
77 | ||
78 | // Register - You should define one instance of this class for each register | |
79 | // in the target machine. String n will become the "name" of the register. | |
80 | class Register<string n, list<string> altNames = []> { | |
81 | string Namespace = ""; | |
82 | string AsmName = n; | |
83 | list<string> AltNames = altNames; | |
84 | ||
85 | // Aliases - A list of registers that this register overlaps with. A read or | |
86 | // modification of this register can potentially read or modify the aliased | |
87 | // registers. | |
88 | list<Register> Aliases = []; | |
89 | ||
90 | // SubRegs - A list of registers that are parts of this register. Note these | |
91 | // are "immediate" sub-registers and the registers within the list do not | |
92 | // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], | |
93 | // not [AX, AH, AL]. | |
94 | list<Register> SubRegs = []; | |
95 | ||
96 | // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used | |
97 | // to address it. Sub-sub-register indices are automatically inherited from | |
98 | // SubRegs. | |
99 | list<SubRegIndex> SubRegIndices = []; | |
100 | ||
101 | // RegAltNameIndices - The alternate name indices which are valid for this | |
102 | // register. | |
103 | list<RegAltNameIndex> RegAltNameIndices = []; | |
104 | ||
105 | // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. | |
106 | // These values can be determined by locating the <target>.h file in the | |
107 | // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The | |
108 | // order of these names correspond to the enumeration used by gcc. A value of | |
109 | // -1 indicates that the gcc number is undefined and -2 that register number | |
110 | // is invalid for this mode/flavour. | |
111 | list<int> DwarfNumbers = []; | |
112 | ||
113 | // CostPerUse - Additional cost of instructions using this register compared | |
114 | // to other registers in its class. The register allocator will try to | |
115 | // minimize the number of instructions using a register with a CostPerUse. | |
116 | // This is used by the x86-64 and ARM Thumb targets where some registers | |
117 | // require larger instruction encodings. | |
118 | int CostPerUse = 0; | |
119 | ||
120 | // CoveredBySubRegs - When this bit is set, the value of this register is | |
121 | // completely determined by the value of its sub-registers. For example, the | |
122 | // x86 register AX is covered by its sub-registers AL and AH, but EAX is not | |
123 | // covered by its sub-register AX. | |
124 | bit CoveredBySubRegs = 0; | |
125 | ||
126 | // HWEncoding - The target specific hardware encoding for this register. | |
127 | bits<16> HWEncoding = 0; | |
128 | } | |
129 | ||
130 | // RegisterWithSubRegs - This can be used to define instances of Register which | |
131 | // need to specify sub-registers. | |
132 | // List "subregs" specifies which registers are sub-registers to this one. This | |
133 | // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. | |
134 | // This allows the code generator to be careful not to put two values with | |
135 | // overlapping live ranges into registers which alias. | |
136 | class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { | |
137 | let SubRegs = subregs; | |
138 | } | |
139 | ||
140 | // DAGOperand - An empty base class that unifies RegisterClass's and other forms | |
141 | // of Operand's that are legal as type qualifiers in DAG patterns. This should | |
142 | // only ever be used for defining multiclasses that are polymorphic over both | |
143 | // RegisterClass's and other Operand's. | |
144 | class DAGOperand { } | |
145 | ||
146 | // RegisterClass - Now that all of the registers are defined, and aliases | |
147 | // between registers are defined, specify which registers belong to which | |
148 | // register classes. This also defines the default allocation order of | |
149 | // registers by register allocators. | |
150 | // | |
151 | class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, | |
152 | dag regList, RegAltNameIndex idx = NoRegAltName> | |
153 | : DAGOperand { | |
154 | string Namespace = namespace; | |
155 | ||
156 | // RegType - Specify the list ValueType of the registers in this register | |
157 | // class. Note that all registers in a register class must have the same | |
158 | // ValueTypes. This is a list because some targets permit storing different | |
159 | // types in same register, for example vector values with 128-bit total size, | |
160 | // but different count/size of items, like SSE on x86. | |
161 | // | |
162 | list<ValueType> RegTypes = regTypes; | |
163 | ||
164 | // Size - Specify the spill size in bits of the registers. A default value of | |
165 | // zero lets tablgen pick an appropriate size. | |
166 | int Size = 0; | |
167 | ||
168 | // Alignment - Specify the alignment required of the registers when they are | |
169 | // stored or loaded to memory. | |
170 | // | |
171 | int Alignment = alignment; | |
172 | ||
173 | // CopyCost - This value is used to specify the cost of copying a value | |
174 | // between two registers in this register class. The default value is one | |
175 | // meaning it takes a single instruction to perform the copying. A negative | |
176 | // value means copying is extremely expensive or impossible. | |
177 | int CopyCost = 1; | |
178 | ||
179 | // MemberList - Specify which registers are in this class. If the | |
180 | // allocation_order_* method are not specified, this also defines the order of | |
181 | // allocation used by the register allocator. | |
182 | // | |
183 | dag MemberList = regList; | |
184 | ||
185 | // AltNameIndex - The alternate register name to use when printing operands | |
186 | // of this register class. Every register in the register class must have | |
187 | // a valid alternate name for the given index. | |
188 | RegAltNameIndex altNameIndex = idx; | |
189 | ||
190 | // isAllocatable - Specify that the register class can be used for virtual | |
191 | // registers and register allocation. Some register classes are only used to | |
192 | // model instruction operand constraints, and should have isAllocatable = 0. | |
193 | bit isAllocatable = 1; | |
194 | ||
195 | // AltOrders - List of alternative allocation orders. The default order is | |
196 | // MemberList itself, and that is good enough for most targets since the | |
197 | // register allocators automatically remove reserved registers and move | |
198 | // callee-saved registers to the end. | |
199 | list<dag> AltOrders = []; | |
200 | ||
201 | // AltOrderSelect - The body of a function that selects the allocation order | |
202 | // to use in a given machine function. The code will be inserted in a | |
203 | // function like this: | |
204 | // | |
205 | // static inline unsigned f(const MachineFunction &MF) { ... } | |
206 | // | |
207 | // The function should return 0 to select the default order defined by | |
208 | // MemberList, 1 to select the first AltOrders entry and so on. | |
209 | code AltOrderSelect = [{}]; | |
210 | } | |
211 | ||
212 | // The memberList in a RegisterClass is a dag of set operations. TableGen | |
213 | // evaluates these set operations and expand them into register lists. These | |
214 | // are the most common operation, see test/TableGen/SetTheory.td for more | |
215 | // examples of what is possible: | |
216 | // | |
217 | // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a | |
218 | // register class, or a sub-expression. This is also the way to simply list | |
219 | // registers. | |
220 | // | |
221 | // (sub GPR, SP) - Set difference. Subtract the last arguments from the first. | |
222 | // | |
223 | // (and GPR, CSR) - Set intersection. All registers from the first set that are | |
224 | // also in the second set. | |
225 | // | |
226 | // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of | |
227 | // numbered registers. Takes an optional 4th operand which is a stride to use | |
228 | // when generating the sequence. | |
229 | // | |
230 | // (shl GPR, 4) - Remove the first N elements. | |
231 | // | |
232 | // (trunc GPR, 4) - Truncate after the first N elements. | |
233 | // | |
234 | // (rotl GPR, 1) - Rotate N places to the left. | |
235 | // | |
236 | // (rotr GPR, 1) - Rotate N places to the right. | |
237 | // | |
238 | // (decimate GPR, 2) - Pick every N'th element, starting with the first. | |
239 | // | |
240 | // (interleave A, B, ...) - Interleave the elements from each argument list. | |
241 | // | |
242 | // All of these operators work on ordered sets, not lists. That means | |
243 | // duplicates are removed from sub-expressions. | |
244 | ||
245 | // Set operators. The rest is defined in TargetSelectionDAG.td. | |
246 | def sequence; | |
247 | def decimate; | |
248 | def interleave; | |
249 | ||
250 | // RegisterTuples - Automatically generate super-registers by forming tuples of | |
251 | // sub-registers. This is useful for modeling register sequence constraints | |
252 | // with pseudo-registers that are larger than the architectural registers. | |
253 | // | |
254 | // The sub-register lists are zipped together: | |
255 | // | |
256 | // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; | |
257 | // | |
258 | // Generates the same registers as: | |
259 | // | |
260 | // let SubRegIndices = [sube, subo] in { | |
261 | // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; | |
262 | // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; | |
263 | // } | |
264 | // | |
265 | // The generated pseudo-registers inherit super-classes and fields from their | |
266 | // first sub-register. Most fields from the Register class are inferred, and | |
267 | // the AsmName and Dwarf numbers are cleared. | |
268 | // | |
269 | // RegisterTuples instances can be used in other set operations to form | |
270 | // register classes and so on. This is the only way of using the generated | |
271 | // registers. | |
272 | class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { | |
273 | // SubRegs - N lists of registers to be zipped up. Super-registers are | |
274 | // synthesized from the first element of each SubRegs list, the second | |
275 | // element and so on. | |
276 | list<dag> SubRegs = Regs; | |
277 | ||
278 | // SubRegIndices - N SubRegIndex instances. This provides the names of the | |
279 | // sub-registers in the synthesized super-registers. | |
280 | list<SubRegIndex> SubRegIndices = Indices; | |
281 | } | |
282 | ||
283 | ||
284 | //===----------------------------------------------------------------------===// | |
285 | // DwarfRegNum - This class provides a mapping of the llvm register enumeration | |
286 | // to the register numbering used by gcc and gdb. These values are used by a | |
287 | // debug information writer to describe where values may be located during | |
288 | // execution. | |
289 | class DwarfRegNum<list<int> Numbers> { | |
290 | // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. | |
291 | // These values can be determined by locating the <target>.h file in the | |
292 | // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The | |
293 | // order of these names correspond to the enumeration used by gcc. A value of | |
294 | // -1 indicates that the gcc number is undefined and -2 that register number | |
295 | // is invalid for this mode/flavour. | |
296 | list<int> DwarfNumbers = Numbers; | |
297 | } | |
298 | ||
299 | // DwarfRegAlias - This class declares that a given register uses the same dwarf | |
300 | // numbers as another one. This is useful for making it clear that the two | |
301 | // registers do have the same number. It also lets us build a mapping | |
302 | // from dwarf register number to llvm register. | |
303 | class DwarfRegAlias<Register reg> { | |
304 | Register DwarfAlias = reg; | |
305 | } | |
306 | ||
307 | //===----------------------------------------------------------------------===// | |
308 | // Pull in the common support for scheduling | |
309 | // | |
310 | include "llvm/Target/TargetSchedule.td" | |
311 | ||
312 | class Predicate; // Forward def | |
313 | ||
314 | //===----------------------------------------------------------------------===// | |
315 | // Instruction set description - These classes correspond to the C++ classes in | |
316 | // the Target/TargetInstrInfo.h file. | |
317 | // | |
318 | class Instruction { | |
319 | string Namespace = ""; | |
320 | ||
321 | dag OutOperandList; // An dag containing the MI def operand list. | |
322 | dag InOperandList; // An dag containing the MI use operand list. | |
323 | string AsmString = ""; // The .s format to print the instruction with. | |
324 | ||
325 | // Pattern - Set to the DAG pattern for this instruction, if we know of one, | |
326 | // otherwise, uninitialized. | |
327 | list<dag> Pattern; | |
328 | ||
329 | // The follow state will eventually be inferred automatically from the | |
330 | // instruction pattern. | |
331 | ||
332 | list<Register> Uses = []; // Default to using no non-operand registers | |
333 | list<Register> Defs = []; // Default to modifying no non-operand registers | |
334 | ||
335 | // Predicates - List of predicates which will be turned into isel matching | |
336 | // code. | |
337 | list<Predicate> Predicates = []; | |
338 | ||
339 | // Size - Size of encoded instruction, or zero if the size cannot be determined | |
340 | // from the opcode. | |
341 | int Size = 0; | |
342 | ||
343 | // DecoderNamespace - The "namespace" in which this instruction exists, on | |
344 | // targets like ARM which multiple ISA namespaces exist. | |
345 | string DecoderNamespace = ""; | |
346 | ||
347 | // Code size, for instruction selection. | |
348 | // FIXME: What does this actually mean? | |
349 | int CodeSize = 0; | |
350 | ||
351 | // Added complexity passed onto matching pattern. | |
352 | int AddedComplexity = 0; | |
353 | ||
354 | // These bits capture information about the high-level semantics of the | |
355 | // instruction. | |
356 | bit isReturn = 0; // Is this instruction a return instruction? | |
357 | bit isBranch = 0; // Is this instruction a branch instruction? | |
358 | bit isIndirectBranch = 0; // Is this instruction an indirect branch? | |
359 | bit isCompare = 0; // Is this instruction a comparison instruction? | |
360 | bit isMoveImm = 0; // Is this instruction a move immediate instruction? | |
361 | bit isBitcast = 0; // Is this instruction a bitcast instruction? | |
362 | bit isSelect = 0; // Is this instruction a select instruction? | |
363 | bit isBarrier = 0; // Can control flow fall through this instruction? | |
364 | bit isCall = 0; // Is this instruction a call instruction? | |
365 | bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? | |
366 | bit mayLoad = ?; // Is it possible for this inst to read memory? | |
367 | bit mayStore = ?; // Is it possible for this inst to write memory? | |
368 | bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? | |
369 | bit isCommutable = 0; // Is this 3 operand instruction commutable? | |
370 | bit isTerminator = 0; // Is this part of the terminator for a basic block? | |
371 | bit isReMaterializable = 0; // Is this instruction re-materializable? | |
372 | bit isPredicable = 0; // Is this instruction predicable? | |
373 | bit hasDelaySlot = 0; // Does this instruction have an delay slot? | |
374 | bit usesCustomInserter = 0; // Pseudo instr needing special help. | |
375 | bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. | |
376 | bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? | |
377 | bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? | |
378 | bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. | |
379 | bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? | |
380 | bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? | |
1a4d82fc JJ |
381 | bit isRegSequence = 0; // Is this instruction a kind of reg sequence? |
382 | // If so, make sure to override | |
383 | // TargetInstrInfo::getRegSequenceLikeInputs. | |
223e47cc LB |
384 | bit isPseudo = 0; // Is this instruction a pseudo-instruction? |
385 | // If so, won't have encoding information for | |
386 | // the [MC]CodeEmitter stuff. | |
1a4d82fc JJ |
387 | bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? |
388 | // If so, make sure to override | |
389 | // TargetInstrInfo::getExtractSubregLikeInputs. | |
390 | bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? | |
391 | // If so, make sure to override | |
392 | // TargetInstrInfo::getInsertSubregLikeInputs. | |
223e47cc LB |
393 | |
394 | // Side effect flags - When set, the flags have these meanings: | |
395 | // | |
396 | // hasSideEffects - The instruction has side effects that are not | |
397 | // captured by any operands of the instruction or other flags. | |
398 | // | |
223e47cc | 399 | bit hasSideEffects = ?; |
223e47cc LB |
400 | |
401 | // Is this instruction a "real" instruction (with a distinct machine | |
402 | // encoding), or is it a pseudo instruction used for codegen modeling | |
403 | // purposes. | |
404 | // FIXME: For now this is distinct from isPseudo, above, as code-gen-only | |
405 | // instructions can (and often do) still have encoding information | |
406 | // associated with them. Once we've migrated all of them over to true | |
407 | // pseudo-instructions that are lowered to real instructions prior to | |
408 | // the printer/emitter, we can remove this attribute and just use isPseudo. | |
409 | // | |
410 | // The intended use is: | |
411 | // isPseudo: Does not have encoding information and should be expanded, | |
412 | // at the latest, during lowering to MCInst. | |
413 | // | |
414 | // isCodeGenOnly: Does have encoding information and can go through to the | |
415 | // CodeEmitter unchanged, but duplicates a canonical instruction | |
416 | // definition's encoding and should be ignored when constructing the | |
417 | // assembler match tables. | |
418 | bit isCodeGenOnly = 0; | |
419 | ||
420 | // Is this instruction a pseudo instruction for use by the assembler parser. | |
421 | bit isAsmParserOnly = 0; | |
422 | ||
423 | InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. | |
424 | ||
970d7e83 LB |
425 | // Scheduling information from TargetSchedule.td. |
426 | list<SchedReadWrite> SchedRW; | |
427 | ||
223e47cc LB |
428 | string Constraints = ""; // OperandConstraint, e.g. $src = $dst. |
429 | ||
430 | /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not | |
431 | /// be encoded into the output machineinstr. | |
432 | string DisableEncoding = ""; | |
433 | ||
434 | string PostEncoderMethod = ""; | |
435 | string DecoderMethod = ""; | |
436 | ||
437 | /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. | |
438 | bits<64> TSFlags = 0; | |
439 | ||
440 | ///@name Assembler Parser Support | |
441 | ///@{ | |
442 | ||
443 | string AsmMatchConverter = ""; | |
444 | ||
445 | /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a | |
446 | /// two-operand matcher inst-alias for a three operand instruction. | |
447 | /// For example, the arm instruction "add r3, r3, r5" can be written | |
448 | /// as "add r3, r5". The constraint is of the same form as a tied-operand | |
449 | /// constraint. For example, "$Rn = $Rd". | |
450 | string TwoOperandAliasConstraint = ""; | |
451 | ||
452 | ///@} | |
1a4d82fc JJ |
453 | |
454 | /// UseNamedOperandTable - If set, the operand indices of this instruction | |
455 | /// can be queried via the getNamedOperandIdx() function which is generated | |
456 | /// by TableGen. | |
457 | bit UseNamedOperandTable = 0; | |
223e47cc LB |
458 | } |
459 | ||
460 | /// PseudoInstExpansion - Expansion information for a pseudo-instruction. | |
461 | /// Which instruction it expands to and how the operands map from the | |
462 | /// pseudo. | |
463 | class PseudoInstExpansion<dag Result> { | |
464 | dag ResultInst = Result; // The instruction to generate. | |
465 | bit isPseudo = 1; | |
466 | } | |
467 | ||
468 | /// Predicates - These are extra conditionals which are turned into instruction | |
469 | /// selector matching code. Currently each predicate is just a string. | |
470 | class Predicate<string cond> { | |
471 | string CondString = cond; | |
472 | ||
473 | /// AssemblerMatcherPredicate - If this feature can be used by the assembler | |
474 | /// matcher, this is true. Targets should set this by inheriting their | |
475 | /// feature from the AssemblerPredicate class in addition to Predicate. | |
476 | bit AssemblerMatcherPredicate = 0; | |
477 | ||
478 | /// AssemblerCondString - Name of the subtarget feature being tested used | |
479 | /// as alternative condition string used for assembler matcher. | |
480 | /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". | |
481 | /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". | |
482 | /// It can also list multiple features separated by ",". | |
483 | /// e.g. "ModeThumb,FeatureThumb2" is translated to | |
484 | /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". | |
485 | string AssemblerCondString = ""; | |
486 | ||
487 | /// PredicateName - User-level name to use for the predicate. Mainly for use | |
488 | /// in diagnostics such as missing feature errors in the asm matcher. | |
489 | string PredicateName = ""; | |
490 | } | |
491 | ||
492 | /// NoHonorSignDependentRounding - This predicate is true if support for | |
493 | /// sign-dependent-rounding is not enabled. | |
494 | def NoHonorSignDependentRounding | |
495 | : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; | |
496 | ||
497 | class Requires<list<Predicate> preds> { | |
498 | list<Predicate> Predicates = preds; | |
499 | } | |
500 | ||
501 | /// ops definition - This is just a simple marker used to identify the operand | |
502 | /// list for an instruction. outs and ins are identical both syntactically and | |
503 | /// semanticallyr; they are used to define def operands and use operands to | |
504 | /// improve readibility. This should be used like this: | |
505 | /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. | |
506 | def ops; | |
507 | def outs; | |
508 | def ins; | |
509 | ||
510 | /// variable_ops definition - Mark this instruction as taking a variable number | |
511 | /// of operands. | |
512 | def variable_ops; | |
513 | ||
514 | ||
515 | /// PointerLikeRegClass - Values that are designed to have pointer width are | |
516 | /// derived from this. TableGen treats the register class as having a symbolic | |
517 | /// type that it doesn't know, and resolves the actual regclass to use by using | |
518 | /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. | |
519 | class PointerLikeRegClass<int Kind> { | |
520 | int RegClassKind = Kind; | |
521 | } | |
522 | ||
523 | ||
524 | /// ptr_rc definition - Mark this operand as being a pointer value whose | |
525 | /// register class is resolved dynamically via a callback to TargetInstrInfo. | |
526 | /// FIXME: We should probably change this to a class which contain a list of | |
527 | /// flags. But currently we have but one flag. | |
528 | def ptr_rc : PointerLikeRegClass<0>; | |
529 | ||
530 | /// unknown definition - Mark this operand as being of unknown type, causing | |
531 | /// it to be resolved by inference in the context it is used. | |
532 | class unknown_class; | |
533 | def unknown : unknown_class; | |
534 | ||
535 | /// AsmOperandClass - Representation for the kinds of operands which the target | |
536 | /// specific parser can create and the assembly matcher may need to distinguish. | |
537 | /// | |
538 | /// Operand classes are used to define the order in which instructions are | |
539 | /// matched, to ensure that the instruction which gets matched for any | |
540 | /// particular list of operands is deterministic. | |
541 | /// | |
542 | /// The target specific parser must be able to classify a parsed operand into a | |
543 | /// unique class which does not partially overlap with any other classes. It can | |
544 | /// match a subset of some other class, in which case the super class field | |
545 | /// should be defined. | |
546 | class AsmOperandClass { | |
547 | /// The name to use for this class, which should be usable as an enum value. | |
548 | string Name = ?; | |
549 | ||
550 | /// The super classes of this operand. | |
551 | list<AsmOperandClass> SuperClasses = []; | |
552 | ||
553 | /// The name of the method on the target specific operand to call to test | |
554 | /// whether the operand is an instance of this class. If not set, this will | |
555 | /// default to "isFoo", where Foo is the AsmOperandClass name. The method | |
556 | /// signature should be: | |
557 | /// bool isFoo() const; | |
558 | string PredicateMethod = ?; | |
559 | ||
560 | /// The name of the method on the target specific operand to call to add the | |
561 | /// target specific operand to an MCInst. If not set, this will default to | |
562 | /// "addFooOperands", where Foo is the AsmOperandClass name. The method | |
563 | /// signature should be: | |
564 | /// void addFooOperands(MCInst &Inst, unsigned N) const; | |
565 | string RenderMethod = ?; | |
566 | ||
567 | /// The name of the method on the target specific operand to call to custom | |
568 | /// handle the operand parsing. This is useful when the operands do not relate | |
569 | /// to immediates or registers and are very instruction specific (as flags to | |
570 | /// set in a processor register, coprocessor number, ...). | |
571 | string ParserMethod = ?; | |
572 | ||
573 | // The diagnostic type to present when referencing this operand in a | |
574 | // match failure error message. By default, use a generic "invalid operand" | |
575 | // diagnostic. The target AsmParser maps these codes to text. | |
576 | string DiagnosticType = ""; | |
577 | } | |
578 | ||
579 | def ImmAsmOperand : AsmOperandClass { | |
580 | let Name = "Imm"; | |
581 | } | |
582 | ||
583 | /// Operand Types - These provide the built-in operand types that may be used | |
584 | /// by a target. Targets can optionally provide their own operand types as | |
585 | /// needed, though this should not be needed for RISC targets. | |
586 | class Operand<ValueType ty> : DAGOperand { | |
587 | ValueType Type = ty; | |
588 | string PrintMethod = "printOperand"; | |
589 | string EncoderMethod = ""; | |
590 | string DecoderMethod = ""; | |
223e47cc LB |
591 | string OperandType = "OPERAND_UNKNOWN"; |
592 | dag MIOperandInfo = (ops); | |
593 | ||
1a4d82fc JJ |
594 | // MCOperandPredicate - Optionally, a code fragment operating on |
595 | // const MCOperand &MCOp, and returning a bool, to indicate if | |
596 | // the value of MCOp is valid for the specific subclass of Operand | |
597 | code MCOperandPredicate; | |
598 | ||
223e47cc LB |
599 | // ParserMatchClass - The "match class" that operands of this type fit |
600 | // in. Match classes are used to define the order in which instructions are | |
601 | // match, to ensure that which instructions gets matched is deterministic. | |
602 | // | |
603 | // The target specific parser must be able to classify an parsed operand into | |
604 | // a unique class, which does not partially overlap with any other classes. It | |
605 | // can match a subset of some other class, in which case the AsmOperandClass | |
606 | // should declare the other operand as one of its super classes. | |
607 | AsmOperandClass ParserMatchClass = ImmAsmOperand; | |
608 | } | |
609 | ||
610 | class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> | |
611 | : DAGOperand { | |
612 | // RegClass - The register class of the operand. | |
613 | RegisterClass RegClass = regclass; | |
614 | // PrintMethod - The target method to call to print register operands of | |
615 | // this type. The method normally will just use an alt-name index to look | |
616 | // up the name to print. Default to the generic printOperand(). | |
617 | string PrintMethod = pm; | |
618 | // ParserMatchClass - The "match class" that operands of this type fit | |
619 | // in. Match classes are used to define the order in which instructions are | |
620 | // match, to ensure that which instructions gets matched is deterministic. | |
621 | // | |
622 | // The target specific parser must be able to classify an parsed operand into | |
623 | // a unique class, which does not partially overlap with any other classes. It | |
624 | // can match a subset of some other class, in which case the AsmOperandClass | |
625 | // should declare the other operand as one of its super classes. | |
626 | AsmOperandClass ParserMatchClass; | |
85aaf69f SL |
627 | |
628 | string OperandNamespace = "MCOI"; | |
629 | string OperandType = "OPERAND_REGISTER"; | |
223e47cc LB |
630 | } |
631 | ||
632 | let OperandType = "OPERAND_IMMEDIATE" in { | |
633 | def i1imm : Operand<i1>; | |
634 | def i8imm : Operand<i8>; | |
635 | def i16imm : Operand<i16>; | |
636 | def i32imm : Operand<i32>; | |
637 | def i64imm : Operand<i64>; | |
638 | ||
639 | def f32imm : Operand<f32>; | |
640 | def f64imm : Operand<f64>; | |
641 | } | |
642 | ||
643 | /// zero_reg definition - Special node to stand for the zero register. | |
644 | /// | |
645 | def zero_reg; | |
646 | ||
1a4d82fc JJ |
647 | /// All operands which the MC layer classifies as predicates should inherit from |
648 | /// this class in some manner. This is already handled for the most commonly | |
649 | /// used PredicateOperand, but may be useful in other circumstances. | |
650 | class PredicateOp; | |
651 | ||
223e47cc LB |
652 | /// OperandWithDefaultOps - This Operand class can be used as the parent class |
653 | /// for an Operand that needs to be initialized with a default value if | |
654 | /// no value is supplied in a pattern. This class can be used to simplify the | |
655 | /// pattern definitions for instructions that have target specific flags | |
656 | /// encoded as immediate operands. | |
657 | class OperandWithDefaultOps<ValueType ty, dag defaultops> | |
658 | : Operand<ty> { | |
659 | dag DefaultOps = defaultops; | |
660 | } | |
661 | ||
662 | /// PredicateOperand - This can be used to define a predicate operand for an | |
663 | /// instruction. OpTypes specifies the MIOperandInfo for the operand, and | |
664 | /// AlwaysVal specifies the value of this predicate when set to "always | |
665 | /// execute". | |
666 | class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> | |
1a4d82fc | 667 | : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { |
223e47cc LB |
668 | let MIOperandInfo = OpTypes; |
669 | } | |
670 | ||
671 | /// OptionalDefOperand - This is used to define a optional definition operand | |
672 | /// for an instruction. DefaultOps is the register the operand represents if | |
673 | /// none is supplied, e.g. zero_reg. | |
674 | class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> | |
675 | : OperandWithDefaultOps<ty, defaultops> { | |
676 | let MIOperandInfo = OpTypes; | |
677 | } | |
678 | ||
679 | ||
680 | // InstrInfo - This class should only be instantiated once to provide parameters | |
681 | // which are global to the target machine. | |
682 | // | |
683 | class InstrInfo { | |
684 | // Target can specify its instructions in either big or little-endian formats. | |
685 | // For instance, while both Sparc and PowerPC are big-endian platforms, the | |
686 | // Sparc manual specifies its instructions in the format [31..0] (big), while | |
687 | // PowerPC specifies them using the format [0..31] (little). | |
688 | bit isLittleEndianEncoding = 0; | |
689 | ||
690 | // The instruction properties mayLoad, mayStore, and hasSideEffects are unset | |
691 | // by default, and TableGen will infer their value from the instruction | |
692 | // pattern when possible. | |
693 | // | |
694 | // Normally, TableGen will issue an error it it can't infer the value of a | |
695 | // property that hasn't been set explicitly. When guessInstructionProperties | |
696 | // is set, it will guess a safe value instead. | |
697 | // | |
698 | // This option is a temporary migration help. It will go away. | |
699 | bit guessInstructionProperties = 1; | |
1a4d82fc JJ |
700 | |
701 | // TableGen's instruction encoder generator has support for matching operands | |
702 | // to bit-field variables both by name and by position. While matching by | |
703 | // name is preferred, this is currently not possible for complex operands, | |
704 | // and some targets still reply on the positional encoding rules. When | |
705 | // generating a decoder for such targets, the positional encoding rules must | |
706 | // be used by the decoder generator as well. | |
707 | // | |
708 | // This option is temporary; it will go away once the TableGen decoder | |
709 | // generator has better support for complex operands and targets have | |
710 | // migrated away from using positionally encoded operands. | |
711 | bit decodePositionallyEncodedOperands = 0; | |
712 | ||
713 | // When set, this indicates that there will be no overlap between those | |
714 | // operands that are matched by ordering (positional operands) and those | |
715 | // matched by name. | |
716 | // | |
717 | // This option is temporary; it will go away once the TableGen decoder | |
718 | // generator has better support for complex operands and targets have | |
719 | // migrated away from using positionally encoded operands. | |
720 | bit noNamedPositionallyEncodedOperands = 0; | |
223e47cc LB |
721 | } |
722 | ||
723 | // Standard Pseudo Instructions. | |
724 | // This list must match TargetOpcodes.h and CodeGenTarget.cpp. | |
725 | // Only these instructions are allowed in the TargetOpcode namespace. | |
726 | let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { | |
727 | def PHI : Instruction { | |
728 | let OutOperandList = (outs); | |
729 | let InOperandList = (ins variable_ops); | |
730 | let AsmString = "PHINODE"; | |
731 | } | |
732 | def INLINEASM : Instruction { | |
733 | let OutOperandList = (outs); | |
734 | let InOperandList = (ins variable_ops); | |
735 | let AsmString = ""; | |
85aaf69f | 736 | let hasSideEffects = 0; // Note side effect is encoded in an operand. |
223e47cc | 737 | } |
1a4d82fc | 738 | def CFI_INSTRUCTION : Instruction { |
223e47cc LB |
739 | let OutOperandList = (outs); |
740 | let InOperandList = (ins i32imm:$id); | |
741 | let AsmString = ""; | |
742 | let hasCtrlDep = 1; | |
743 | let isNotDuplicable = 1; | |
744 | } | |
745 | def EH_LABEL : Instruction { | |
746 | let OutOperandList = (outs); | |
747 | let InOperandList = (ins i32imm:$id); | |
748 | let AsmString = ""; | |
749 | let hasCtrlDep = 1; | |
750 | let isNotDuplicable = 1; | |
751 | } | |
752 | def GC_LABEL : Instruction { | |
753 | let OutOperandList = (outs); | |
754 | let InOperandList = (ins i32imm:$id); | |
755 | let AsmString = ""; | |
756 | let hasCtrlDep = 1; | |
757 | let isNotDuplicable = 1; | |
758 | } | |
759 | def KILL : Instruction { | |
760 | let OutOperandList = (outs); | |
761 | let InOperandList = (ins variable_ops); | |
762 | let AsmString = ""; | |
85aaf69f | 763 | let hasSideEffects = 0; |
223e47cc LB |
764 | } |
765 | def EXTRACT_SUBREG : Instruction { | |
766 | let OutOperandList = (outs unknown:$dst); | |
767 | let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); | |
768 | let AsmString = ""; | |
85aaf69f | 769 | let hasSideEffects = 0; |
223e47cc LB |
770 | } |
771 | def INSERT_SUBREG : Instruction { | |
772 | let OutOperandList = (outs unknown:$dst); | |
773 | let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); | |
774 | let AsmString = ""; | |
85aaf69f | 775 | let hasSideEffects = 0; |
223e47cc LB |
776 | let Constraints = "$supersrc = $dst"; |
777 | } | |
778 | def IMPLICIT_DEF : Instruction { | |
779 | let OutOperandList = (outs unknown:$dst); | |
780 | let InOperandList = (ins); | |
781 | let AsmString = ""; | |
85aaf69f | 782 | let hasSideEffects = 0; |
223e47cc LB |
783 | let isReMaterializable = 1; |
784 | let isAsCheapAsAMove = 1; | |
785 | } | |
786 | def SUBREG_TO_REG : Instruction { | |
787 | let OutOperandList = (outs unknown:$dst); | |
788 | let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); | |
789 | let AsmString = ""; | |
85aaf69f | 790 | let hasSideEffects = 0; |
223e47cc LB |
791 | } |
792 | def COPY_TO_REGCLASS : Instruction { | |
793 | let OutOperandList = (outs unknown:$dst); | |
794 | let InOperandList = (ins unknown:$src, i32imm:$regclass); | |
795 | let AsmString = ""; | |
85aaf69f | 796 | let hasSideEffects = 0; |
223e47cc LB |
797 | let isAsCheapAsAMove = 1; |
798 | } | |
799 | def DBG_VALUE : Instruction { | |
800 | let OutOperandList = (outs); | |
801 | let InOperandList = (ins variable_ops); | |
802 | let AsmString = "DBG_VALUE"; | |
85aaf69f | 803 | let hasSideEffects = 0; |
223e47cc LB |
804 | } |
805 | def REG_SEQUENCE : Instruction { | |
806 | let OutOperandList = (outs unknown:$dst); | |
85aaf69f | 807 | let InOperandList = (ins unknown:$supersrc, variable_ops); |
223e47cc | 808 | let AsmString = ""; |
85aaf69f | 809 | let hasSideEffects = 0; |
223e47cc LB |
810 | let isAsCheapAsAMove = 1; |
811 | } | |
812 | def COPY : Instruction { | |
813 | let OutOperandList = (outs unknown:$dst); | |
814 | let InOperandList = (ins unknown:$src); | |
815 | let AsmString = ""; | |
85aaf69f | 816 | let hasSideEffects = 0; |
223e47cc LB |
817 | let isAsCheapAsAMove = 1; |
818 | } | |
223e47cc LB |
819 | def BUNDLE : Instruction { |
820 | let OutOperandList = (outs); | |
821 | let InOperandList = (ins variable_ops); | |
822 | let AsmString = "BUNDLE"; | |
823 | } | |
824 | def LIFETIME_START : Instruction { | |
825 | let OutOperandList = (outs); | |
826 | let InOperandList = (ins i32imm:$id); | |
827 | let AsmString = "LIFETIME_START"; | |
85aaf69f | 828 | let hasSideEffects = 0; |
223e47cc LB |
829 | } |
830 | def LIFETIME_END : Instruction { | |
831 | let OutOperandList = (outs); | |
832 | let InOperandList = (ins i32imm:$id); | |
833 | let AsmString = "LIFETIME_END"; | |
85aaf69f | 834 | let hasSideEffects = 0; |
223e47cc | 835 | } |
1a4d82fc JJ |
836 | def STACKMAP : Instruction { |
837 | let OutOperandList = (outs); | |
838 | let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); | |
839 | let isCall = 1; | |
840 | let mayLoad = 1; | |
841 | let usesCustomInserter = 1; | |
842 | } | |
843 | def PATCHPOINT : Instruction { | |
844 | let OutOperandList = (outs unknown:$dst); | |
845 | let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, | |
846 | i32imm:$nargs, i32imm:$cc, variable_ops); | |
847 | let isCall = 1; | |
848 | let mayLoad = 1; | |
849 | let usesCustomInserter = 1; | |
850 | } | |
85aaf69f SL |
851 | def STATEPOINT : Instruction { |
852 | let OutOperandList = (outs); | |
853 | let InOperandList = (ins variable_ops); | |
854 | let usesCustomInserter = 1; | |
855 | let mayLoad = 1; | |
856 | let mayStore = 1; | |
857 | let hasSideEffects = 1; | |
858 | let isCall = 1; | |
859 | } | |
1a4d82fc JJ |
860 | def LOAD_STACK_GUARD : Instruction { |
861 | let OutOperandList = (outs ptr_rc:$dst); | |
862 | let InOperandList = (ins); | |
863 | let mayLoad = 1; | |
864 | bit isReMaterializable = 1; | |
865 | let hasSideEffects = 0; | |
866 | bit isPseudo = 1; | |
867 | } | |
85aaf69f SL |
868 | def FRAME_ALLOC : Instruction { |
869 | // This instruction is really just a label. It has to be part of the chain so | |
870 | // that it doesn't get dropped from the DAG, but it produces nothing and has | |
871 | // no side effects. | |
872 | let OutOperandList = (outs); | |
873 | let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); | |
874 | let hasSideEffects = 0; | |
875 | let hasCtrlDep = 1; | |
876 | } | |
223e47cc LB |
877 | } |
878 | ||
879 | //===----------------------------------------------------------------------===// | |
880 | // AsmParser - This class can be implemented by targets that wish to implement | |
881 | // .s file parsing. | |
882 | // | |
883 | // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel | |
884 | // syntax on X86 for example). | |
885 | // | |
886 | class AsmParser { | |
887 | // AsmParserClassName - This specifies the suffix to use for the asmparser | |
888 | // class. Generated AsmParser classes are always prefixed with the target | |
889 | // name. | |
890 | string AsmParserClassName = "AsmParser"; | |
891 | ||
892 | // AsmParserInstCleanup - If non-empty, this is the name of a custom member | |
893 | // function of the AsmParser class to call on every matched instruction. | |
894 | // This can be used to perform target specific instruction post-processing. | |
895 | string AsmParserInstCleanup = ""; | |
896 | ||
1a4d82fc JJ |
897 | // ShouldEmitMatchRegisterName - Set to false if the target needs a hand |
898 | // written register name matcher | |
223e47cc | 899 | bit ShouldEmitMatchRegisterName = 1; |
1a4d82fc JJ |
900 | |
901 | /// Does the instruction mnemonic allow '.' | |
902 | bit MnemonicContainsDot = 0; | |
223e47cc LB |
903 | } |
904 | def DefaultAsmParser : AsmParser; | |
905 | ||
906 | //===----------------------------------------------------------------------===// | |
907 | // AsmParserVariant - Subtargets can have multiple different assembly parsers | |
908 | // (e.g. AT&T vs Intel syntax on X86 for example). This class can be | |
909 | // implemented by targets to describe such variants. | |
910 | // | |
911 | class AsmParserVariant { | |
912 | // Variant - AsmParsers can be of multiple different variants. Variants are | |
913 | // used to support targets that need to parser multiple formats for the | |
914 | // assembly language. | |
915 | int Variant = 0; | |
916 | ||
1a4d82fc JJ |
917 | // Name - The AsmParser variant name (e.g., AT&T vs Intel). |
918 | string Name = ""; | |
919 | ||
223e47cc LB |
920 | // CommentDelimiter - If given, the delimiter string used to recognize |
921 | // comments which are hard coded in the .td assembler strings for individual | |
922 | // instructions. | |
923 | string CommentDelimiter = ""; | |
924 | ||
925 | // RegisterPrefix - If given, the token prefix which indicates a register | |
926 | // token. This is used by the matcher to automatically recognize hard coded | |
927 | // register tokens as constrained registers, instead of tokens, for the | |
928 | // purposes of matching. | |
929 | string RegisterPrefix = ""; | |
930 | } | |
931 | def DefaultAsmParserVariant : AsmParserVariant; | |
932 | ||
933 | /// AssemblerPredicate - This is a Predicate that can be used when the assembler | |
934 | /// matches instructions and aliases. | |
935 | class AssemblerPredicate<string cond, string name = ""> { | |
936 | bit AssemblerMatcherPredicate = 1; | |
937 | string AssemblerCondString = cond; | |
938 | string PredicateName = name; | |
939 | } | |
940 | ||
941 | /// TokenAlias - This class allows targets to define assembler token | |
942 | /// operand aliases. That is, a token literal operand which is equivalent | |
943 | /// to another, canonical, token literal. For example, ARM allows: | |
944 | /// vmov.u32 s4, #0 -> vmov.i32, #0 | |
945 | /// 'u32' is a more specific designator for the 32-bit integer type specifier | |
946 | /// and is legal for any instruction which accepts 'i32' as a datatype suffix. | |
947 | /// def : TokenAlias<".u32", ".i32">; | |
948 | /// | |
949 | /// This works by marking the match class of 'From' as a subclass of the | |
950 | /// match class of 'To'. | |
951 | class TokenAlias<string From, string To> { | |
952 | string FromToken = From; | |
953 | string ToToken = To; | |
954 | } | |
955 | ||
956 | /// MnemonicAlias - This class allows targets to define assembler mnemonic | |
957 | /// aliases. This should be used when all forms of one mnemonic are accepted | |
958 | /// with a different mnemonic. For example, X86 allows: | |
959 | /// sal %al, 1 -> shl %al, 1 | |
960 | /// sal %ax, %cl -> shl %ax, %cl | |
961 | /// sal %eax, %cl -> shl %eax, %cl | |
962 | /// etc. Though "sal" is accepted with many forms, all of them are directly | |
963 | /// translated to a shl, so it can be handled with (in the case of X86, it | |
964 | /// actually has one for each suffix as well): | |
965 | /// def : MnemonicAlias<"sal", "shl">; | |
966 | /// | |
967 | /// Mnemonic aliases are mapped before any other translation in the match phase, | |
968 | /// and do allow Requires predicates, e.g.: | |
969 | /// | |
970 | /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; | |
971 | /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; | |
972 | /// | |
1a4d82fc JJ |
973 | /// Mnemonic aliases can also be constrained to specific variants, e.g.: |
974 | /// | |
975 | /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; | |
976 | /// | |
977 | /// If no variant (e.g., "att" or "intel") is specified then the alias is | |
978 | /// applied unconditionally. | |
979 | class MnemonicAlias<string From, string To, string VariantName = ""> { | |
223e47cc LB |
980 | string FromMnemonic = From; |
981 | string ToMnemonic = To; | |
1a4d82fc | 982 | string AsmVariantName = VariantName; |
223e47cc LB |
983 | |
984 | // Predicates - Predicates that must be true for this remapping to happen. | |
985 | list<Predicate> Predicates = []; | |
986 | } | |
987 | ||
988 | /// InstAlias - This defines an alternate assembly syntax that is allowed to | |
989 | /// match an instruction that has a different (more canonical) assembly | |
990 | /// representation. | |
1a4d82fc | 991 | class InstAlias<string Asm, dag Result, int Emit = 1> { |
223e47cc LB |
992 | string AsmString = Asm; // The .s format to match the instruction with. |
993 | dag ResultInst = Result; // The MCInst to generate. | |
1a4d82fc JJ |
994 | |
995 | // This determines which order the InstPrinter detects aliases for | |
996 | // printing. A larger value makes the alias more likely to be | |
997 | // emitted. The Instruction's own definition is notionally 0.5, so 0 | |
998 | // disables printing and 1 enables it if there are no conflicting aliases. | |
999 | int EmitPriority = Emit; | |
223e47cc LB |
1000 | |
1001 | // Predicates - Predicates that must be true for this to match. | |
1002 | list<Predicate> Predicates = []; | |
1003 | } | |
1004 | ||
1005 | //===----------------------------------------------------------------------===// | |
1006 | // AsmWriter - This class can be implemented by targets that need to customize | |
1007 | // the format of the .s file writer. | |
1008 | // | |
1009 | // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax | |
1010 | // on X86 for example). | |
1011 | // | |
1012 | class AsmWriter { | |
1013 | // AsmWriterClassName - This specifies the suffix to use for the asmwriter | |
1014 | // class. Generated AsmWriter classes are always prefixed with the target | |
1015 | // name. | |
1a4d82fc | 1016 | string AsmWriterClassName = "InstPrinter"; |
223e47cc LB |
1017 | |
1018 | // Variant - AsmWriters can be of multiple different variants. Variants are | |
1019 | // used to support targets that need to emit assembly code in ways that are | |
1020 | // mostly the same for different targets, but have minor differences in | |
1021 | // syntax. If the asmstring contains {|} characters in them, this integer | |
1022 | // will specify which alternative to use. For example "{x|y|z}" with Variant | |
1023 | // == 1, will expand to "y". | |
1024 | int Variant = 0; | |
223e47cc LB |
1025 | } |
1026 | def DefaultAsmWriter : AsmWriter; | |
1027 | ||
1028 | ||
1029 | //===----------------------------------------------------------------------===// | |
1030 | // Target - This class contains the "global" target information | |
1031 | // | |
1032 | class Target { | |
1033 | // InstructionSet - Instruction set description for this target. | |
1034 | InstrInfo InstructionSet; | |
1035 | ||
1036 | // AssemblyParsers - The AsmParser instances available for this target. | |
1037 | list<AsmParser> AssemblyParsers = [DefaultAsmParser]; | |
1038 | ||
1039 | /// AssemblyParserVariants - The AsmParserVariant instances available for | |
1040 | /// this target. | |
1041 | list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; | |
1042 | ||
1043 | // AssemblyWriters - The AsmWriter instances available for this target. | |
1044 | list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; | |
1045 | } | |
1046 | ||
1047 | //===----------------------------------------------------------------------===// | |
1048 | // SubtargetFeature - A characteristic of the chip set. | |
1049 | // | |
1050 | class SubtargetFeature<string n, string a, string v, string d, | |
1051 | list<SubtargetFeature> i = []> { | |
1052 | // Name - Feature name. Used by command line (-mattr=) to determine the | |
1053 | // appropriate target chip. | |
1054 | // | |
1055 | string Name = n; | |
1056 | ||
1057 | // Attribute - Attribute to be set by feature. | |
1058 | // | |
1059 | string Attribute = a; | |
1060 | ||
1061 | // Value - Value the attribute to be set to by feature. | |
1062 | // | |
1063 | string Value = v; | |
1064 | ||
1065 | // Desc - Feature description. Used by command line (-mattr=) to display help | |
1066 | // information. | |
1067 | // | |
1068 | string Desc = d; | |
1069 | ||
1070 | // Implies - Features that this feature implies are present. If one of those | |
1071 | // features isn't set, then this one shouldn't be set either. | |
1072 | // | |
1073 | list<SubtargetFeature> Implies = i; | |
1074 | } | |
1075 | ||
1a4d82fc JJ |
1076 | /// Specifies a Subtarget feature that this instruction is deprecated on. |
1077 | class Deprecated<SubtargetFeature dep> { | |
1078 | SubtargetFeature DeprecatedFeatureMask = dep; | |
1079 | } | |
1080 | ||
1081 | /// A custom predicate used to determine if an instruction is | |
1082 | /// deprecated or not. | |
1083 | class ComplexDeprecationPredicate<string dep> { | |
1084 | string ComplexDeprecationPredicate = dep; | |
1085 | } | |
1086 | ||
223e47cc LB |
1087 | //===----------------------------------------------------------------------===// |
1088 | // Processor chip sets - These values represent each of the chip sets supported | |
1089 | // by the scheduler. Each Processor definition requires corresponding | |
1090 | // instruction itineraries. | |
1091 | // | |
1092 | class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { | |
1093 | // Name - Chip set name. Used by command line (-mcpu=) to determine the | |
1094 | // appropriate target chip. | |
1095 | // | |
1096 | string Name = n; | |
1097 | ||
1098 | // SchedModel - The machine model for scheduling and instruction cost. | |
1099 | // | |
1100 | SchedMachineModel SchedModel = NoSchedModel; | |
1101 | ||
1102 | // ProcItin - The scheduling information for the target processor. | |
1103 | // | |
1104 | ProcessorItineraries ProcItin = pi; | |
1105 | ||
1106 | // Features - list of | |
1107 | list<SubtargetFeature> Features = f; | |
1108 | } | |
1109 | ||
1110 | // ProcessorModel allows subtargets to specify the more general | |
1111 | // SchedMachineModel instead if a ProcessorItinerary. Subtargets will | |
1112 | // gradually move to this newer form. | |
1113 | // | |
1114 | // Although this class always passes NoItineraries to the Processor | |
1115 | // class, the SchedMachineModel may still define valid Itineraries. | |
1116 | class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> | |
1117 | : Processor<n, NoItineraries, f> { | |
1118 | let SchedModel = m; | |
1119 | } | |
1120 | ||
970d7e83 LB |
1121 | //===----------------------------------------------------------------------===// |
1122 | // InstrMapping - This class is used to create mapping tables to relate | |
1123 | // instructions with each other based on the values specified in RowFields, | |
1124 | // ColFields, KeyCol and ValueCols. | |
1125 | // | |
1126 | class InstrMapping { | |
1127 | // FilterClass - Used to limit search space only to the instructions that | |
1128 | // define the relationship modeled by this InstrMapping record. | |
1129 | string FilterClass; | |
1130 | ||
1131 | // RowFields - List of fields/attributes that should be same for all the | |
1132 | // instructions in a row of the relation table. Think of this as a set of | |
1133 | // properties shared by all the instructions related by this relationship | |
1134 | // model and is used to categorize instructions into subgroups. For instance, | |
1135 | // if we want to define a relation that maps 'Add' instruction to its | |
1136 | // predicated forms, we can define RowFields like this: | |
1137 | // | |
1138 | // let RowFields = BaseOp | |
1139 | // All add instruction predicated/non-predicated will have to set their BaseOp | |
1140 | // to the same value. | |
1141 | // | |
1142 | // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } | |
1143 | // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } | |
1144 | // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } | |
1145 | list<string> RowFields = []; | |
1146 | ||
1147 | // List of fields/attributes that are same for all the instructions | |
1148 | // in a column of the relation table. | |
1149 | // Ex: let ColFields = 'predSense' -- It means that the columns are arranged | |
1150 | // based on the 'predSense' values. All the instruction in a specific | |
1151 | // column have the same value and it is fixed for the column according | |
1152 | // to the values set in 'ValueCols'. | |
1153 | list<string> ColFields = []; | |
1154 | ||
1155 | // Values for the fields/attributes listed in 'ColFields'. | |
1156 | // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction | |
1157 | // that models this relation) should be non-predicated. | |
1158 | // In the example above, 'Add' is the key instruction. | |
1159 | list<string> KeyCol = []; | |
1160 | ||
1161 | // List of values for the fields/attributes listed in 'ColFields', one for | |
1162 | // each column in the relation table. | |
1163 | // | |
1164 | // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the | |
1165 | // table. First column requires all the instructions to have predSense | |
1166 | // set to 'true' and second column requires it to be 'false'. | |
1167 | list<list<string> > ValueCols = []; | |
1168 | } | |
1169 | ||
223e47cc LB |
1170 | //===----------------------------------------------------------------------===// |
1171 | // Pull in the common support for calling conventions. | |
1172 | // | |
1173 | include "llvm/Target/TargetCallingConv.td" | |
1174 | ||
1175 | //===----------------------------------------------------------------------===// | |
1176 | // Pull in the common support for DAG isel generation. | |
1177 | // | |
1178 | include "llvm/Target/TargetSelectionDAG.td" |