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1 | //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo | |
11 | // instructions after register allocation. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | #define DEBUG_TYPE "postrapseudos" | |
16 | #include "llvm/CodeGen/Passes.h" | |
17 | #include "llvm/CodeGen/MachineFunctionPass.h" | |
18 | #include "llvm/CodeGen/MachineInstr.h" | |
19 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |
20 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |
223e47cc LB |
21 | #include "llvm/Support/Debug.h" |
22 | #include "llvm/Support/raw_ostream.h" | |
970d7e83 LB |
23 | #include "llvm/Target/TargetInstrInfo.h" |
24 | #include "llvm/Target/TargetMachine.h" | |
25 | #include "llvm/Target/TargetRegisterInfo.h" | |
223e47cc LB |
26 | using namespace llvm; |
27 | ||
28 | namespace { | |
29 | struct ExpandPostRA : public MachineFunctionPass { | |
30 | private: | |
31 | const TargetRegisterInfo *TRI; | |
32 | const TargetInstrInfo *TII; | |
33 | ||
34 | public: | |
35 | static char ID; // Pass identification, replacement for typeid | |
36 | ExpandPostRA() : MachineFunctionPass(ID) {} | |
37 | ||
38 | virtual void getAnalysisUsage(AnalysisUsage &AU) const { | |
39 | AU.setPreservesCFG(); | |
40 | AU.addPreservedID(MachineLoopInfoID); | |
41 | AU.addPreservedID(MachineDominatorsID); | |
42 | MachineFunctionPass::getAnalysisUsage(AU); | |
43 | } | |
44 | ||
45 | /// runOnMachineFunction - pass entry point | |
46 | bool runOnMachineFunction(MachineFunction&); | |
47 | ||
48 | private: | |
49 | bool LowerSubregToReg(MachineInstr *MI); | |
50 | bool LowerCopy(MachineInstr *MI); | |
51 | ||
223e47cc LB |
52 | void TransferImplicitDefs(MachineInstr *MI); |
53 | }; | |
54 | } // end anonymous namespace | |
55 | ||
56 | char ExpandPostRA::ID = 0; | |
57 | char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID; | |
58 | ||
59 | INITIALIZE_PASS(ExpandPostRA, "postrapseudos", | |
60 | "Post-RA pseudo instruction expansion pass", false, false) | |
61 | ||
223e47cc LB |
62 | /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered |
63 | /// replacement instructions immediately precede it. Copy any implicit-def | |
64 | /// operands from MI to the replacement instruction. | |
65 | void | |
66 | ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { | |
67 | MachineBasicBlock::iterator CopyMI = MI; | |
68 | --CopyMI; | |
69 | ||
70 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { | |
71 | MachineOperand &MO = MI->getOperand(i); | |
72 | if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) | |
73 | continue; | |
74 | CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true)); | |
75 | } | |
76 | } | |
77 | ||
78 | bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { | |
79 | MachineBasicBlock *MBB = MI->getParent(); | |
80 | assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && | |
81 | MI->getOperand(1).isImm() && | |
82 | (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && | |
83 | MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); | |
84 | ||
85 | unsigned DstReg = MI->getOperand(0).getReg(); | |
86 | unsigned InsReg = MI->getOperand(2).getReg(); | |
87 | assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); | |
88 | unsigned SubIdx = MI->getOperand(3).getImm(); | |
89 | ||
90 | assert(SubIdx != 0 && "Invalid index for insert_subreg"); | |
91 | unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); | |
92 | ||
93 | assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && | |
94 | "Insert destination must be in a physical register"); | |
95 | assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && | |
96 | "Inserted value must be in a physical register"); | |
97 | ||
98 | DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); | |
99 | ||
970d7e83 LB |
100 | if (MI->allDefsAreDead()) { |
101 | MI->setDesc(TII->get(TargetOpcode::KILL)); | |
102 | DEBUG(dbgs() << "subreg: replaced by: " << *MI); | |
103 | return true; | |
104 | } | |
105 | ||
223e47cc LB |
106 | if (DstSubReg == InsReg) { |
107 | // No need to insert an identify copy instruction. | |
108 | // Watch out for case like this: | |
109 | // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3 | |
110 | // We must leave %RAX live. | |
111 | if (DstReg != InsReg) { | |
112 | MI->setDesc(TII->get(TargetOpcode::KILL)); | |
113 | MI->RemoveOperand(3); // SubIdx | |
114 | MI->RemoveOperand(1); // Imm | |
115 | DEBUG(dbgs() << "subreg: replace by: " << *MI); | |
116 | return true; | |
117 | } | |
118 | DEBUG(dbgs() << "subreg: eliminated!"); | |
119 | } else { | |
120 | TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, | |
121 | MI->getOperand(2).isKill()); | |
122 | ||
123 | // Implicitly define DstReg for subsequent uses. | |
124 | MachineBasicBlock::iterator CopyMI = MI; | |
125 | --CopyMI; | |
126 | CopyMI->addRegisterDefined(DstReg); | |
223e47cc LB |
127 | DEBUG(dbgs() << "subreg: " << *CopyMI); |
128 | } | |
129 | ||
130 | DEBUG(dbgs() << '\n'); | |
131 | MBB->erase(MI); | |
132 | return true; | |
133 | } | |
134 | ||
135 | bool ExpandPostRA::LowerCopy(MachineInstr *MI) { | |
970d7e83 LB |
136 | |
137 | if (MI->allDefsAreDead()) { | |
138 | DEBUG(dbgs() << "dead copy: " << *MI); | |
139 | MI->setDesc(TII->get(TargetOpcode::KILL)); | |
140 | DEBUG(dbgs() << "replaced by: " << *MI); | |
141 | return true; | |
142 | } | |
143 | ||
223e47cc LB |
144 | MachineOperand &DstMO = MI->getOperand(0); |
145 | MachineOperand &SrcMO = MI->getOperand(1); | |
146 | ||
147 | if (SrcMO.getReg() == DstMO.getReg()) { | |
148 | DEBUG(dbgs() << "identity copy: " << *MI); | |
149 | // No need to insert an identity copy instruction, but replace with a KILL | |
150 | // if liveness is changed. | |
970d7e83 | 151 | if (SrcMO.isUndef() || MI->getNumOperands() > 2) { |
223e47cc LB |
152 | // We must make sure the super-register gets killed. Replace the |
153 | // instruction with KILL. | |
154 | MI->setDesc(TII->get(TargetOpcode::KILL)); | |
155 | DEBUG(dbgs() << "replaced by: " << *MI); | |
156 | return true; | |
157 | } | |
158 | // Vanilla identity copy. | |
159 | MI->eraseFromParent(); | |
160 | return true; | |
161 | } | |
162 | ||
163 | DEBUG(dbgs() << "real copy: " << *MI); | |
164 | TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), | |
165 | DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); | |
166 | ||
223e47cc LB |
167 | if (MI->getNumOperands() > 2) |
168 | TransferImplicitDefs(MI); | |
169 | DEBUG({ | |
170 | MachineBasicBlock::iterator dMI = MI; | |
171 | dbgs() << "replaced by: " << *(--dMI); | |
172 | }); | |
173 | MI->eraseFromParent(); | |
174 | return true; | |
175 | } | |
176 | ||
177 | /// runOnMachineFunction - Reduce subregister inserts and extracts to register | |
178 | /// copies. | |
179 | /// | |
180 | bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) { | |
181 | DEBUG(dbgs() << "Machine Function\n" | |
182 | << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" | |
183 | << "********** Function: " << MF.getName() << '\n'); | |
184 | TRI = MF.getTarget().getRegisterInfo(); | |
185 | TII = MF.getTarget().getInstrInfo(); | |
186 | ||
187 | bool MadeChange = false; | |
188 | ||
189 | for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); | |
190 | mbbi != mbbe; ++mbbi) { | |
191 | for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); | |
192 | mi != me;) { | |
193 | MachineInstr *MI = mi; | |
194 | // Advance iterator here because MI may be erased. | |
195 | ++mi; | |
196 | ||
197 | // Only expand pseudos. | |
198 | if (!MI->isPseudo()) | |
199 | continue; | |
200 | ||
201 | // Give targets a chance to expand even standard pseudos. | |
202 | if (TII->expandPostRAPseudo(MI)) { | |
203 | MadeChange = true; | |
204 | continue; | |
205 | } | |
206 | ||
207 | // Expand standard pseudos. | |
208 | switch (MI->getOpcode()) { | |
209 | case TargetOpcode::SUBREG_TO_REG: | |
210 | MadeChange |= LowerSubregToReg(MI); | |
211 | break; | |
212 | case TargetOpcode::COPY: | |
213 | MadeChange |= LowerCopy(MI); | |
214 | break; | |
215 | case TargetOpcode::DBG_VALUE: | |
216 | continue; | |
217 | case TargetOpcode::INSERT_SUBREG: | |
218 | case TargetOpcode::EXTRACT_SUBREG: | |
219 | llvm_unreachable("Sub-register pseudos should have been eliminated."); | |
220 | } | |
221 | } | |
222 | } | |
223 | ||
224 | return MadeChange; | |
225 | } |