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223e47cc LB |
1 | //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file contains the base ARM implementation of TargetRegisterInfo class. | |
11 | // | |
12 | //===----------------------------------------------------------------------===// | |
13 | ||
14 | #include "ARMBaseRegisterInfo.h" | |
15 | #include "ARM.h" | |
16 | #include "ARMBaseInstrInfo.h" | |
17 | #include "ARMFrameLowering.h" | |
18 | #include "ARMMachineFunctionInfo.h" | |
19 | #include "ARMSubtarget.h" | |
20 | #include "MCTargetDesc/ARMAddressingModes.h" | |
970d7e83 LB |
21 | #include "llvm/ADT/BitVector.h" |
22 | #include "llvm/ADT/SmallVector.h" | |
223e47cc LB |
23 | #include "llvm/CodeGen/MachineConstantPool.h" |
24 | #include "llvm/CodeGen/MachineFrameInfo.h" | |
25 | #include "llvm/CodeGen/MachineFunction.h" | |
26 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |
27 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |
28 | #include "llvm/CodeGen/RegisterScavenging.h" | |
970d7e83 LB |
29 | #include "llvm/CodeGen/VirtRegMap.h" |
30 | #include "llvm/IR/Constants.h" | |
31 | #include "llvm/IR/DerivedTypes.h" | |
32 | #include "llvm/IR/Function.h" | |
33 | #include "llvm/IR/LLVMContext.h" | |
223e47cc LB |
34 | #include "llvm/Support/Debug.h" |
35 | #include "llvm/Support/ErrorHandling.h" | |
36 | #include "llvm/Support/raw_ostream.h" | |
37 | #include "llvm/Target/TargetFrameLowering.h" | |
38 | #include "llvm/Target/TargetMachine.h" | |
39 | #include "llvm/Target/TargetOptions.h" | |
223e47cc | 40 | |
1a4d82fc JJ |
41 | #define DEBUG_TYPE "arm-register-info" |
42 | ||
223e47cc LB |
43 | #define GET_REGINFO_TARGET_DESC |
44 | #include "ARMGenRegisterInfo.inc" | |
45 | ||
46 | using namespace llvm; | |
47 | ||
1a4d82fc JJ |
48 | ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) |
49 | : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) { | |
50 | if (STI.isTargetMachO()) { | |
51 | if (STI.isTargetDarwin() || STI.isThumb1Only()) | |
52 | FramePtr = ARM::R7; | |
53 | else | |
54 | FramePtr = ARM::R11; | |
55 | } else if (STI.isTargetWindows()) | |
56 | FramePtr = ARM::R11; | |
57 | else // ARM EABI | |
58 | FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11; | |
223e47cc LB |
59 | } |
60 | ||
1a4d82fc | 61 | const MCPhysReg* |
223e47cc | 62 | ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
85aaf69f SL |
63 | const MCPhysReg *RegList = |
64 | STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; | |
1a4d82fc JJ |
65 | |
66 | if (!MF) return RegList; | |
67 | ||
68 | const Function *F = MF->getFunction(); | |
69 | if (F->getCallingConv() == CallingConv::GHC) { | |
70 | // GHC set of callee saved regs is empty as all those regs are | |
71 | // used for passing STG regs around | |
72 | return CSR_NoRegs_SaveList; | |
73 | } else if (F->hasFnAttribute("interrupt")) { | |
74 | if (STI.isMClass()) { | |
75 | // M-class CPUs have hardware which saves the registers needed to allow a | |
76 | // function conforming to the AAPCS to function as a handler. | |
77 | return CSR_AAPCS_SaveList; | |
78 | } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { | |
79 | // Fast interrupt mode gives the handler a private copy of R8-R14, so less | |
80 | // need to be saved to restore user-mode state. | |
81 | return CSR_FIQ_SaveList; | |
82 | } else { | |
83 | // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by | |
84 | // exception handling. | |
85 | return CSR_GenericInt_SaveList; | |
86 | } | |
223e47cc | 87 | } |
1a4d82fc JJ |
88 | |
89 | return RegList; | |
223e47cc LB |
90 | } |
91 | ||
92 | const uint32_t* | |
1a4d82fc JJ |
93 | ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { |
94 | if (CC == CallingConv::GHC) | |
95 | // This is academic becase all GHC calls are (supposed to be) tail calls | |
96 | return CSR_NoRegs_RegMask; | |
85aaf69f | 97 | return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; |
223e47cc LB |
98 | } |
99 | ||
970d7e83 LB |
100 | const uint32_t* |
101 | ARMBaseRegisterInfo::getNoPreservedMask() const { | |
102 | return CSR_NoRegs_RegMask; | |
103 | } | |
104 | ||
1a4d82fc JJ |
105 | const uint32_t* |
106 | ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { | |
107 | // This should return a register mask that is the same as that returned by | |
108 | // getCallPreservedMask but that additionally preserves the register used for | |
109 | // the first i32 argument (which must also be the register used to return a | |
110 | // single i32 return value) | |
111 | // | |
112 | // In case that the calling convention does not use the same register for | |
113 | // both or otherwise does not want to enable this optimization, the function | |
114 | // should return NULL | |
115 | if (CC == CallingConv::GHC) | |
116 | // This is academic becase all GHC calls are (supposed to be) tail calls | |
117 | return nullptr; | |
85aaf69f SL |
118 | return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask |
119 | : CSR_AAPCS_ThisReturn_RegMask; | |
1a4d82fc JJ |
120 | } |
121 | ||
223e47cc LB |
122 | BitVector ARMBaseRegisterInfo:: |
123 | getReservedRegs(const MachineFunction &MF) const { | |
1a4d82fc | 124 | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
223e47cc LB |
125 | |
126 | // FIXME: avoid re-calculating this every time. | |
127 | BitVector Reserved(getNumRegs()); | |
128 | Reserved.set(ARM::SP); | |
129 | Reserved.set(ARM::PC); | |
130 | Reserved.set(ARM::FPSCR); | |
1a4d82fc | 131 | Reserved.set(ARM::APSR_NZCV); |
223e47cc LB |
132 | if (TFI->hasFP(MF)) |
133 | Reserved.set(FramePtr); | |
134 | if (hasBasePointer(MF)) | |
135 | Reserved.set(BasePtr); | |
136 | // Some targets reserve R9. | |
137 | if (STI.isR9Reserved()) | |
138 | Reserved.set(ARM::R9); | |
139 | // Reserve D16-D31 if the subtarget doesn't support them. | |
140 | if (!STI.hasVFP3() || STI.hasD16()) { | |
141 | assert(ARM::D31 == ARM::D16 + 15); | |
142 | for (unsigned i = 0; i != 16; ++i) | |
143 | Reserved.set(ARM::D16 + i); | |
144 | } | |
970d7e83 LB |
145 | const TargetRegisterClass *RC = &ARM::GPRPairRegClass; |
146 | for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) | |
147 | for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) | |
148 | if (Reserved.test(*SI)) Reserved.set(*I); | |
223e47cc | 149 | |
970d7e83 | 150 | return Reserved; |
223e47cc LB |
151 | } |
152 | ||
153 | const TargetRegisterClass* | |
154 | ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) | |
155 | const { | |
156 | const TargetRegisterClass *Super = RC; | |
157 | TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); | |
158 | do { | |
159 | switch (Super->getID()) { | |
160 | case ARM::GPRRegClassID: | |
161 | case ARM::SPRRegClassID: | |
162 | case ARM::DPRRegClassID: | |
163 | case ARM::QPRRegClassID: | |
164 | case ARM::QQPRRegClassID: | |
165 | case ARM::QQQQPRRegClassID: | |
970d7e83 | 166 | case ARM::GPRPairRegClassID: |
223e47cc LB |
167 | return Super; |
168 | } | |
169 | Super = *I++; | |
170 | } while (Super); | |
171 | return RC; | |
172 | } | |
173 | ||
174 | const TargetRegisterClass * | |
175 | ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) | |
176 | const { | |
177 | return &ARM::GPRRegClass; | |
178 | } | |
179 | ||
180 | const TargetRegisterClass * | |
181 | ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { | |
182 | if (RC == &ARM::CCRRegClass) | |
85aaf69f | 183 | return &ARM::rGPRRegClass; // Can't copy CCR registers. |
223e47cc LB |
184 | return RC; |
185 | } | |
186 | ||
187 | unsigned | |
188 | ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, | |
189 | MachineFunction &MF) const { | |
1a4d82fc | 190 | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
223e47cc LB |
191 | |
192 | switch (RC->getID()) { | |
193 | default: | |
194 | return 0; | |
195 | case ARM::tGPRRegClassID: | |
196 | return TFI->hasFP(MF) ? 4 : 5; | |
197 | case ARM::GPRRegClassID: { | |
198 | unsigned FP = TFI->hasFP(MF) ? 1 : 0; | |
199 | return 10 - FP - (STI.isR9Reserved() ? 1 : 0); | |
200 | } | |
201 | case ARM::SPRRegClassID: // Currently not used as 'rep' register class. | |
202 | case ARM::DPRRegClassID: | |
203 | return 32 - 10; | |
204 | } | |
205 | } | |
206 | ||
970d7e83 LB |
207 | // Get the other register in a GPRPair. |
208 | static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { | |
209 | for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) | |
210 | if (ARM::GPRPairRegClass.contains(*Supers)) | |
211 | return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); | |
212 | return 0; | |
223e47cc LB |
213 | } |
214 | ||
970d7e83 LB |
215 | // Resolve the RegPairEven / RegPairOdd register allocator hints. |
216 | void | |
217 | ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, | |
218 | ArrayRef<MCPhysReg> Order, | |
219 | SmallVectorImpl<MCPhysReg> &Hints, | |
220 | const MachineFunction &MF, | |
221 | const VirtRegMap *VRM) const { | |
222 | const MachineRegisterInfo &MRI = MF.getRegInfo(); | |
223 | std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); | |
224 | ||
225 | unsigned Odd; | |
226 | switch (Hint.first) { | |
227 | case ARMRI::RegPairEven: | |
228 | Odd = 0; | |
229 | break; | |
230 | case ARMRI::RegPairOdd: | |
231 | Odd = 1; | |
232 | break; | |
233 | default: | |
234 | TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); | |
235 | return; | |
236 | } | |
237 | ||
238 | // This register should preferably be even (Odd == 0) or odd (Odd == 1). | |
239 | // Check if the other part of the pair has already been assigned, and provide | |
240 | // the paired register as the first hint. | |
241 | unsigned PairedPhys = 0; | |
242 | if (VRM && VRM->hasPhys(Hint.second)) { | |
243 | PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); | |
244 | if (PairedPhys && MRI.isReserved(PairedPhys)) | |
245 | PairedPhys = 0; | |
246 | } | |
247 | ||
248 | // First prefer the paired physreg. | |
249 | if (PairedPhys && | |
250 | std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) | |
251 | Hints.push_back(PairedPhys); | |
252 | ||
253 | // Then prefer even or odd registers. | |
254 | for (unsigned I = 0, E = Order.size(); I != E; ++I) { | |
255 | unsigned Reg = Order[I]; | |
256 | if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) | |
257 | continue; | |
258 | // Don't provide hints that are paired to a reserved register. | |
259 | unsigned Paired = getPairedGPR(Reg, !Odd, this); | |
260 | if (!Paired || MRI.isReserved(Paired)) | |
261 | continue; | |
262 | Hints.push_back(Reg); | |
263 | } | |
223e47cc LB |
264 | } |
265 | ||
266 | void | |
267 | ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, | |
268 | MachineFunction &MF) const { | |
269 | MachineRegisterInfo *MRI = &MF.getRegInfo(); | |
270 | std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); | |
271 | if ((Hint.first == (unsigned)ARMRI::RegPairOdd || | |
272 | Hint.first == (unsigned)ARMRI::RegPairEven) && | |
273 | TargetRegisterInfo::isVirtualRegister(Hint.second)) { | |
274 | // If 'Reg' is one of the even / odd register pair and it's now changed | |
275 | // (e.g. coalesced) into a different register. The other register of the | |
276 | // pair allocation hint must be updated to reflect the relationship | |
277 | // change. | |
278 | unsigned OtherReg = Hint.second; | |
279 | Hint = MRI->getRegAllocationHint(OtherReg); | |
280 | if (Hint.second == Reg) | |
281 | // Make sure the pair has not already divorced. | |
282 | MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); | |
283 | } | |
284 | } | |
285 | ||
286 | bool | |
287 | ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { | |
288 | // CortexA9 has a Write-after-write hazard for NEON registers. | |
289 | if (!STI.isLikeA9()) | |
290 | return false; | |
291 | ||
292 | switch (RC->getID()) { | |
293 | case ARM::DPRRegClassID: | |
294 | case ARM::DPR_8RegClassID: | |
295 | case ARM::DPR_VFP2RegClassID: | |
296 | case ARM::QPRRegClassID: | |
297 | case ARM::QPR_8RegClassID: | |
298 | case ARM::QPR_VFP2RegClassID: | |
299 | case ARM::SPRRegClassID: | |
300 | case ARM::SPR_8RegClassID: | |
301 | // Avoid reusing S, D, and Q registers. | |
302 | // Don't increase register pressure for QQ and QQQQ. | |
303 | return true; | |
304 | default: | |
305 | return false; | |
306 | } | |
307 | } | |
308 | ||
309 | bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { | |
310 | const MachineFrameInfo *MFI = MF.getFrameInfo(); | |
311 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |
1a4d82fc | 312 | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
223e47cc | 313 | |
223e47cc LB |
314 | // When outgoing call frames are so large that we adjust the stack pointer |
315 | // around the call, we can no longer use the stack pointer to reach the | |
316 | // emergency spill slot. | |
317 | if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) | |
318 | return true; | |
319 | ||
320 | // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited | |
321 | // negative range for ldr/str (255), and thumb1 is positive offsets only. | |
322 | // It's going to be better to use the SP or Base Pointer instead. When there | |
323 | // are variable sized objects, we can't reference off of the SP, so we | |
324 | // reserve a Base Pointer. | |
325 | if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { | |
326 | // Conservatively estimate whether the negative offset from the frame | |
327 | // pointer will be sufficient to reach. If a function has a smallish | |
328 | // frame, it's less likely to have lots of spills and callee saved | |
329 | // space, so it's all more likely to be within range of the frame pointer. | |
330 | // If it's wrong, the scavenger will still enable access to work, it just | |
331 | // won't be optimal. | |
332 | if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) | |
333 | return false; | |
334 | return true; | |
335 | } | |
336 | ||
337 | return false; | |
338 | } | |
339 | ||
340 | bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { | |
341 | const MachineRegisterInfo *MRI = &MF.getRegInfo(); | |
342 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |
343 | // We can't realign the stack if: | |
344 | // 1. Dynamic stack realignment is explicitly disabled, | |
345 | // 2. This is a Thumb1 function (it's not useful, so we don't bother), or | |
346 | // 3. There are VLAs in the function and the base pointer is disabled. | |
1a4d82fc | 347 | if (MF.getFunction()->hasFnAttribute("no-realign-stack")) |
223e47cc LB |
348 | return false; |
349 | if (AFI->isThumb1OnlyFunction()) | |
350 | return false; | |
351 | // Stack realignment requires a frame pointer. If we already started | |
352 | // register allocation with frame pointer elimination, it is too late now. | |
353 | if (!MRI->canReserveReg(FramePtr)) | |
354 | return false; | |
355 | // We may also need a base pointer if there are dynamic allocas or stack | |
356 | // pointer adjustments around calls. | |
1a4d82fc JJ |
357 | if (MF.getTarget() |
358 | .getSubtargetImpl() | |
359 | ->getFrameLowering() | |
360 | ->hasReservedCallFrame(MF)) | |
223e47cc | 361 | return true; |
223e47cc LB |
362 | // A base pointer is required and allowed. Check that it isn't too late to |
363 | // reserve it. | |
364 | return MRI->canReserveReg(BasePtr); | |
365 | } | |
366 | ||
367 | bool ARMBaseRegisterInfo:: | |
368 | needsStackRealignment(const MachineFunction &MF) const { | |
369 | const MachineFrameInfo *MFI = MF.getFrameInfo(); | |
370 | const Function *F = MF.getFunction(); | |
1a4d82fc JJ |
371 | unsigned StackAlign = MF.getTarget() |
372 | .getSubtargetImpl() | |
373 | ->getFrameLowering() | |
374 | ->getStackAlignment(); | |
970d7e83 LB |
375 | bool requiresRealignment = |
376 | ((MFI->getMaxAlignment() > StackAlign) || | |
377 | F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, | |
378 | Attribute::StackAlignment)); | |
223e47cc LB |
379 | |
380 | return requiresRealignment && canRealignStack(MF); | |
381 | } | |
382 | ||
383 | bool ARMBaseRegisterInfo:: | |
384 | cannotEliminateFrame(const MachineFunction &MF) const { | |
385 | const MachineFrameInfo *MFI = MF.getFrameInfo(); | |
386 | if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) | |
387 | return true; | |
388 | return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() | |
389 | || needsStackRealignment(MF); | |
390 | } | |
391 | ||
392 | unsigned | |
393 | ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { | |
1a4d82fc | 394 | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
223e47cc LB |
395 | |
396 | if (TFI->hasFP(MF)) | |
397 | return FramePtr; | |
398 | return ARM::SP; | |
399 | } | |
400 | ||
223e47cc LB |
401 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
402 | /// specified immediate. | |
403 | void ARMBaseRegisterInfo:: | |
404 | emitLoadConstPool(MachineBasicBlock &MBB, | |
405 | MachineBasicBlock::iterator &MBBI, | |
406 | DebugLoc dl, | |
407 | unsigned DestReg, unsigned SubIdx, int Val, | |
408 | ARMCC::CondCodes Pred, | |
409 | unsigned PredReg, unsigned MIFlags) const { | |
410 | MachineFunction &MF = *MBB.getParent(); | |
1a4d82fc | 411 | const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); |
223e47cc LB |
412 | MachineConstantPool *ConstantPool = MF.getConstantPool(); |
413 | const Constant *C = | |
414 | ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); | |
415 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); | |
416 | ||
417 | BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) | |
418 | .addReg(DestReg, getDefRegState(true), SubIdx) | |
419 | .addConstantPoolIndex(Idx) | |
420 | .addImm(0).addImm(Pred).addReg(PredReg) | |
421 | .setMIFlags(MIFlags); | |
422 | } | |
423 | ||
424 | bool ARMBaseRegisterInfo:: | |
425 | requiresRegisterScavenging(const MachineFunction &MF) const { | |
426 | return true; | |
427 | } | |
428 | ||
429 | bool ARMBaseRegisterInfo:: | |
430 | trackLivenessAfterRegAlloc(const MachineFunction &MF) const { | |
431 | return true; | |
432 | } | |
433 | ||
434 | bool ARMBaseRegisterInfo:: | |
435 | requiresFrameIndexScavenging(const MachineFunction &MF) const { | |
436 | return true; | |
437 | } | |
438 | ||
439 | bool ARMBaseRegisterInfo:: | |
440 | requiresVirtualBaseRegisters(const MachineFunction &MF) const { | |
970d7e83 | 441 | return true; |
223e47cc LB |
442 | } |
443 | ||
444 | int64_t ARMBaseRegisterInfo:: | |
445 | getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { | |
446 | const MCInstrDesc &Desc = MI->getDesc(); | |
447 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); | |
448 | int64_t InstrOffs = 0; | |
449 | int Scale = 1; | |
450 | unsigned ImmIdx = 0; | |
451 | switch (AddrMode) { | |
452 | case ARMII::AddrModeT2_i8: | |
453 | case ARMII::AddrModeT2_i12: | |
454 | case ARMII::AddrMode_i12: | |
455 | InstrOffs = MI->getOperand(Idx+1).getImm(); | |
456 | Scale = 1; | |
457 | break; | |
458 | case ARMII::AddrMode5: { | |
459 | // VFP address mode. | |
460 | const MachineOperand &OffOp = MI->getOperand(Idx+1); | |
461 | InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); | |
462 | if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) | |
463 | InstrOffs = -InstrOffs; | |
464 | Scale = 4; | |
465 | break; | |
466 | } | |
467 | case ARMII::AddrMode2: { | |
468 | ImmIdx = Idx+2; | |
469 | InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); | |
470 | if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) | |
471 | InstrOffs = -InstrOffs; | |
472 | break; | |
473 | } | |
474 | case ARMII::AddrMode3: { | |
475 | ImmIdx = Idx+2; | |
476 | InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); | |
477 | if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) | |
478 | InstrOffs = -InstrOffs; | |
479 | break; | |
480 | } | |
481 | case ARMII::AddrModeT1_s: { | |
482 | ImmIdx = Idx+1; | |
483 | InstrOffs = MI->getOperand(ImmIdx).getImm(); | |
484 | Scale = 4; | |
485 | break; | |
486 | } | |
487 | default: | |
488 | llvm_unreachable("Unsupported addressing mode!"); | |
489 | } | |
490 | ||
491 | return InstrOffs * Scale; | |
492 | } | |
493 | ||
494 | /// needsFrameBaseReg - Returns true if the instruction's frame index | |
495 | /// reference would be better served by a base register other than FP | |
496 | /// or SP. Used by LocalStackFrameAllocation to determine which frame index | |
497 | /// references it should create new base registers for. | |
498 | bool ARMBaseRegisterInfo:: | |
499 | needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { | |
500 | for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { | |
501 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); | |
502 | } | |
503 | ||
504 | // It's the load/store FI references that cause issues, as it can be difficult | |
505 | // to materialize the offset if it won't fit in the literal field. Estimate | |
506 | // based on the size of the local frame and some conservative assumptions | |
507 | // about the rest of the stack frame (note, this is pre-regalloc, so | |
508 | // we don't know everything for certain yet) whether this offset is likely | |
509 | // to be out of range of the immediate. Return true if so. | |
510 | ||
511 | // We only generate virtual base registers for loads and stores, so | |
512 | // return false for everything else. | |
513 | unsigned Opc = MI->getOpcode(); | |
514 | switch (Opc) { | |
515 | case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: | |
516 | case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: | |
517 | case ARM::t2LDRi12: case ARM::t2LDRi8: | |
518 | case ARM::t2STRi12: case ARM::t2STRi8: | |
519 | case ARM::VLDRS: case ARM::VLDRD: | |
520 | case ARM::VSTRS: case ARM::VSTRD: | |
521 | case ARM::tSTRspi: case ARM::tLDRspi: | |
223e47cc LB |
522 | break; |
523 | default: | |
524 | return false; | |
525 | } | |
526 | ||
527 | // Without a virtual base register, if the function has variable sized | |
528 | // objects, all fixed-size local references will be via the frame pointer, | |
529 | // Approximate the offset and see if it's legal for the instruction. | |
530 | // Note that the incoming offset is based on the SP value at function entry, | |
531 | // so it'll be negative. | |
532 | MachineFunction &MF = *MI->getParent()->getParent(); | |
1a4d82fc | 533 | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
223e47cc LB |
534 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
535 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); | |
536 | ||
537 | // Estimate an offset from the frame pointer. | |
538 | // Conservatively assume all callee-saved registers get pushed. R4-R6 | |
539 | // will be earlier than the FP, so we ignore those. | |
540 | // R7, LR | |
541 | int64_t FPOffset = Offset - 8; | |
542 | // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 | |
543 | if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) | |
544 | FPOffset -= 80; | |
545 | // Estimate an offset from the stack pointer. | |
546 | // The incoming offset is relating to the SP at the start of the function, | |
547 | // but when we access the local it'll be relative to the SP after local | |
548 | // allocation, so adjust our SP-relative offset by that allocation size. | |
549 | Offset = -Offset; | |
550 | Offset += MFI->getLocalFrameSize(); | |
551 | // Assume that we'll have at least some spill slots allocated. | |
552 | // FIXME: This is a total SWAG number. We should run some statistics | |
553 | // and pick a real one. | |
554 | Offset += 128; // 128 bytes of spill slots | |
555 | ||
556 | // If there is a frame pointer, try using it. | |
557 | // The FP is only available if there is no dynamic realignment. We | |
558 | // don't know for sure yet whether we'll need that, so we guess based | |
559 | // on whether there are any local variables that would trigger it. | |
560 | unsigned StackAlign = TFI->getStackAlignment(); | |
561 | if (TFI->hasFP(MF) && | |
562 | !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { | |
563 | if (isFrameOffsetLegal(MI, FPOffset)) | |
564 | return false; | |
565 | } | |
566 | // If we can reference via the stack pointer, try that. | |
567 | // FIXME: This (and the code that resolves the references) can be improved | |
568 | // to only disallow SP relative references in the live range of | |
569 | // the VLA(s). In practice, it's unclear how much difference that | |
570 | // would make, but it may be worth doing. | |
571 | if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) | |
572 | return false; | |
573 | ||
574 | // The offset likely isn't legal, we want to allocate a virtual base register. | |
575 | return true; | |
576 | } | |
577 | ||
578 | /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to | |
579 | /// be a pointer to FrameIdx at the beginning of the basic block. | |
580 | void ARMBaseRegisterInfo:: | |
581 | materializeFrameBaseRegister(MachineBasicBlock *MBB, | |
582 | unsigned BaseReg, int FrameIdx, | |
583 | int64_t Offset) const { | |
584 | ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); | |
585 | unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : | |
85aaf69f | 586 | (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); |
223e47cc LB |
587 | |
588 | MachineBasicBlock::iterator Ins = MBB->begin(); | |
589 | DebugLoc DL; // Defaults to "unknown" | |
590 | if (Ins != MBB->end()) | |
591 | DL = Ins->getDebugLoc(); | |
592 | ||
223e47cc | 593 | const MachineFunction &MF = *MBB->getParent(); |
1a4d82fc JJ |
594 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); |
595 | const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); | |
596 | const MCInstrDesc &MCID = TII.get(ADDriOpc); | |
223e47cc LB |
597 | MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); |
598 | ||
85aaf69f SL |
599 | MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) |
600 | .addFrameIndex(FrameIdx).addImm(Offset); | |
223e47cc LB |
601 | |
602 | if (!AFI->isThumb1OnlyFunction()) | |
85aaf69f | 603 | AddDefaultCC(AddDefaultPred(MIB)); |
223e47cc LB |
604 | } |
605 | ||
1a4d82fc JJ |
606 | void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, |
607 | int64_t Offset) const { | |
223e47cc LB |
608 | MachineBasicBlock &MBB = *MI.getParent(); |
609 | MachineFunction &MF = *MBB.getParent(); | |
1a4d82fc JJ |
610 | const ARMBaseInstrInfo &TII = |
611 | *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); | |
223e47cc LB |
612 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
613 | int Off = Offset; // ARM doesn't need the general 64-bit offsets | |
614 | unsigned i = 0; | |
615 | ||
616 | assert(!AFI->isThumb1OnlyFunction() && | |
617 | "This resolveFrameIndex does not support Thumb1!"); | |
618 | ||
619 | while (!MI.getOperand(i).isFI()) { | |
620 | ++i; | |
621 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); | |
622 | } | |
623 | bool Done = false; | |
624 | if (!AFI->isThumbFunction()) | |
625 | Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); | |
626 | else { | |
627 | assert(AFI->isThumb2Function()); | |
628 | Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); | |
629 | } | |
630 | assert (Done && "Unable to resolve frame index!"); | |
631 | (void)Done; | |
632 | } | |
633 | ||
634 | bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, | |
635 | int64_t Offset) const { | |
636 | const MCInstrDesc &Desc = MI->getDesc(); | |
637 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); | |
638 | unsigned i = 0; | |
639 | ||
640 | while (!MI->getOperand(i).isFI()) { | |
641 | ++i; | |
642 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); | |
643 | } | |
644 | ||
645 | // AddrMode4 and AddrMode6 cannot handle any offset. | |
646 | if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) | |
647 | return Offset == 0; | |
648 | ||
649 | unsigned NumBits = 0; | |
650 | unsigned Scale = 1; | |
651 | bool isSigned = true; | |
652 | switch (AddrMode) { | |
653 | case ARMII::AddrModeT2_i8: | |
654 | case ARMII::AddrModeT2_i12: | |
655 | // i8 supports only negative, and i12 supports only positive, so | |
656 | // based on Offset sign, consider the appropriate instruction | |
657 | Scale = 1; | |
658 | if (Offset < 0) { | |
659 | NumBits = 8; | |
660 | Offset = -Offset; | |
661 | } else { | |
662 | NumBits = 12; | |
663 | } | |
664 | break; | |
665 | case ARMII::AddrMode5: | |
666 | // VFP address mode. | |
667 | NumBits = 8; | |
668 | Scale = 4; | |
669 | break; | |
670 | case ARMII::AddrMode_i12: | |
671 | case ARMII::AddrMode2: | |
672 | NumBits = 12; | |
673 | break; | |
674 | case ARMII::AddrMode3: | |
675 | NumBits = 8; | |
676 | break; | |
677 | case ARMII::AddrModeT1_s: | |
678 | NumBits = 5; | |
679 | Scale = 4; | |
680 | isSigned = false; | |
681 | break; | |
682 | default: | |
683 | llvm_unreachable("Unsupported addressing mode!"); | |
684 | } | |
685 | ||
686 | Offset += getFrameIndexInstrOffset(MI, i); | |
687 | // Make sure the offset is encodable for instructions that scale the | |
688 | // immediate. | |
689 | if ((Offset & (Scale-1)) != 0) | |
690 | return false; | |
691 | ||
692 | if (isSigned && Offset < 0) | |
693 | Offset = -Offset; | |
694 | ||
695 | unsigned Mask = (1 << NumBits) - 1; | |
696 | if ((unsigned)Offset <= Mask * Scale) | |
697 | return true; | |
698 | ||
699 | return false; | |
700 | } | |
701 | ||
702 | void | |
703 | ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, | |
970d7e83 LB |
704 | int SPAdj, unsigned FIOperandNum, |
705 | RegScavenger *RS) const { | |
223e47cc LB |
706 | MachineInstr &MI = *II; |
707 | MachineBasicBlock &MBB = *MI.getParent(); | |
708 | MachineFunction &MF = *MBB.getParent(); | |
1a4d82fc JJ |
709 | const ARMBaseInstrInfo &TII = |
710 | *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); | |
711 | const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>( | |
712 | MF.getSubtarget().getFrameLowering()); | |
223e47cc LB |
713 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
714 | assert(!AFI->isThumb1OnlyFunction() && | |
715 | "This eliminateFrameIndex does not support Thumb1!"); | |
970d7e83 | 716 | int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); |
223e47cc LB |
717 | unsigned FrameReg; |
718 | ||
719 | int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); | |
720 | ||
721 | // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the | |
722 | // call frame setup/destroy instructions have already been eliminated. That | |
723 | // means the stack pointer cannot be used to access the emergency spill slot | |
724 | // when !hasReservedCallFrame(). | |
725 | #ifndef NDEBUG | |
1a4d82fc | 726 | if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ |
223e47cc LB |
727 | assert(TFI->hasReservedCallFrame(MF) && |
728 | "Cannot use SP to access the emergency spill slot in " | |
729 | "functions without a reserved call frame"); | |
730 | assert(!MF.getFrameInfo()->hasVarSizedObjects() && | |
731 | "Cannot use SP to access the emergency spill slot in " | |
732 | "functions with variable sized frame objects"); | |
733 | } | |
734 | #endif // NDEBUG | |
735 | ||
1a4d82fc | 736 | assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); |
223e47cc LB |
737 | |
738 | // Modify MI as necessary to handle as much of 'Offset' as possible | |
739 | bool Done = false; | |
740 | if (!AFI->isThumbFunction()) | |
970d7e83 | 741 | Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); |
223e47cc LB |
742 | else { |
743 | assert(AFI->isThumb2Function()); | |
970d7e83 | 744 | Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); |
223e47cc LB |
745 | } |
746 | if (Done) | |
747 | return; | |
748 | ||
749 | // If we get here, the immediate doesn't fit into the instruction. We folded | |
750 | // as much as possible above, handle the rest, providing a register that is | |
751 | // SP+LargeImm. | |
752 | assert((Offset || | |
753 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || | |
754 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && | |
755 | "This code isn't needed if offset already handled!"); | |
756 | ||
757 | unsigned ScratchReg = 0; | |
758 | int PIdx = MI.findFirstPredOperandIdx(); | |
759 | ARMCC::CondCodes Pred = (PIdx == -1) | |
760 | ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); | |
761 | unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); | |
762 | if (Offset == 0) | |
763 | // Must be addrmode4/6. | |
970d7e83 | 764 | MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); |
223e47cc LB |
765 | else { |
766 | ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); | |
767 | if (!AFI->isThumbFunction()) | |
768 | emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, | |
769 | Offset, Pred, PredReg, TII); | |
770 | else { | |
771 | assert(AFI->isThumb2Function()); | |
772 | emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, | |
773 | Offset, Pred, PredReg, TII); | |
774 | } | |
775 | // Update the original instruction to use the scratch register. | |
970d7e83 | 776 | MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); |
223e47cc LB |
777 | } |
778 | } | |
1a4d82fc JJ |
779 | |
780 | bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, | |
781 | const TargetRegisterClass *SrcRC, | |
782 | unsigned SubReg, | |
783 | const TargetRegisterClass *DstRC, | |
784 | unsigned DstSubReg, | |
785 | const TargetRegisterClass *NewRC) const { | |
786 | auto MBB = MI->getParent(); | |
787 | auto MF = MBB->getParent(); | |
788 | const MachineRegisterInfo &MRI = MF->getRegInfo(); | |
789 | // If not copying into a sub-register this should be ok because we shouldn't | |
790 | // need to split the reg. | |
791 | if (!DstSubReg) | |
792 | return true; | |
793 | // Small registers don't frequently cause a problem, so we can coalesce them. | |
794 | if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) | |
795 | return true; | |
796 | ||
797 | auto NewRCWeight = | |
798 | MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); | |
799 | auto SrcRCWeight = | |
800 | MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); | |
801 | auto DstRCWeight = | |
802 | MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); | |
803 | // If the source register class is more expensive than the destination, the | |
804 | // coalescing is probably profitable. | |
805 | if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) | |
806 | return true; | |
807 | if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) | |
808 | return true; | |
809 | ||
810 | // If the register allocator isn't constrained, we can always allow coalescing | |
811 | // unfortunately we don't know yet if we will be constrained. | |
812 | // The goal of this heuristic is to restrict how many expensive registers | |
813 | // we allow to coalesce in a given basic block. | |
814 | auto AFI = MF->getInfo<ARMFunctionInfo>(); | |
815 | auto It = AFI->getCoalescedWeight(MBB); | |
816 | ||
817 | DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " | |
818 | << It->second << "\n"); | |
819 | DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " | |
820 | << NewRCWeight.RegWeight << "\n"); | |
821 | ||
822 | // This number is the largest round number that which meets the criteria: | |
823 | // (1) addresses PR18825 | |
824 | // (2) generates better code in some test cases (like vldm-shed-a9.ll) | |
825 | // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) | |
826 | // In practice the SizeMultiplier will only factor in for straight line code | |
827 | // that uses a lot of NEON vectors, which isn't terribly common. | |
828 | unsigned SizeMultiplier = MBB->size()/100; | |
829 | SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; | |
830 | if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { | |
831 | It->second += NewRCWeight.RegWeight; | |
832 | return true; | |
833 | } | |
834 | return false; | |
835 | } |