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223e47cc LB |
1 | //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file defines the ARM-specific support for the FastISel class. Some | |
11 | // of the target-specific code is generated by tablegen in the file | |
12 | // ARMGenFastISel.inc, which is #included here. | |
13 | // | |
14 | //===----------------------------------------------------------------------===// | |
15 | ||
16 | #include "ARM.h" | |
1a4d82fc | 17 | #include "ARMBaseRegisterInfo.h" |
223e47cc | 18 | #include "ARMCallingConv.h" |
223e47cc | 19 | #include "ARMConstantPoolValue.h" |
1a4d82fc JJ |
20 | #include "ARMISelLowering.h" |
21 | #include "ARMMachineFunctionInfo.h" | |
970d7e83 | 22 | #include "ARMSubtarget.h" |
223e47cc | 23 | #include "MCTargetDesc/ARMAddressingModes.h" |
1a4d82fc | 24 | #include "llvm/ADT/STLExtras.h" |
223e47cc LB |
25 | #include "llvm/CodeGen/Analysis.h" |
26 | #include "llvm/CodeGen/FastISel.h" | |
27 | #include "llvm/CodeGen/FunctionLoweringInfo.h" | |
223e47cc LB |
28 | #include "llvm/CodeGen/MachineConstantPool.h" |
29 | #include "llvm/CodeGen/MachineFrameInfo.h" | |
970d7e83 | 30 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
223e47cc | 31 | #include "llvm/CodeGen/MachineMemOperand.h" |
970d7e83 | 32 | #include "llvm/CodeGen/MachineModuleInfo.h" |
223e47cc | 33 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
1a4d82fc | 34 | #include "llvm/IR/CallSite.h" |
970d7e83 LB |
35 | #include "llvm/IR/CallingConv.h" |
36 | #include "llvm/IR/DataLayout.h" | |
37 | #include "llvm/IR/DerivedTypes.h" | |
1a4d82fc | 38 | #include "llvm/IR/GetElementPtrTypeIterator.h" |
970d7e83 LB |
39 | #include "llvm/IR/GlobalVariable.h" |
40 | #include "llvm/IR/Instructions.h" | |
41 | #include "llvm/IR/IntrinsicInst.h" | |
42 | #include "llvm/IR/Module.h" | |
43 | #include "llvm/IR/Operator.h" | |
223e47cc LB |
44 | #include "llvm/Support/CommandLine.h" |
45 | #include "llvm/Support/ErrorHandling.h" | |
223e47cc LB |
46 | #include "llvm/Target/TargetInstrInfo.h" |
47 | #include "llvm/Target/TargetLowering.h" | |
48 | #include "llvm/Target/TargetMachine.h" | |
49 | #include "llvm/Target/TargetOptions.h" | |
50 | using namespace llvm; | |
51 | ||
52 | extern cl::opt<bool> EnableARMLongCalls; | |
53 | ||
54 | namespace { | |
55 | ||
56 | // All possible address modes, plus some. | |
57 | typedef struct Address { | |
58 | enum { | |
59 | RegBase, | |
60 | FrameIndexBase | |
61 | } BaseType; | |
62 | ||
63 | union { | |
64 | unsigned Reg; | |
65 | int FI; | |
66 | } Base; | |
67 | ||
68 | int Offset; | |
69 | ||
70 | // Innocuous defaults for our address. | |
71 | Address() | |
72 | : BaseType(RegBase), Offset(0) { | |
73 | Base.Reg = 0; | |
74 | } | |
75 | } Address; | |
76 | ||
1a4d82fc | 77 | class ARMFastISel final : public FastISel { |
223e47cc LB |
78 | |
79 | /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can | |
80 | /// make the right decision when generating code for different targets. | |
81 | const ARMSubtarget *Subtarget; | |
1a4d82fc | 82 | Module &M; |
223e47cc LB |
83 | const TargetMachine &TM; |
84 | const TargetInstrInfo &TII; | |
85 | const TargetLowering &TLI; | |
86 | ARMFunctionInfo *AFI; | |
87 | ||
88 | // Convenience variables to avoid some queries. | |
89 | bool isThumb2; | |
90 | LLVMContext *Context; | |
91 | ||
92 | public: | |
93 | explicit ARMFastISel(FunctionLoweringInfo &funcInfo, | |
970d7e83 | 94 | const TargetLibraryInfo *libInfo) |
1a4d82fc JJ |
95 | : FastISel(funcInfo, libInfo), |
96 | M(const_cast<Module &>(*funcInfo.Fn->getParent())), | |
97 | TM(funcInfo.MF->getTarget()), | |
98 | TII(*TM.getSubtargetImpl()->getInstrInfo()), | |
99 | TLI(*TM.getSubtargetImpl()->getTargetLowering()) { | |
223e47cc LB |
100 | Subtarget = &TM.getSubtarget<ARMSubtarget>(); |
101 | AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); | |
102 | isThumb2 = AFI->isThumbFunction(); | |
103 | Context = &funcInfo.Fn->getContext(); | |
104 | } | |
105 | ||
106 | // Code from FastISel.cpp. | |
107 | private: | |
1a4d82fc | 108 | unsigned fastEmitInst_r(unsigned MachineInstOpcode, |
223e47cc LB |
109 | const TargetRegisterClass *RC, |
110 | unsigned Op0, bool Op0IsKill); | |
1a4d82fc | 111 | unsigned fastEmitInst_rr(unsigned MachineInstOpcode, |
223e47cc LB |
112 | const TargetRegisterClass *RC, |
113 | unsigned Op0, bool Op0IsKill, | |
114 | unsigned Op1, bool Op1IsKill); | |
1a4d82fc | 115 | unsigned fastEmitInst_rrr(unsigned MachineInstOpcode, |
223e47cc LB |
116 | const TargetRegisterClass *RC, |
117 | unsigned Op0, bool Op0IsKill, | |
118 | unsigned Op1, bool Op1IsKill, | |
119 | unsigned Op2, bool Op2IsKill); | |
1a4d82fc | 120 | unsigned fastEmitInst_ri(unsigned MachineInstOpcode, |
223e47cc LB |
121 | const TargetRegisterClass *RC, |
122 | unsigned Op0, bool Op0IsKill, | |
123 | uint64_t Imm); | |
1a4d82fc | 124 | unsigned fastEmitInst_rri(unsigned MachineInstOpcode, |
223e47cc LB |
125 | const TargetRegisterClass *RC, |
126 | unsigned Op0, bool Op0IsKill, | |
127 | unsigned Op1, bool Op1IsKill, | |
128 | uint64_t Imm); | |
1a4d82fc | 129 | unsigned fastEmitInst_i(unsigned MachineInstOpcode, |
223e47cc LB |
130 | const TargetRegisterClass *RC, |
131 | uint64_t Imm); | |
223e47cc LB |
132 | |
133 | // Backend specific FastISel code. | |
134 | private: | |
1a4d82fc JJ |
135 | bool fastSelectInstruction(const Instruction *I) override; |
136 | unsigned fastMaterializeConstant(const Constant *C) override; | |
137 | unsigned fastMaterializeAlloca(const AllocaInst *AI) override; | |
138 | bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, | |
139 | const LoadInst *LI) override; | |
140 | bool fastLowerArguments() override; | |
223e47cc LB |
141 | private: |
142 | #include "ARMGenFastISel.inc" | |
143 | ||
144 | // Instruction selection routines. | |
145 | private: | |
146 | bool SelectLoad(const Instruction *I); | |
147 | bool SelectStore(const Instruction *I); | |
148 | bool SelectBranch(const Instruction *I); | |
149 | bool SelectIndirectBr(const Instruction *I); | |
150 | bool SelectCmp(const Instruction *I); | |
151 | bool SelectFPExt(const Instruction *I); | |
152 | bool SelectFPTrunc(const Instruction *I); | |
153 | bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode); | |
154 | bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode); | |
155 | bool SelectIToFP(const Instruction *I, bool isSigned); | |
156 | bool SelectFPToI(const Instruction *I, bool isSigned); | |
157 | bool SelectDiv(const Instruction *I, bool isSigned); | |
158 | bool SelectRem(const Instruction *I, bool isSigned); | |
159 | bool SelectCall(const Instruction *I, const char *IntrMemName); | |
160 | bool SelectIntrinsicCall(const IntrinsicInst &I); | |
161 | bool SelectSelect(const Instruction *I); | |
162 | bool SelectRet(const Instruction *I); | |
163 | bool SelectTrunc(const Instruction *I); | |
164 | bool SelectIntExt(const Instruction *I); | |
165 | bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); | |
166 | ||
167 | // Utility routines. | |
168 | private: | |
169 | bool isTypeLegal(Type *Ty, MVT &VT); | |
170 | bool isLoadTypeLegal(Type *Ty, MVT &VT); | |
171 | bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, | |
172 | bool isZExt); | |
970d7e83 | 173 | bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, |
223e47cc LB |
174 | unsigned Alignment = 0, bool isZExt = true, |
175 | bool allocReg = true); | |
970d7e83 | 176 | bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, |
223e47cc LB |
177 | unsigned Alignment = 0); |
178 | bool ARMComputeAddress(const Value *Obj, Address &Addr); | |
970d7e83 | 179 | void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3); |
223e47cc | 180 | bool ARMIsMemCpySmall(uint64_t Len); |
970d7e83 LB |
181 | bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len, |
182 | unsigned Alignment); | |
183 | unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); | |
184 | unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT); | |
185 | unsigned ARMMaterializeInt(const Constant *C, MVT VT); | |
186 | unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT); | |
187 | unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg); | |
188 | unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg); | |
223e47cc | 189 | unsigned ARMSelectCallOp(bool UseReg); |
970d7e83 | 190 | unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT); |
223e47cc | 191 | |
1a4d82fc JJ |
192 | const TargetLowering *getTargetLowering() { |
193 | return TM.getSubtargetImpl()->getTargetLowering(); | |
194 | } | |
195 | ||
223e47cc LB |
196 | // Call handling routines. |
197 | private: | |
198 | CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, | |
199 | bool Return, | |
200 | bool isVarArg); | |
201 | bool ProcessCallArgs(SmallVectorImpl<Value*> &Args, | |
202 | SmallVectorImpl<unsigned> &ArgRegs, | |
203 | SmallVectorImpl<MVT> &ArgVTs, | |
204 | SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, | |
205 | SmallVectorImpl<unsigned> &RegArgs, | |
206 | CallingConv::ID CC, | |
207 | unsigned &NumBytes, | |
208 | bool isVarArg); | |
209 | unsigned getLibcallReg(const Twine &Name); | |
210 | bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, | |
211 | const Instruction *I, CallingConv::ID CC, | |
212 | unsigned &NumBytes, bool isVarArg); | |
213 | bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); | |
214 | ||
215 | // OptionalDef handling routines. | |
216 | private: | |
217 | bool isARMNEONPred(const MachineInstr *MI); | |
218 | bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); | |
219 | const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); | |
970d7e83 | 220 | void AddLoadStoreOperands(MVT VT, Address &Addr, |
223e47cc LB |
221 | const MachineInstrBuilder &MIB, |
222 | unsigned Flags, bool useAM3); | |
223 | }; | |
224 | ||
225 | } // end anonymous namespace | |
226 | ||
227 | #include "ARMGenCallingConv.inc" | |
228 | ||
229 | // DefinesOptionalPredicate - This is different from DefinesPredicate in that | |
230 | // we don't care about implicit defs here, just places we'll need to add a | |
231 | // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. | |
232 | bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { | |
233 | if (!MI->hasOptionalDef()) | |
234 | return false; | |
235 | ||
236 | // Look to see if our OptionalDef is defining CPSR or CCR. | |
237 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { | |
238 | const MachineOperand &MO = MI->getOperand(i); | |
239 | if (!MO.isReg() || !MO.isDef()) continue; | |
240 | if (MO.getReg() == ARM::CPSR) | |
241 | *CPSR = true; | |
242 | } | |
243 | return true; | |
244 | } | |
245 | ||
246 | bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { | |
247 | const MCInstrDesc &MCID = MI->getDesc(); | |
248 | ||
1a4d82fc | 249 | // If we're a thumb2 or not NEON function we'll be handled via isPredicable. |
223e47cc LB |
250 | if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || |
251 | AFI->isThumb2Function()) | |
1a4d82fc | 252 | return MI->isPredicable(); |
223e47cc LB |
253 | |
254 | for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) | |
255 | if (MCID.OpInfo[i].isPredicate()) | |
256 | return true; | |
257 | ||
258 | return false; | |
259 | } | |
260 | ||
261 | // If the machine is predicable go ahead and add the predicate operands, if | |
262 | // it needs default CC operands add those. | |
263 | // TODO: If we want to support thumb1 then we'll need to deal with optional | |
264 | // CPSR defs that need to be added before the remaining operands. See s_cc_out | |
265 | // for descriptions why. | |
266 | const MachineInstrBuilder & | |
267 | ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { | |
268 | MachineInstr *MI = &*MIB; | |
269 | ||
270 | // Do we use a predicate? or... | |
271 | // Are we NEON in ARM mode and have a predicate operand? If so, I know | |
272 | // we're not predicable but add it anyways. | |
1a4d82fc | 273 | if (isARMNEONPred(MI)) |
223e47cc LB |
274 | AddDefaultPred(MIB); |
275 | ||
276 | // Do we optionally set a predicate? Preds is size > 0 iff the predicate | |
277 | // defines CPSR. All other OptionalDefines in ARM are the CCR register. | |
278 | bool CPSR = false; | |
279 | if (DefinesOptionalPredicate(MI, &CPSR)) { | |
280 | if (CPSR) | |
281 | AddDefaultT1CC(MIB); | |
282 | else | |
283 | AddDefaultCC(MIB); | |
284 | } | |
285 | return MIB; | |
286 | } | |
287 | ||
1a4d82fc | 288 | unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode, |
223e47cc LB |
289 | const TargetRegisterClass *RC, |
290 | unsigned Op0, bool Op0IsKill) { | |
291 | unsigned ResultReg = createResultReg(RC); | |
292 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
293 | ||
1a4d82fc JJ |
294 | // Make sure the input operand is sufficiently constrained to be legal |
295 | // for this instruction. | |
296 | Op0 = constrainOperandRegClass(II, Op0, 1); | |
223e47cc | 297 | if (II.getNumDefs() >= 1) { |
1a4d82fc JJ |
298 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, |
299 | ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); | |
223e47cc | 300 | } else { |
1a4d82fc | 301 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc | 302 | .addReg(Op0, Op0IsKill * RegState::Kill)); |
1a4d82fc | 303 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
304 | TII.get(TargetOpcode::COPY), ResultReg) |
305 | .addReg(II.ImplicitDefs[0])); | |
306 | } | |
307 | return ResultReg; | |
308 | } | |
309 | ||
1a4d82fc | 310 | unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, |
223e47cc LB |
311 | const TargetRegisterClass *RC, |
312 | unsigned Op0, bool Op0IsKill, | |
313 | unsigned Op1, bool Op1IsKill) { | |
314 | unsigned ResultReg = createResultReg(RC); | |
315 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
316 | ||
1a4d82fc JJ |
317 | // Make sure the input operands are sufficiently constrained to be legal |
318 | // for this instruction. | |
319 | Op0 = constrainOperandRegClass(II, Op0, 1); | |
320 | Op1 = constrainOperandRegClass(II, Op1, 2); | |
321 | ||
223e47cc | 322 | if (II.getNumDefs() >= 1) { |
1a4d82fc JJ |
323 | AddOptionalDefs( |
324 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) | |
325 | .addReg(Op0, Op0IsKill * RegState::Kill) | |
326 | .addReg(Op1, Op1IsKill * RegState::Kill)); | |
223e47cc | 327 | } else { |
1a4d82fc | 328 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc LB |
329 | .addReg(Op0, Op0IsKill * RegState::Kill) |
330 | .addReg(Op1, Op1IsKill * RegState::Kill)); | |
1a4d82fc | 331 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
332 | TII.get(TargetOpcode::COPY), ResultReg) |
333 | .addReg(II.ImplicitDefs[0])); | |
334 | } | |
335 | return ResultReg; | |
336 | } | |
337 | ||
1a4d82fc | 338 | unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode, |
223e47cc LB |
339 | const TargetRegisterClass *RC, |
340 | unsigned Op0, bool Op0IsKill, | |
341 | unsigned Op1, bool Op1IsKill, | |
342 | unsigned Op2, bool Op2IsKill) { | |
343 | unsigned ResultReg = createResultReg(RC); | |
344 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
345 | ||
1a4d82fc JJ |
346 | // Make sure the input operands are sufficiently constrained to be legal |
347 | // for this instruction. | |
348 | Op0 = constrainOperandRegClass(II, Op0, 1); | |
349 | Op1 = constrainOperandRegClass(II, Op1, 2); | |
350 | Op2 = constrainOperandRegClass(II, Op1, 3); | |
351 | ||
223e47cc | 352 | if (II.getNumDefs() >= 1) { |
1a4d82fc JJ |
353 | AddOptionalDefs( |
354 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) | |
355 | .addReg(Op0, Op0IsKill * RegState::Kill) | |
356 | .addReg(Op1, Op1IsKill * RegState::Kill) | |
357 | .addReg(Op2, Op2IsKill * RegState::Kill)); | |
223e47cc | 358 | } else { |
1a4d82fc | 359 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc LB |
360 | .addReg(Op0, Op0IsKill * RegState::Kill) |
361 | .addReg(Op1, Op1IsKill * RegState::Kill) | |
362 | .addReg(Op2, Op2IsKill * RegState::Kill)); | |
1a4d82fc | 363 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
364 | TII.get(TargetOpcode::COPY), ResultReg) |
365 | .addReg(II.ImplicitDefs[0])); | |
366 | } | |
367 | return ResultReg; | |
368 | } | |
369 | ||
1a4d82fc | 370 | unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, |
223e47cc LB |
371 | const TargetRegisterClass *RC, |
372 | unsigned Op0, bool Op0IsKill, | |
373 | uint64_t Imm) { | |
374 | unsigned ResultReg = createResultReg(RC); | |
375 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
376 | ||
1a4d82fc JJ |
377 | // Make sure the input operand is sufficiently constrained to be legal |
378 | // for this instruction. | |
379 | Op0 = constrainOperandRegClass(II, Op0, 1); | |
223e47cc | 380 | if (II.getNumDefs() >= 1) { |
1a4d82fc JJ |
381 | AddOptionalDefs( |
382 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) | |
383 | .addReg(Op0, Op0IsKill * RegState::Kill) | |
384 | .addImm(Imm)); | |
223e47cc | 385 | } else { |
1a4d82fc | 386 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc LB |
387 | .addReg(Op0, Op0IsKill * RegState::Kill) |
388 | .addImm(Imm)); | |
1a4d82fc | 389 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
390 | TII.get(TargetOpcode::COPY), ResultReg) |
391 | .addReg(II.ImplicitDefs[0])); | |
392 | } | |
393 | return ResultReg; | |
394 | } | |
395 | ||
1a4d82fc | 396 | unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode, |
223e47cc LB |
397 | const TargetRegisterClass *RC, |
398 | unsigned Op0, bool Op0IsKill, | |
399 | unsigned Op1, bool Op1IsKill, | |
400 | uint64_t Imm) { | |
401 | unsigned ResultReg = createResultReg(RC); | |
402 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
403 | ||
1a4d82fc JJ |
404 | // Make sure the input operands are sufficiently constrained to be legal |
405 | // for this instruction. | |
406 | Op0 = constrainOperandRegClass(II, Op0, 1); | |
407 | Op1 = constrainOperandRegClass(II, Op1, 2); | |
223e47cc | 408 | if (II.getNumDefs() >= 1) { |
1a4d82fc JJ |
409 | AddOptionalDefs( |
410 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) | |
411 | .addReg(Op0, Op0IsKill * RegState::Kill) | |
412 | .addReg(Op1, Op1IsKill * RegState::Kill) | |
413 | .addImm(Imm)); | |
223e47cc | 414 | } else { |
1a4d82fc | 415 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc LB |
416 | .addReg(Op0, Op0IsKill * RegState::Kill) |
417 | .addReg(Op1, Op1IsKill * RegState::Kill) | |
418 | .addImm(Imm)); | |
1a4d82fc | 419 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
420 | TII.get(TargetOpcode::COPY), ResultReg) |
421 | .addReg(II.ImplicitDefs[0])); | |
422 | } | |
423 | return ResultReg; | |
424 | } | |
425 | ||
1a4d82fc | 426 | unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode, |
223e47cc LB |
427 | const TargetRegisterClass *RC, |
428 | uint64_t Imm) { | |
429 | unsigned ResultReg = createResultReg(RC); | |
430 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | |
431 | ||
432 | if (II.getNumDefs() >= 1) { | |
1a4d82fc JJ |
433 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, |
434 | ResultReg).addImm(Imm)); | |
223e47cc | 435 | } else { |
1a4d82fc | 436 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc | 437 | .addImm(Imm)); |
1a4d82fc | 438 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
439 | TII.get(TargetOpcode::COPY), ResultReg) |
440 | .addReg(II.ImplicitDefs[0])); | |
441 | } | |
442 | return ResultReg; | |
443 | } | |
444 | ||
223e47cc LB |
445 | // TODO: Don't worry about 64-bit now, but when this is fixed remove the |
446 | // checks from the various callers. | |
970d7e83 | 447 | unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { |
223e47cc LB |
448 | if (VT == MVT::f64) return 0; |
449 | ||
450 | unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); | |
1a4d82fc | 451 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
452 | TII.get(ARM::VMOVSR), MoveReg) |
453 | .addReg(SrcReg)); | |
454 | return MoveReg; | |
455 | } | |
456 | ||
970d7e83 | 457 | unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { |
223e47cc LB |
458 | if (VT == MVT::i64) return 0; |
459 | ||
460 | unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); | |
1a4d82fc | 461 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
462 | TII.get(ARM::VMOVRS), MoveReg) |
463 | .addReg(SrcReg)); | |
464 | return MoveReg; | |
465 | } | |
466 | ||
467 | // For double width floating point we need to materialize two constants | |
468 | // (the high and the low) into integer registers then use a move to get | |
469 | // the combined constant into an FP reg. | |
970d7e83 | 470 | unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { |
223e47cc LB |
471 | const APFloat Val = CFP->getValueAPF(); |
472 | bool is64bit = VT == MVT::f64; | |
473 | ||
474 | // This checks to see if we can use VFP3 instructions to materialize | |
475 | // a constant, otherwise we have to go through the constant pool. | |
476 | if (TLI.isFPImmLegal(Val, VT)) { | |
477 | int Imm; | |
478 | unsigned Opc; | |
479 | if (is64bit) { | |
480 | Imm = ARM_AM::getFP64Imm(Val); | |
481 | Opc = ARM::FCONSTD; | |
482 | } else { | |
483 | Imm = ARM_AM::getFP32Imm(Val); | |
484 | Opc = ARM::FCONSTS; | |
485 | } | |
486 | unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); | |
1a4d82fc JJ |
487 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
488 | TII.get(Opc), DestReg).addImm(Imm)); | |
223e47cc LB |
489 | return DestReg; |
490 | } | |
491 | ||
492 | // Require VFP2 for loading fp constants. | |
493 | if (!Subtarget->hasVFP2()) return false; | |
494 | ||
495 | // MachineConstantPool wants an explicit alignment. | |
1a4d82fc | 496 | unsigned Align = DL.getPrefTypeAlignment(CFP->getType()); |
223e47cc LB |
497 | if (Align == 0) { |
498 | // TODO: Figure out if this is correct. | |
1a4d82fc | 499 | Align = DL.getTypeAllocSize(CFP->getType()); |
223e47cc LB |
500 | } |
501 | unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); | |
502 | unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); | |
503 | unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; | |
504 | ||
505 | // The extra reg is for addrmode5. | |
1a4d82fc JJ |
506 | AddOptionalDefs( |
507 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) | |
508 | .addConstantPoolIndex(Idx) | |
509 | .addReg(0)); | |
223e47cc LB |
510 | return DestReg; |
511 | } | |
512 | ||
970d7e83 | 513 | unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { |
223e47cc LB |
514 | |
515 | if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) | |
1a4d82fc | 516 | return 0; |
223e47cc LB |
517 | |
518 | // If we can do this in a single instruction without a constant pool entry | |
519 | // do so now. | |
520 | const ConstantInt *CI = cast<ConstantInt>(C); | |
521 | if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { | |
522 | unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; | |
970d7e83 LB |
523 | const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : |
524 | &ARM::GPRRegClass; | |
525 | unsigned ImmReg = createResultReg(RC); | |
1a4d82fc | 526 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
527 | TII.get(Opc), ImmReg) |
528 | .addImm(CI->getZExtValue())); | |
529 | return ImmReg; | |
530 | } | |
531 | ||
532 | // Use MVN to emit negative constants. | |
533 | if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { | |
534 | unsigned Imm = (unsigned)~(CI->getSExtValue()); | |
535 | bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : | |
536 | (ARM_AM::getSOImmVal(Imm) != -1); | |
537 | if (UseImm) { | |
538 | unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; | |
1a4d82fc JJ |
539 | const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : |
540 | &ARM::GPRRegClass; | |
541 | unsigned ImmReg = createResultReg(RC); | |
542 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
543 | TII.get(Opc), ImmReg) |
544 | .addImm(Imm)); | |
545 | return ImmReg; | |
546 | } | |
547 | } | |
548 | ||
1a4d82fc JJ |
549 | unsigned ResultReg = 0; |
550 | if (Subtarget->useMovt(*FuncInfo.MF)) | |
551 | ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); | |
552 | ||
553 | if (ResultReg) | |
554 | return ResultReg; | |
555 | ||
223e47cc LB |
556 | // Load from constant pool. For now 32-bit only. |
557 | if (VT != MVT::i32) | |
1a4d82fc | 558 | return 0; |
223e47cc LB |
559 | |
560 | // MachineConstantPool wants an explicit alignment. | |
1a4d82fc | 561 | unsigned Align = DL.getPrefTypeAlignment(C->getType()); |
223e47cc LB |
562 | if (Align == 0) { |
563 | // TODO: Figure out if this is correct. | |
1a4d82fc | 564 | Align = DL.getTypeAllocSize(C->getType()); |
223e47cc LB |
565 | } |
566 | unsigned Idx = MCP.getConstantPoolIndex(C, Align); | |
1a4d82fc | 567 | ResultReg = createResultReg(TLI.getRegClassFor(VT)); |
223e47cc | 568 | if (isThumb2) |
1a4d82fc JJ |
569 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
570 | TII.get(ARM::t2LDRpci), ResultReg) | |
571 | .addConstantPoolIndex(Idx)); | |
572 | else { | |
223e47cc | 573 | // The extra immediate is for addrmode2. |
1a4d82fc JJ |
574 | ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); |
575 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
576 | TII.get(ARM::LDRcp), ResultReg) | |
577 | .addConstantPoolIndex(Idx) | |
578 | .addImm(0)); | |
579 | } | |
580 | return ResultReg; | |
223e47cc LB |
581 | } |
582 | ||
970d7e83 | 583 | unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { |
223e47cc LB |
584 | // For now 32-bit only. |
585 | if (VT != MVT::i32) return 0; | |
586 | ||
587 | Reloc::Model RelocM = TM.getRelocationModel(); | |
588 | bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); | |
85aaf69f SL |
589 | const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass |
590 | : &ARM::GPRRegClass; | |
970d7e83 | 591 | unsigned DestReg = createResultReg(RC); |
223e47cc | 592 | |
1a4d82fc JJ |
593 | // FastISel TLS support on non-MachO is broken, punt to SelectionDAG. |
594 | const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); | |
595 | bool IsThreadLocal = GVar && GVar->isThreadLocal(); | |
596 | if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0; | |
597 | ||
223e47cc | 598 | // Use movw+movt when possible, it avoids constant pool entries. |
1a4d82fc JJ |
599 | // Non-darwin targets only support static movt relocations in FastISel. |
600 | if (Subtarget->useMovt(*FuncInfo.MF) && | |
601 | (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) { | |
223e47cc | 602 | unsigned Opc; |
1a4d82fc JJ |
603 | unsigned char TF = 0; |
604 | if (Subtarget->isTargetMachO()) | |
605 | TF = ARMII::MO_NONLAZY; | |
606 | ||
223e47cc LB |
607 | switch (RelocM) { |
608 | case Reloc::PIC_: | |
609 | Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; | |
610 | break; | |
223e47cc LB |
611 | default: |
612 | Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; | |
613 | break; | |
614 | } | |
1a4d82fc JJ |
615 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
616 | TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF)); | |
223e47cc LB |
617 | } else { |
618 | // MachineConstantPool wants an explicit alignment. | |
1a4d82fc | 619 | unsigned Align = DL.getPrefTypeAlignment(GV->getType()); |
223e47cc LB |
620 | if (Align == 0) { |
621 | // TODO: Figure out if this is correct. | |
1a4d82fc | 622 | Align = DL.getTypeAllocSize(GV->getType()); |
223e47cc LB |
623 | } |
624 | ||
625 | if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_) | |
626 | return ARMLowerPICELF(GV, Align, VT); | |
627 | ||
628 | // Grab index. | |
629 | unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : | |
630 | (Subtarget->isThumb() ? 4 : 8); | |
631 | unsigned Id = AFI->createPICLabelUId(); | |
632 | ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id, | |
633 | ARMCP::CPValue, | |
634 | PCAdj); | |
635 | unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); | |
636 | ||
637 | // Load value. | |
638 | MachineInstrBuilder MIB; | |
639 | if (isThumb2) { | |
640 | unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; | |
1a4d82fc JJ |
641 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), |
642 | DestReg).addConstantPoolIndex(Idx); | |
223e47cc LB |
643 | if (RelocM == Reloc::PIC_) |
644 | MIB.addImm(Id); | |
645 | AddOptionalDefs(MIB); | |
646 | } else { | |
647 | // The extra immediate is for addrmode2. | |
1a4d82fc JJ |
648 | DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); |
649 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
650 | TII.get(ARM::LDRcp), DestReg) | |
651 | .addConstantPoolIndex(Idx) | |
652 | .addImm(0); | |
223e47cc LB |
653 | AddOptionalDefs(MIB); |
654 | ||
655 | if (RelocM == Reloc::PIC_) { | |
656 | unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; | |
657 | unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); | |
658 | ||
659 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, | |
1a4d82fc | 660 | DbgLoc, TII.get(Opc), NewDestReg) |
223e47cc LB |
661 | .addReg(DestReg) |
662 | .addImm(Id); | |
663 | AddOptionalDefs(MIB); | |
664 | return NewDestReg; | |
665 | } | |
666 | } | |
667 | } | |
668 | ||
669 | if (IsIndirect) { | |
670 | MachineInstrBuilder MIB; | |
671 | unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); | |
672 | if (isThumb2) | |
1a4d82fc | 673 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
674 | TII.get(ARM::t2LDRi12), NewDestReg) |
675 | .addReg(DestReg) | |
676 | .addImm(0); | |
677 | else | |
1a4d82fc JJ |
678 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
679 | TII.get(ARM::LDRi12), NewDestReg) | |
680 | .addReg(DestReg) | |
681 | .addImm(0); | |
223e47cc LB |
682 | DestReg = NewDestReg; |
683 | AddOptionalDefs(MIB); | |
684 | } | |
685 | ||
686 | return DestReg; | |
687 | } | |
688 | ||
1a4d82fc | 689 | unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) { |
970d7e83 | 690 | EVT CEVT = TLI.getValueType(C->getType(), true); |
223e47cc LB |
691 | |
692 | // Only handle simple types. | |
970d7e83 LB |
693 | if (!CEVT.isSimple()) return 0; |
694 | MVT VT = CEVT.getSimpleVT(); | |
223e47cc LB |
695 | |
696 | if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) | |
697 | return ARMMaterializeFP(CFP, VT); | |
698 | else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) | |
699 | return ARMMaterializeGV(GV, VT); | |
700 | else if (isa<ConstantInt>(C)) | |
701 | return ARMMaterializeInt(C, VT); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF); | |
707 | ||
1a4d82fc | 708 | unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) { |
223e47cc LB |
709 | // Don't handle dynamic allocas. |
710 | if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; | |
711 | ||
712 | MVT VT; | |
713 | if (!isLoadTypeLegal(AI->getType(), VT)) return 0; | |
714 | ||
715 | DenseMap<const AllocaInst*, int>::iterator SI = | |
716 | FuncInfo.StaticAllocaMap.find(AI); | |
717 | ||
718 | // This will get lowered later into the correct offsets and registers | |
719 | // via rewriteXFrameIndex. | |
720 | if (SI != FuncInfo.StaticAllocaMap.end()) { | |
1a4d82fc | 721 | unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; |
223e47cc LB |
722 | const TargetRegisterClass* RC = TLI.getRegClassFor(VT); |
723 | unsigned ResultReg = createResultReg(RC); | |
1a4d82fc JJ |
724 | ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); |
725 | ||
726 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
727 | TII.get(Opc), ResultReg) |
728 | .addFrameIndex(SI->second) | |
729 | .addImm(0)); | |
730 | return ResultReg; | |
731 | } | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
736 | bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { | |
737 | EVT evt = TLI.getValueType(Ty, true); | |
738 | ||
739 | // Only handle simple types. | |
740 | if (evt == MVT::Other || !evt.isSimple()) return false; | |
741 | VT = evt.getSimpleVT(); | |
742 | ||
743 | // Handle all legal types, i.e. a register that will directly hold this | |
744 | // value. | |
745 | return TLI.isTypeLegal(VT); | |
746 | } | |
747 | ||
748 | bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { | |
749 | if (isTypeLegal(Ty, VT)) return true; | |
750 | ||
751 | // If this is a type than can be sign or zero-extended to a basic operation | |
752 | // go ahead and accept it now. | |
753 | if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) | |
754 | return true; | |
755 | ||
756 | return false; | |
757 | } | |
758 | ||
759 | // Computes the address to get to an object. | |
760 | bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) { | |
761 | // Some boilerplate from the X86 FastISel. | |
1a4d82fc | 762 | const User *U = nullptr; |
223e47cc LB |
763 | unsigned Opcode = Instruction::UserOp1; |
764 | if (const Instruction *I = dyn_cast<Instruction>(Obj)) { | |
765 | // Don't walk into other basic blocks unless the object is an alloca from | |
766 | // another block, otherwise it may not have a virtual register assigned. | |
767 | if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || | |
768 | FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { | |
769 | Opcode = I->getOpcode(); | |
770 | U = I; | |
771 | } | |
772 | } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { | |
773 | Opcode = C->getOpcode(); | |
774 | U = C; | |
775 | } | |
776 | ||
777 | if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) | |
778 | if (Ty->getAddressSpace() > 255) | |
779 | // Fast instruction selection doesn't support the special | |
780 | // address spaces. | |
781 | return false; | |
782 | ||
783 | switch (Opcode) { | |
784 | default: | |
785 | break; | |
1a4d82fc | 786 | case Instruction::BitCast: |
223e47cc LB |
787 | // Look through bitcasts. |
788 | return ARMComputeAddress(U->getOperand(0), Addr); | |
1a4d82fc | 789 | case Instruction::IntToPtr: |
223e47cc LB |
790 | // Look past no-op inttoptrs. |
791 | if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) | |
792 | return ARMComputeAddress(U->getOperand(0), Addr); | |
793 | break; | |
1a4d82fc | 794 | case Instruction::PtrToInt: |
223e47cc LB |
795 | // Look past no-op ptrtoints. |
796 | if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) | |
797 | return ARMComputeAddress(U->getOperand(0), Addr); | |
798 | break; | |
223e47cc LB |
799 | case Instruction::GetElementPtr: { |
800 | Address SavedAddr = Addr; | |
801 | int TmpOffset = Addr.Offset; | |
802 | ||
803 | // Iterate through the GEP folding the constants into offsets where | |
804 | // we can. | |
805 | gep_type_iterator GTI = gep_type_begin(U); | |
806 | for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); | |
807 | i != e; ++i, ++GTI) { | |
808 | const Value *Op = *i; | |
809 | if (StructType *STy = dyn_cast<StructType>(*GTI)) { | |
1a4d82fc | 810 | const StructLayout *SL = DL.getStructLayout(STy); |
223e47cc LB |
811 | unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); |
812 | TmpOffset += SL->getElementOffset(Idx); | |
813 | } else { | |
1a4d82fc | 814 | uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType()); |
223e47cc LB |
815 | for (;;) { |
816 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { | |
817 | // Constant-offset addressing. | |
818 | TmpOffset += CI->getSExtValue() * S; | |
819 | break; | |
820 | } | |
1a4d82fc JJ |
821 | if (canFoldAddIntoGEP(U, Op)) { |
822 | // A compatible add with a constant operand. Fold the constant. | |
223e47cc LB |
823 | ConstantInt *CI = |
824 | cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); | |
825 | TmpOffset += CI->getSExtValue() * S; | |
826 | // Iterate on the other operand. | |
827 | Op = cast<AddOperator>(Op)->getOperand(0); | |
828 | continue; | |
829 | } | |
830 | // Unsupported | |
831 | goto unsupported_gep; | |
832 | } | |
833 | } | |
834 | } | |
835 | ||
836 | // Try to grab the base operand now. | |
837 | Addr.Offset = TmpOffset; | |
838 | if (ARMComputeAddress(U->getOperand(0), Addr)) return true; | |
839 | ||
840 | // We failed, restore everything and try the other options. | |
841 | Addr = SavedAddr; | |
842 | ||
843 | unsupported_gep: | |
844 | break; | |
845 | } | |
846 | case Instruction::Alloca: { | |
847 | const AllocaInst *AI = cast<AllocaInst>(Obj); | |
848 | DenseMap<const AllocaInst*, int>::iterator SI = | |
849 | FuncInfo.StaticAllocaMap.find(AI); | |
850 | if (SI != FuncInfo.StaticAllocaMap.end()) { | |
851 | Addr.BaseType = Address::FrameIndexBase; | |
852 | Addr.Base.FI = SI->second; | |
853 | return true; | |
854 | } | |
855 | break; | |
856 | } | |
857 | } | |
858 | ||
859 | // Try to get this in a register if nothing else has worked. | |
860 | if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj); | |
861 | return Addr.Base.Reg != 0; | |
862 | } | |
863 | ||
970d7e83 | 864 | void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { |
223e47cc | 865 | bool needsLowering = false; |
970d7e83 | 866 | switch (VT.SimpleTy) { |
223e47cc LB |
867 | default: llvm_unreachable("Unhandled load/store type!"); |
868 | case MVT::i1: | |
869 | case MVT::i8: | |
870 | case MVT::i16: | |
871 | case MVT::i32: | |
872 | if (!useAM3) { | |
873 | // Integer loads/stores handle 12-bit offsets. | |
874 | needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); | |
875 | // Handle negative offsets. | |
876 | if (needsLowering && isThumb2) | |
877 | needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 && | |
878 | Addr.Offset > -256); | |
879 | } else { | |
880 | // ARM halfword load/stores and signed byte loads use +/-imm8 offsets. | |
881 | needsLowering = (Addr.Offset > 255 || Addr.Offset < -255); | |
882 | } | |
883 | break; | |
884 | case MVT::f32: | |
885 | case MVT::f64: | |
886 | // Floating point operands handle 8-bit offsets. | |
887 | needsLowering = ((Addr.Offset & 0xff) != Addr.Offset); | |
888 | break; | |
889 | } | |
890 | ||
891 | // If this is a stack pointer and the offset needs to be simplified then | |
892 | // put the alloca address into a register, set the base type back to | |
893 | // register and continue. This should almost never happen. | |
894 | if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { | |
85aaf69f SL |
895 | const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass |
896 | : &ARM::GPRRegClass; | |
223e47cc LB |
897 | unsigned ResultReg = createResultReg(RC); |
898 | unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; | |
1a4d82fc | 899 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
900 | TII.get(Opc), ResultReg) |
901 | .addFrameIndex(Addr.Base.FI) | |
902 | .addImm(0)); | |
903 | Addr.Base.Reg = ResultReg; | |
904 | Addr.BaseType = Address::RegBase; | |
905 | } | |
906 | ||
907 | // Since the offset is too large for the load/store instruction | |
908 | // get the reg+offset into a register. | |
909 | if (needsLowering) { | |
1a4d82fc | 910 | Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, |
223e47cc LB |
911 | /*Op0IsKill*/false, Addr.Offset, MVT::i32); |
912 | Addr.Offset = 0; | |
913 | } | |
914 | } | |
915 | ||
970d7e83 | 916 | void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, |
223e47cc LB |
917 | const MachineInstrBuilder &MIB, |
918 | unsigned Flags, bool useAM3) { | |
919 | // addrmode5 output depends on the selection dag addressing dividing the | |
920 | // offset by 4 that it then later multiplies. Do this here as well. | |
970d7e83 | 921 | if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) |
223e47cc LB |
922 | Addr.Offset /= 4; |
923 | ||
924 | // Frame base works a bit differently. Handle it separately. | |
925 | if (Addr.BaseType == Address::FrameIndexBase) { | |
926 | int FI = Addr.Base.FI; | |
927 | int Offset = Addr.Offset; | |
928 | MachineMemOperand *MMO = | |
929 | FuncInfo.MF->getMachineMemOperand( | |
930 | MachinePointerInfo::getFixedStack(FI, Offset), | |
931 | Flags, | |
932 | MFI.getObjectSize(FI), | |
933 | MFI.getObjectAlignment(FI)); | |
934 | // Now add the rest of the operands. | |
935 | MIB.addFrameIndex(FI); | |
936 | ||
937 | // ARM halfword load/stores and signed byte loads need an additional | |
938 | // operand. | |
939 | if (useAM3) { | |
940 | signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; | |
941 | MIB.addReg(0); | |
942 | MIB.addImm(Imm); | |
943 | } else { | |
944 | MIB.addImm(Addr.Offset); | |
945 | } | |
946 | MIB.addMemOperand(MMO); | |
947 | } else { | |
948 | // Now add the rest of the operands. | |
949 | MIB.addReg(Addr.Base.Reg); | |
950 | ||
951 | // ARM halfword load/stores and signed byte loads need an additional | |
952 | // operand. | |
953 | if (useAM3) { | |
954 | signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; | |
955 | MIB.addReg(0); | |
956 | MIB.addImm(Imm); | |
957 | } else { | |
958 | MIB.addImm(Addr.Offset); | |
959 | } | |
960 | } | |
961 | AddOptionalDefs(MIB); | |
962 | } | |
963 | ||
970d7e83 | 964 | bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, |
223e47cc | 965 | unsigned Alignment, bool isZExt, bool allocReg) { |
223e47cc LB |
966 | unsigned Opc; |
967 | bool useAM3 = false; | |
968 | bool needVMOV = false; | |
969 | const TargetRegisterClass *RC; | |
970d7e83 | 970 | switch (VT.SimpleTy) { |
223e47cc LB |
971 | // This is mostly going to be Neon/vector support. |
972 | default: return false; | |
973 | case MVT::i1: | |
974 | case MVT::i8: | |
975 | if (isThumb2) { | |
976 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
977 | Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; | |
978 | else | |
979 | Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; | |
980 | } else { | |
981 | if (isZExt) { | |
982 | Opc = ARM::LDRBi12; | |
983 | } else { | |
984 | Opc = ARM::LDRSB; | |
985 | useAM3 = true; | |
986 | } | |
987 | } | |
1a4d82fc | 988 | RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; |
223e47cc LB |
989 | break; |
990 | case MVT::i16: | |
991 | if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) | |
992 | return false; | |
993 | ||
994 | if (isThumb2) { | |
995 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
996 | Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; | |
997 | else | |
998 | Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; | |
999 | } else { | |
1000 | Opc = isZExt ? ARM::LDRH : ARM::LDRSH; | |
1001 | useAM3 = true; | |
1002 | } | |
1a4d82fc | 1003 | RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; |
223e47cc LB |
1004 | break; |
1005 | case MVT::i32: | |
1006 | if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) | |
1007 | return false; | |
1008 | ||
1009 | if (isThumb2) { | |
1010 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
1011 | Opc = ARM::t2LDRi8; | |
1012 | else | |
1013 | Opc = ARM::t2LDRi12; | |
1014 | } else { | |
1015 | Opc = ARM::LDRi12; | |
1016 | } | |
1a4d82fc | 1017 | RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; |
223e47cc LB |
1018 | break; |
1019 | case MVT::f32: | |
1020 | if (!Subtarget->hasVFP2()) return false; | |
1021 | // Unaligned loads need special handling. Floats require word-alignment. | |
1022 | if (Alignment && Alignment < 4) { | |
1023 | needVMOV = true; | |
1024 | VT = MVT::i32; | |
1025 | Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; | |
1a4d82fc | 1026 | RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; |
223e47cc LB |
1027 | } else { |
1028 | Opc = ARM::VLDRS; | |
1029 | RC = TLI.getRegClassFor(VT); | |
1030 | } | |
1031 | break; | |
1032 | case MVT::f64: | |
1033 | if (!Subtarget->hasVFP2()) return false; | |
1034 | // FIXME: Unaligned loads need special handling. Doublewords require | |
1035 | // word-alignment. | |
1036 | if (Alignment && Alignment < 4) | |
1037 | return false; | |
1038 | ||
1039 | Opc = ARM::VLDRD; | |
1040 | RC = TLI.getRegClassFor(VT); | |
1041 | break; | |
1042 | } | |
1043 | // Simplify this down to something we can handle. | |
1044 | ARMSimplifyAddress(Addr, VT, useAM3); | |
1045 | ||
1046 | // Create the base instruction, then add the operands. | |
1047 | if (allocReg) | |
1048 | ResultReg = createResultReg(RC); | |
1049 | assert (ResultReg > 255 && "Expected an allocated virtual register."); | |
1a4d82fc | 1050 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1051 | TII.get(Opc), ResultReg); |
1052 | AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3); | |
1053 | ||
1054 | // If we had an unaligned load of a float we've converted it to an regular | |
1055 | // load. Now we must move from the GRP to the FP register. | |
1056 | if (needVMOV) { | |
1057 | unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32)); | |
1a4d82fc | 1058 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1059 | TII.get(ARM::VMOVSR), MoveReg) |
1060 | .addReg(ResultReg)); | |
1061 | ResultReg = MoveReg; | |
1062 | } | |
1063 | return true; | |
1064 | } | |
1065 | ||
1066 | bool ARMFastISel::SelectLoad(const Instruction *I) { | |
1067 | // Atomic loads need special handling. | |
1068 | if (cast<LoadInst>(I)->isAtomic()) | |
1069 | return false; | |
1070 | ||
1071 | // Verify we have a legal type before going any further. | |
1072 | MVT VT; | |
1073 | if (!isLoadTypeLegal(I->getType(), VT)) | |
1074 | return false; | |
1075 | ||
1076 | // See if we can handle this address. | |
1077 | Address Addr; | |
1078 | if (!ARMComputeAddress(I->getOperand(0), Addr)) return false; | |
1079 | ||
1080 | unsigned ResultReg; | |
1081 | if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) | |
1082 | return false; | |
1a4d82fc | 1083 | updateValueMap(I, ResultReg); |
223e47cc LB |
1084 | return true; |
1085 | } | |
1086 | ||
970d7e83 | 1087 | bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, |
223e47cc LB |
1088 | unsigned Alignment) { |
1089 | unsigned StrOpc; | |
1090 | bool useAM3 = false; | |
970d7e83 | 1091 | switch (VT.SimpleTy) { |
223e47cc LB |
1092 | // This is mostly going to be Neon/vector support. |
1093 | default: return false; | |
1094 | case MVT::i1: { | |
85aaf69f SL |
1095 | unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass |
1096 | : &ARM::GPRRegClass); | |
223e47cc | 1097 | unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; |
1a4d82fc JJ |
1098 | SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); |
1099 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
1100 | TII.get(Opc), Res) |
1101 | .addReg(SrcReg).addImm(1)); | |
1102 | SrcReg = Res; | |
1103 | } // Fallthrough here. | |
1104 | case MVT::i8: | |
1105 | if (isThumb2) { | |
1106 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
1107 | StrOpc = ARM::t2STRBi8; | |
1108 | else | |
1109 | StrOpc = ARM::t2STRBi12; | |
1110 | } else { | |
1111 | StrOpc = ARM::STRBi12; | |
1112 | } | |
1113 | break; | |
1114 | case MVT::i16: | |
1115 | if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) | |
1116 | return false; | |
1117 | ||
1118 | if (isThumb2) { | |
1119 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
1120 | StrOpc = ARM::t2STRHi8; | |
1121 | else | |
1122 | StrOpc = ARM::t2STRHi12; | |
1123 | } else { | |
1124 | StrOpc = ARM::STRH; | |
1125 | useAM3 = true; | |
1126 | } | |
1127 | break; | |
1128 | case MVT::i32: | |
1129 | if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) | |
1130 | return false; | |
1131 | ||
1132 | if (isThumb2) { | |
1133 | if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) | |
1134 | StrOpc = ARM::t2STRi8; | |
1135 | else | |
1136 | StrOpc = ARM::t2STRi12; | |
1137 | } else { | |
1138 | StrOpc = ARM::STRi12; | |
1139 | } | |
1140 | break; | |
1141 | case MVT::f32: | |
1142 | if (!Subtarget->hasVFP2()) return false; | |
1143 | // Unaligned stores need special handling. Floats require word-alignment. | |
1144 | if (Alignment && Alignment < 4) { | |
1145 | unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); | |
1a4d82fc | 1146 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1147 | TII.get(ARM::VMOVRS), MoveReg) |
1148 | .addReg(SrcReg)); | |
1149 | SrcReg = MoveReg; | |
1150 | VT = MVT::i32; | |
1151 | StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; | |
1152 | } else { | |
1153 | StrOpc = ARM::VSTRS; | |
1154 | } | |
1155 | break; | |
1156 | case MVT::f64: | |
1157 | if (!Subtarget->hasVFP2()) return false; | |
1158 | // FIXME: Unaligned stores need special handling. Doublewords require | |
1159 | // word-alignment. | |
1160 | if (Alignment && Alignment < 4) | |
1161 | return false; | |
1162 | ||
1163 | StrOpc = ARM::VSTRD; | |
1164 | break; | |
1165 | } | |
1166 | // Simplify this down to something we can handle. | |
1167 | ARMSimplifyAddress(Addr, VT, useAM3); | |
1168 | ||
1169 | // Create the base instruction, then add the operands. | |
1a4d82fc JJ |
1170 | SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); |
1171 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
1172 | TII.get(StrOpc)) |
1173 | .addReg(SrcReg); | |
1174 | AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3); | |
1175 | return true; | |
1176 | } | |
1177 | ||
1178 | bool ARMFastISel::SelectStore(const Instruction *I) { | |
1179 | Value *Op0 = I->getOperand(0); | |
1180 | unsigned SrcReg = 0; | |
1181 | ||
1182 | // Atomic stores need special handling. | |
1183 | if (cast<StoreInst>(I)->isAtomic()) | |
1184 | return false; | |
1185 | ||
1186 | // Verify we have a legal type before going any further. | |
1187 | MVT VT; | |
1188 | if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) | |
1189 | return false; | |
1190 | ||
1191 | // Get the value to be stored into a register. | |
1192 | SrcReg = getRegForValue(Op0); | |
1193 | if (SrcReg == 0) return false; | |
1194 | ||
1195 | // See if we can handle this address. | |
1196 | Address Addr; | |
1197 | if (!ARMComputeAddress(I->getOperand(1), Addr)) | |
1198 | return false; | |
1199 | ||
1200 | if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) | |
1201 | return false; | |
1202 | return true; | |
1203 | } | |
1204 | ||
1205 | static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { | |
1206 | switch (Pred) { | |
1207 | // Needs two compares... | |
1208 | case CmpInst::FCMP_ONE: | |
1209 | case CmpInst::FCMP_UEQ: | |
1210 | default: | |
1211 | // AL is our "false" for now. The other two need more compares. | |
1212 | return ARMCC::AL; | |
1213 | case CmpInst::ICMP_EQ: | |
1214 | case CmpInst::FCMP_OEQ: | |
1215 | return ARMCC::EQ; | |
1216 | case CmpInst::ICMP_SGT: | |
1217 | case CmpInst::FCMP_OGT: | |
1218 | return ARMCC::GT; | |
1219 | case CmpInst::ICMP_SGE: | |
1220 | case CmpInst::FCMP_OGE: | |
1221 | return ARMCC::GE; | |
1222 | case CmpInst::ICMP_UGT: | |
1223 | case CmpInst::FCMP_UGT: | |
1224 | return ARMCC::HI; | |
1225 | case CmpInst::FCMP_OLT: | |
1226 | return ARMCC::MI; | |
1227 | case CmpInst::ICMP_ULE: | |
1228 | case CmpInst::FCMP_OLE: | |
1229 | return ARMCC::LS; | |
1230 | case CmpInst::FCMP_ORD: | |
1231 | return ARMCC::VC; | |
1232 | case CmpInst::FCMP_UNO: | |
1233 | return ARMCC::VS; | |
1234 | case CmpInst::FCMP_UGE: | |
1235 | return ARMCC::PL; | |
1236 | case CmpInst::ICMP_SLT: | |
1237 | case CmpInst::FCMP_ULT: | |
1238 | return ARMCC::LT; | |
1239 | case CmpInst::ICMP_SLE: | |
1240 | case CmpInst::FCMP_ULE: | |
1241 | return ARMCC::LE; | |
1242 | case CmpInst::FCMP_UNE: | |
1243 | case CmpInst::ICMP_NE: | |
1244 | return ARMCC::NE; | |
1245 | case CmpInst::ICMP_UGE: | |
1246 | return ARMCC::HS; | |
1247 | case CmpInst::ICMP_ULT: | |
1248 | return ARMCC::LO; | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | bool ARMFastISel::SelectBranch(const Instruction *I) { | |
1253 | const BranchInst *BI = cast<BranchInst>(I); | |
1254 | MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; | |
1255 | MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; | |
1256 | ||
1257 | // Simple branch support. | |
1258 | ||
1259 | // If we can, avoid recomputing the compare - redoing it could lead to wonky | |
1260 | // behavior. | |
1261 | if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { | |
1262 | if (CI->hasOneUse() && (CI->getParent() == I->getParent())) { | |
1263 | ||
1264 | // Get the compare predicate. | |
1265 | // Try to take advantage of fallthrough opportunities. | |
1266 | CmpInst::Predicate Predicate = CI->getPredicate(); | |
1267 | if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { | |
1268 | std::swap(TBB, FBB); | |
1269 | Predicate = CmpInst::getInversePredicate(Predicate); | |
1270 | } | |
1271 | ||
1272 | ARMCC::CondCodes ARMPred = getComparePred(Predicate); | |
1273 | ||
1274 | // We may not handle every CC for now. | |
1275 | if (ARMPred == ARMCC::AL) return false; | |
1276 | ||
1277 | // Emit the compare. | |
1278 | if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) | |
1279 | return false; | |
1280 | ||
1281 | unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; | |
1a4d82fc | 1282 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) |
223e47cc | 1283 | .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); |
1a4d82fc | 1284 | fastEmitBranch(FBB, DbgLoc); |
223e47cc LB |
1285 | FuncInfo.MBB->addSuccessor(TBB); |
1286 | return true; | |
1287 | } | |
1288 | } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { | |
1289 | MVT SourceVT; | |
1290 | if (TI->hasOneUse() && TI->getParent() == I->getParent() && | |
1291 | (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) { | |
1292 | unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; | |
1293 | unsigned OpReg = getRegForValue(TI->getOperand(0)); | |
1a4d82fc JJ |
1294 | OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); |
1295 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
1296 | TII.get(TstOpc)) |
1297 | .addReg(OpReg).addImm(1)); | |
1298 | ||
1299 | unsigned CCMode = ARMCC::NE; | |
1300 | if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { | |
1301 | std::swap(TBB, FBB); | |
1302 | CCMode = ARMCC::EQ; | |
1303 | } | |
1304 | ||
1305 | unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; | |
1a4d82fc | 1306 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) |
223e47cc LB |
1307 | .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); |
1308 | ||
1a4d82fc | 1309 | fastEmitBranch(FBB, DbgLoc); |
223e47cc LB |
1310 | FuncInfo.MBB->addSuccessor(TBB); |
1311 | return true; | |
1312 | } | |
1313 | } else if (const ConstantInt *CI = | |
1314 | dyn_cast<ConstantInt>(BI->getCondition())) { | |
1315 | uint64_t Imm = CI->getZExtValue(); | |
1316 | MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; | |
1a4d82fc | 1317 | fastEmitBranch(Target, DbgLoc); |
223e47cc LB |
1318 | return true; |
1319 | } | |
1320 | ||
1321 | unsigned CmpReg = getRegForValue(BI->getCondition()); | |
1322 | if (CmpReg == 0) return false; | |
1323 | ||
1324 | // We've been divorced from our compare! Our block was split, and | |
1325 | // now our compare lives in a predecessor block. We musn't | |
1326 | // re-compare here, as the children of the compare aren't guaranteed | |
1327 | // live across the block boundary (we *could* check for this). | |
1328 | // Regardless, the compare has been done in the predecessor block, | |
1329 | // and it left a value for us in a virtual register. Ergo, we test | |
1330 | // the one-bit value left in the virtual register. | |
1331 | unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; | |
1a4d82fc JJ |
1332 | CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); |
1333 | AddOptionalDefs( | |
1334 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc)) | |
1335 | .addReg(CmpReg) | |
1336 | .addImm(1)); | |
223e47cc LB |
1337 | |
1338 | unsigned CCMode = ARMCC::NE; | |
1339 | if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { | |
1340 | std::swap(TBB, FBB); | |
1341 | CCMode = ARMCC::EQ; | |
1342 | } | |
1343 | ||
1344 | unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; | |
1a4d82fc | 1345 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) |
223e47cc | 1346 | .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); |
1a4d82fc | 1347 | fastEmitBranch(FBB, DbgLoc); |
223e47cc LB |
1348 | FuncInfo.MBB->addSuccessor(TBB); |
1349 | return true; | |
1350 | } | |
1351 | ||
1352 | bool ARMFastISel::SelectIndirectBr(const Instruction *I) { | |
1353 | unsigned AddrReg = getRegForValue(I->getOperand(0)); | |
1354 | if (AddrReg == 0) return false; | |
1355 | ||
1356 | unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; | |
1a4d82fc JJ |
1357 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
1358 | TII.get(Opc)).addReg(AddrReg)); | |
970d7e83 LB |
1359 | |
1360 | const IndirectBrInst *IB = cast<IndirectBrInst>(I); | |
1361 | for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i) | |
1362 | FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]); | |
1363 | ||
223e47cc LB |
1364 | return true; |
1365 | } | |
1366 | ||
1367 | bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, | |
1368 | bool isZExt) { | |
1369 | Type *Ty = Src1Value->getType(); | |
970d7e83 LB |
1370 | EVT SrcEVT = TLI.getValueType(Ty, true); |
1371 | if (!SrcEVT.isSimple()) return false; | |
1372 | MVT SrcVT = SrcEVT.getSimpleVT(); | |
223e47cc LB |
1373 | |
1374 | bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy()); | |
1375 | if (isFloat && !Subtarget->hasVFP2()) | |
1376 | return false; | |
1377 | ||
1378 | // Check to see if the 2nd operand is a constant that we can encode directly | |
1379 | // in the compare. | |
1380 | int Imm = 0; | |
1381 | bool UseImm = false; | |
1382 | bool isNegativeImm = false; | |
1383 | // FIXME: At -O0 we don't have anything that canonicalizes operand order. | |
1384 | // Thus, Src1Value may be a ConstantInt, but we're missing it. | |
1385 | if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) { | |
1386 | if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || | |
1387 | SrcVT == MVT::i1) { | |
1388 | const APInt &CIVal = ConstInt->getValue(); | |
1389 | Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue(); | |
1390 | // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather | |
1a4d82fc | 1391 | // then a cmn, because there is no way to represent 2147483648 as a |
223e47cc LB |
1392 | // signed 32-bit int. |
1393 | if (Imm < 0 && Imm != (int)0x80000000) { | |
1394 | isNegativeImm = true; | |
1395 | Imm = -Imm; | |
1396 | } | |
1397 | UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : | |
1398 | (ARM_AM::getSOImmVal(Imm) != -1); | |
1399 | } | |
1400 | } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) { | |
1401 | if (SrcVT == MVT::f32 || SrcVT == MVT::f64) | |
1402 | if (ConstFP->isZero() && !ConstFP->isNegative()) | |
1403 | UseImm = true; | |
1404 | } | |
1405 | ||
1406 | unsigned CmpOpc; | |
1407 | bool isICmp = true; | |
1408 | bool needsExt = false; | |
970d7e83 | 1409 | switch (SrcVT.SimpleTy) { |
223e47cc LB |
1410 | default: return false; |
1411 | // TODO: Verify compares. | |
1412 | case MVT::f32: | |
1413 | isICmp = false; | |
1414 | CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES; | |
1415 | break; | |
1416 | case MVT::f64: | |
1417 | isICmp = false; | |
1418 | CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED; | |
1419 | break; | |
1420 | case MVT::i1: | |
1421 | case MVT::i8: | |
1422 | case MVT::i16: | |
1423 | needsExt = true; | |
1424 | // Intentional fall-through. | |
1425 | case MVT::i32: | |
1426 | if (isThumb2) { | |
1427 | if (!UseImm) | |
1428 | CmpOpc = ARM::t2CMPrr; | |
1429 | else | |
1430 | CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri; | |
1431 | } else { | |
1432 | if (!UseImm) | |
1433 | CmpOpc = ARM::CMPrr; | |
1434 | else | |
1435 | CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri; | |
1436 | } | |
1437 | break; | |
1438 | } | |
1439 | ||
1440 | unsigned SrcReg1 = getRegForValue(Src1Value); | |
1441 | if (SrcReg1 == 0) return false; | |
1442 | ||
1443 | unsigned SrcReg2 = 0; | |
1444 | if (!UseImm) { | |
1445 | SrcReg2 = getRegForValue(Src2Value); | |
1446 | if (SrcReg2 == 0) return false; | |
1447 | } | |
1448 | ||
1449 | // We have i1, i8, or i16, we need to either zero extend or sign extend. | |
1450 | if (needsExt) { | |
1451 | SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); | |
1452 | if (SrcReg1 == 0) return false; | |
1453 | if (!UseImm) { | |
1454 | SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); | |
1455 | if (SrcReg2 == 0) return false; | |
1456 | } | |
1457 | } | |
1458 | ||
1a4d82fc JJ |
1459 | const MCInstrDesc &II = TII.get(CmpOpc); |
1460 | SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); | |
223e47cc | 1461 | if (!UseImm) { |
1a4d82fc JJ |
1462 | SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); |
1463 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) | |
223e47cc LB |
1464 | .addReg(SrcReg1).addReg(SrcReg2)); |
1465 | } else { | |
1466 | MachineInstrBuilder MIB; | |
1a4d82fc | 1467 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) |
223e47cc LB |
1468 | .addReg(SrcReg1); |
1469 | ||
1470 | // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. | |
1471 | if (isICmp) | |
1472 | MIB.addImm(Imm); | |
1473 | AddOptionalDefs(MIB); | |
1474 | } | |
1475 | ||
1476 | // For floating point we need to move the result to a comparison register | |
1477 | // that we can then use for branches. | |
1478 | if (Ty->isFloatTy() || Ty->isDoubleTy()) | |
1a4d82fc | 1479 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1480 | TII.get(ARM::FMSTAT))); |
1481 | return true; | |
1482 | } | |
1483 | ||
1484 | bool ARMFastISel::SelectCmp(const Instruction *I) { | |
1485 | const CmpInst *CI = cast<CmpInst>(I); | |
1486 | ||
1487 | // Get the compare predicate. | |
1488 | ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); | |
1489 | ||
1490 | // We may not handle every CC for now. | |
1491 | if (ARMPred == ARMCC::AL) return false; | |
1492 | ||
1493 | // Emit the compare. | |
1494 | if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) | |
1495 | return false; | |
1496 | ||
1497 | // Now set a register based on the comparison. Explicitly set the predicates | |
1498 | // here. | |
1499 | unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; | |
85aaf69f SL |
1500 | const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass |
1501 | : &ARM::GPRRegClass; | |
223e47cc LB |
1502 | unsigned DestReg = createResultReg(RC); |
1503 | Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); | |
1a4d82fc | 1504 | unsigned ZeroReg = fastMaterializeConstant(Zero); |
223e47cc | 1505 | // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR. |
1a4d82fc | 1506 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg) |
223e47cc LB |
1507 | .addReg(ZeroReg).addImm(1) |
1508 | .addImm(ARMPred).addReg(ARM::CPSR); | |
1509 | ||
1a4d82fc | 1510 | updateValueMap(I, DestReg); |
223e47cc LB |
1511 | return true; |
1512 | } | |
1513 | ||
1514 | bool ARMFastISel::SelectFPExt(const Instruction *I) { | |
1515 | // Make sure we have VFP and that we're extending float to double. | |
1516 | if (!Subtarget->hasVFP2()) return false; | |
1517 | ||
1518 | Value *V = I->getOperand(0); | |
1519 | if (!I->getType()->isDoubleTy() || | |
1520 | !V->getType()->isFloatTy()) return false; | |
1521 | ||
1522 | unsigned Op = getRegForValue(V); | |
1523 | if (Op == 0) return false; | |
1524 | ||
1525 | unsigned Result = createResultReg(&ARM::DPRRegClass); | |
1a4d82fc | 1526 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1527 | TII.get(ARM::VCVTDS), Result) |
1528 | .addReg(Op)); | |
1a4d82fc | 1529 | updateValueMap(I, Result); |
223e47cc LB |
1530 | return true; |
1531 | } | |
1532 | ||
1533 | bool ARMFastISel::SelectFPTrunc(const Instruction *I) { | |
1534 | // Make sure we have VFP and that we're truncating double to float. | |
1535 | if (!Subtarget->hasVFP2()) return false; | |
1536 | ||
1537 | Value *V = I->getOperand(0); | |
1538 | if (!(I->getType()->isFloatTy() && | |
1539 | V->getType()->isDoubleTy())) return false; | |
1540 | ||
1541 | unsigned Op = getRegForValue(V); | |
1542 | if (Op == 0) return false; | |
1543 | ||
1544 | unsigned Result = createResultReg(&ARM::SPRRegClass); | |
1a4d82fc | 1545 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1546 | TII.get(ARM::VCVTSD), Result) |
1547 | .addReg(Op)); | |
1a4d82fc | 1548 | updateValueMap(I, Result); |
223e47cc LB |
1549 | return true; |
1550 | } | |
1551 | ||
1552 | bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) { | |
1553 | // Make sure we have VFP. | |
1554 | if (!Subtarget->hasVFP2()) return false; | |
1555 | ||
1556 | MVT DstVT; | |
1557 | Type *Ty = I->getType(); | |
1558 | if (!isTypeLegal(Ty, DstVT)) | |
1559 | return false; | |
1560 | ||
1561 | Value *Src = I->getOperand(0); | |
970d7e83 LB |
1562 | EVT SrcEVT = TLI.getValueType(Src->getType(), true); |
1563 | if (!SrcEVT.isSimple()) | |
1564 | return false; | |
1565 | MVT SrcVT = SrcEVT.getSimpleVT(); | |
223e47cc LB |
1566 | if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) |
1567 | return false; | |
1568 | ||
1569 | unsigned SrcReg = getRegForValue(Src); | |
1570 | if (SrcReg == 0) return false; | |
1571 | ||
1572 | // Handle sign-extension. | |
1573 | if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { | |
970d7e83 | 1574 | SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32, |
223e47cc LB |
1575 | /*isZExt*/!isSigned); |
1576 | if (SrcReg == 0) return false; | |
1577 | } | |
1578 | ||
1579 | // The conversion routine works on fp-reg to fp-reg and the operand above | |
1580 | // was an integer, move it to the fp registers if possible. | |
1581 | unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); | |
1582 | if (FP == 0) return false; | |
1583 | ||
1584 | unsigned Opc; | |
1585 | if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS; | |
1586 | else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; | |
1587 | else return false; | |
1588 | ||
1589 | unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); | |
1a4d82fc JJ |
1590 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
1591 | TII.get(Opc), ResultReg).addReg(FP)); | |
1592 | updateValueMap(I, ResultReg); | |
223e47cc LB |
1593 | return true; |
1594 | } | |
1595 | ||
1596 | bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) { | |
1597 | // Make sure we have VFP. | |
1598 | if (!Subtarget->hasVFP2()) return false; | |
1599 | ||
1600 | MVT DstVT; | |
1601 | Type *RetTy = I->getType(); | |
1602 | if (!isTypeLegal(RetTy, DstVT)) | |
1603 | return false; | |
1604 | ||
1605 | unsigned Op = getRegForValue(I->getOperand(0)); | |
1606 | if (Op == 0) return false; | |
1607 | ||
1608 | unsigned Opc; | |
1609 | Type *OpTy = I->getOperand(0)->getType(); | |
1610 | if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS; | |
1611 | else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; | |
1612 | else return false; | |
1613 | ||
1614 | // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg. | |
1615 | unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); | |
1a4d82fc JJ |
1616 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
1617 | TII.get(Opc), ResultReg).addReg(Op)); | |
223e47cc LB |
1618 | |
1619 | // This result needs to be in an integer register, but the conversion only | |
1620 | // takes place in fp-regs. | |
1621 | unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); | |
1622 | if (IntReg == 0) return false; | |
1623 | ||
1a4d82fc | 1624 | updateValueMap(I, IntReg); |
223e47cc LB |
1625 | return true; |
1626 | } | |
1627 | ||
1628 | bool ARMFastISel::SelectSelect(const Instruction *I) { | |
1629 | MVT VT; | |
1630 | if (!isTypeLegal(I->getType(), VT)) | |
1631 | return false; | |
1632 | ||
1633 | // Things need to be register sized for register moves. | |
1634 | if (VT != MVT::i32) return false; | |
223e47cc LB |
1635 | |
1636 | unsigned CondReg = getRegForValue(I->getOperand(0)); | |
1637 | if (CondReg == 0) return false; | |
1638 | unsigned Op1Reg = getRegForValue(I->getOperand(1)); | |
1639 | if (Op1Reg == 0) return false; | |
1640 | ||
1641 | // Check to see if we can use an immediate in the conditional move. | |
1642 | int Imm = 0; | |
1643 | bool UseImm = false; | |
1644 | bool isNegativeImm = false; | |
1645 | if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) { | |
1646 | assert (VT == MVT::i32 && "Expecting an i32."); | |
1647 | Imm = (int)ConstInt->getValue().getZExtValue(); | |
1648 | if (Imm < 0) { | |
1649 | isNegativeImm = true; | |
1650 | Imm = ~Imm; | |
1651 | } | |
1652 | UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : | |
1653 | (ARM_AM::getSOImmVal(Imm) != -1); | |
1654 | } | |
1655 | ||
1656 | unsigned Op2Reg = 0; | |
1657 | if (!UseImm) { | |
1658 | Op2Reg = getRegForValue(I->getOperand(2)); | |
1659 | if (Op2Reg == 0) return false; | |
1660 | } | |
1661 | ||
1662 | unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri; | |
1a4d82fc JJ |
1663 | CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0); |
1664 | AddOptionalDefs( | |
1665 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc)) | |
1666 | .addReg(CondReg) | |
1667 | .addImm(0)); | |
223e47cc LB |
1668 | |
1669 | unsigned MovCCOpc; | |
970d7e83 | 1670 | const TargetRegisterClass *RC; |
223e47cc | 1671 | if (!UseImm) { |
970d7e83 | 1672 | RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; |
223e47cc LB |
1673 | MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; |
1674 | } else { | |
970d7e83 LB |
1675 | RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; |
1676 | if (!isNegativeImm) | |
223e47cc | 1677 | MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; |
970d7e83 | 1678 | else |
223e47cc | 1679 | MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; |
223e47cc LB |
1680 | } |
1681 | unsigned ResultReg = createResultReg(RC); | |
1a4d82fc JJ |
1682 | if (!UseImm) { |
1683 | Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); | |
1684 | Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); | |
1685 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), | |
1686 | ResultReg) | |
1687 | .addReg(Op2Reg) | |
1688 | .addReg(Op1Reg) | |
1689 | .addImm(ARMCC::NE) | |
1690 | .addReg(ARM::CPSR); | |
1691 | } else { | |
1692 | Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); | |
1693 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), | |
1694 | ResultReg) | |
1695 | .addReg(Op1Reg) | |
1696 | .addImm(Imm) | |
1697 | .addImm(ARMCC::EQ) | |
1698 | .addReg(ARM::CPSR); | |
1699 | } | |
1700 | updateValueMap(I, ResultReg); | |
223e47cc LB |
1701 | return true; |
1702 | } | |
1703 | ||
1704 | bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) { | |
1705 | MVT VT; | |
1706 | Type *Ty = I->getType(); | |
1707 | if (!isTypeLegal(Ty, VT)) | |
1708 | return false; | |
1709 | ||
1710 | // If we have integer div support we should have selected this automagically. | |
1711 | // In case we have a real miss go ahead and return false and we'll pick | |
1712 | // it up later. | |
1713 | if (Subtarget->hasDivide()) return false; | |
1714 | ||
1715 | // Otherwise emit a libcall. | |
1716 | RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; | |
1717 | if (VT == MVT::i8) | |
1718 | LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8; | |
1719 | else if (VT == MVT::i16) | |
1720 | LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16; | |
1721 | else if (VT == MVT::i32) | |
1722 | LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32; | |
1723 | else if (VT == MVT::i64) | |
1724 | LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64; | |
1725 | else if (VT == MVT::i128) | |
1726 | LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128; | |
1727 | assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); | |
1728 | ||
1729 | return ARMEmitLibcall(I, LC); | |
1730 | } | |
1731 | ||
1732 | bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) { | |
1733 | MVT VT; | |
1734 | Type *Ty = I->getType(); | |
1735 | if (!isTypeLegal(Ty, VT)) | |
1736 | return false; | |
1737 | ||
1738 | RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; | |
1739 | if (VT == MVT::i8) | |
1740 | LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8; | |
1741 | else if (VT == MVT::i16) | |
1742 | LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16; | |
1743 | else if (VT == MVT::i32) | |
1744 | LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32; | |
1745 | else if (VT == MVT::i64) | |
1746 | LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64; | |
1747 | else if (VT == MVT::i128) | |
1748 | LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128; | |
1749 | assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); | |
1750 | ||
1751 | return ARMEmitLibcall(I, LC); | |
1752 | } | |
1753 | ||
1754 | bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { | |
1755 | EVT DestVT = TLI.getValueType(I->getType(), true); | |
1756 | ||
1757 | // We can get here in the case when we have a binary operation on a non-legal | |
1758 | // type and the target independent selector doesn't know how to handle it. | |
1759 | if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) | |
1760 | return false; | |
1761 | ||
1762 | unsigned Opc; | |
1763 | switch (ISDOpcode) { | |
1764 | default: return false; | |
1765 | case ISD::ADD: | |
1766 | Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; | |
1767 | break; | |
1768 | case ISD::OR: | |
1769 | Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; | |
1770 | break; | |
1771 | case ISD::SUB: | |
1772 | Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; | |
1773 | break; | |
1774 | } | |
1775 | ||
1776 | unsigned SrcReg1 = getRegForValue(I->getOperand(0)); | |
1777 | if (SrcReg1 == 0) return false; | |
1778 | ||
1779 | // TODO: Often the 2nd operand is an immediate, which can be encoded directly | |
1780 | // in the instruction, rather then materializing the value in a register. | |
1781 | unsigned SrcReg2 = getRegForValue(I->getOperand(1)); | |
1782 | if (SrcReg2 == 0) return false; | |
1783 | ||
1a4d82fc JJ |
1784 | unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); |
1785 | SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); | |
1786 | SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); | |
1787 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
1788 | TII.get(Opc), ResultReg) |
1789 | .addReg(SrcReg1).addReg(SrcReg2)); | |
1a4d82fc | 1790 | updateValueMap(I, ResultReg); |
223e47cc LB |
1791 | return true; |
1792 | } | |
1793 | ||
1794 | bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) { | |
970d7e83 LB |
1795 | EVT FPVT = TLI.getValueType(I->getType(), true); |
1796 | if (!FPVT.isSimple()) return false; | |
1797 | MVT VT = FPVT.getSimpleVT(); | |
223e47cc LB |
1798 | |
1799 | // We can get here in the case when we want to use NEON for our fp | |
1800 | // operations, but can't figure out how to. Just use the vfp instructions | |
1801 | // if we have them. | |
1802 | // FIXME: It'd be nice to use NEON instructions. | |
1803 | Type *Ty = I->getType(); | |
1804 | bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); | |
1805 | if (isFloat && !Subtarget->hasVFP2()) | |
1806 | return false; | |
1807 | ||
1808 | unsigned Opc; | |
1809 | bool is64bit = VT == MVT::f64 || VT == MVT::i64; | |
1810 | switch (ISDOpcode) { | |
1811 | default: return false; | |
1812 | case ISD::FADD: | |
1813 | Opc = is64bit ? ARM::VADDD : ARM::VADDS; | |
1814 | break; | |
1815 | case ISD::FSUB: | |
1816 | Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; | |
1817 | break; | |
1818 | case ISD::FMUL: | |
1819 | Opc = is64bit ? ARM::VMULD : ARM::VMULS; | |
1820 | break; | |
1821 | } | |
1822 | unsigned Op1 = getRegForValue(I->getOperand(0)); | |
1823 | if (Op1 == 0) return false; | |
1824 | ||
1825 | unsigned Op2 = getRegForValue(I->getOperand(1)); | |
1826 | if (Op2 == 0) return false; | |
1827 | ||
970d7e83 | 1828 | unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); |
1a4d82fc | 1829 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1830 | TII.get(Opc), ResultReg) |
1831 | .addReg(Op1).addReg(Op2)); | |
1a4d82fc | 1832 | updateValueMap(I, ResultReg); |
223e47cc LB |
1833 | return true; |
1834 | } | |
1835 | ||
1836 | // Call Handling Code | |
1837 | ||
1838 | // This is largely taken directly from CCAssignFnForNode | |
1839 | // TODO: We may not support all of this. | |
1840 | CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, | |
1841 | bool Return, | |
1842 | bool isVarArg) { | |
1843 | switch (CC) { | |
1844 | default: | |
1845 | llvm_unreachable("Unsupported calling convention"); | |
1846 | case CallingConv::Fast: | |
1847 | if (Subtarget->hasVFP2() && !isVarArg) { | |
1848 | if (!Subtarget->isAAPCS_ABI()) | |
1849 | return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); | |
1850 | // For AAPCS ABI targets, just use VFP variant of the calling convention. | |
1851 | return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); | |
1852 | } | |
1853 | // Fallthrough | |
1854 | case CallingConv::C: | |
1855 | // Use target triple & subtarget features to do actual dispatch. | |
1856 | if (Subtarget->isAAPCS_ABI()) { | |
1857 | if (Subtarget->hasVFP2() && | |
1858 | TM.Options.FloatABIType == FloatABI::Hard && !isVarArg) | |
1859 | return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); | |
1860 | else | |
1861 | return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); | |
1862 | } else | |
1863 | return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); | |
1864 | case CallingConv::ARM_AAPCS_VFP: | |
1865 | if (!isVarArg) | |
1866 | return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); | |
1867 | // Fall through to soft float variant, variadic functions don't | |
1868 | // use hard floating point ABI. | |
1869 | case CallingConv::ARM_AAPCS: | |
1870 | return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); | |
1871 | case CallingConv::ARM_APCS: | |
1872 | return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); | |
1873 | case CallingConv::GHC: | |
1874 | if (Return) | |
1875 | llvm_unreachable("Can't return in GHC call convention"); | |
1876 | else | |
1877 | return CC_ARM_APCS_GHC; | |
1878 | } | |
1879 | } | |
1880 | ||
1881 | bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, | |
1882 | SmallVectorImpl<unsigned> &ArgRegs, | |
1883 | SmallVectorImpl<MVT> &ArgVTs, | |
1884 | SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, | |
1885 | SmallVectorImpl<unsigned> &RegArgs, | |
1886 | CallingConv::ID CC, | |
1887 | unsigned &NumBytes, | |
1888 | bool isVarArg) { | |
1889 | SmallVector<CCValAssign, 16> ArgLocs; | |
1a4d82fc | 1890 | CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context); |
223e47cc LB |
1891 | CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, |
1892 | CCAssignFnForCall(CC, false, isVarArg)); | |
1893 | ||
1894 | // Check that we can handle all of the arguments. If we can't, then bail out | |
1895 | // now before we add code to the MBB. | |
1896 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |
1897 | CCValAssign &VA = ArgLocs[i]; | |
1898 | MVT ArgVT = ArgVTs[VA.getValNo()]; | |
1899 | ||
1900 | // We don't handle NEON/vector parameters yet. | |
1901 | if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64) | |
1902 | return false; | |
1903 | ||
1904 | // Now copy/store arg to correct locations. | |
1905 | if (VA.isRegLoc() && !VA.needsCustom()) { | |
1906 | continue; | |
1907 | } else if (VA.needsCustom()) { | |
1908 | // TODO: We need custom lowering for vector (v2f64) args. | |
1909 | if (VA.getLocVT() != MVT::f64 || | |
1910 | // TODO: Only handle register args for now. | |
1911 | !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) | |
1912 | return false; | |
1913 | } else { | |
1a4d82fc | 1914 | switch (ArgVT.SimpleTy) { |
223e47cc LB |
1915 | default: |
1916 | return false; | |
1917 | case MVT::i1: | |
1918 | case MVT::i8: | |
1919 | case MVT::i16: | |
1920 | case MVT::i32: | |
1921 | break; | |
1922 | case MVT::f32: | |
1923 | if (!Subtarget->hasVFP2()) | |
1924 | return false; | |
1925 | break; | |
1926 | case MVT::f64: | |
1927 | if (!Subtarget->hasVFP2()) | |
1928 | return false; | |
1929 | break; | |
1930 | } | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | // At the point, we are able to handle the call's arguments in fast isel. | |
1935 | ||
1936 | // Get a count of how many bytes are to be pushed on the stack. | |
1937 | NumBytes = CCInfo.getNextStackOffset(); | |
1938 | ||
1939 | // Issue CALLSEQ_START | |
1940 | unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); | |
1a4d82fc | 1941 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
1942 | TII.get(AdjStackDown)) |
1943 | .addImm(NumBytes)); | |
1944 | ||
1945 | // Process the args. | |
1946 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |
1947 | CCValAssign &VA = ArgLocs[i]; | |
1a4d82fc | 1948 | const Value *ArgVal = Args[VA.getValNo()]; |
223e47cc LB |
1949 | unsigned Arg = ArgRegs[VA.getValNo()]; |
1950 | MVT ArgVT = ArgVTs[VA.getValNo()]; | |
1951 | ||
1952 | assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) && | |
1953 | "We don't handle NEON/vector parameters yet."); | |
1954 | ||
1955 | // Handle arg promotion, etc. | |
1956 | switch (VA.getLocInfo()) { | |
1957 | case CCValAssign::Full: break; | |
1958 | case CCValAssign::SExt: { | |
1959 | MVT DestVT = VA.getLocVT(); | |
1960 | Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); | |
1961 | assert (Arg != 0 && "Failed to emit a sext"); | |
1962 | ArgVT = DestVT; | |
1963 | break; | |
1964 | } | |
1965 | case CCValAssign::AExt: | |
1966 | // Intentional fall-through. Handle AExt and ZExt. | |
1967 | case CCValAssign::ZExt: { | |
1968 | MVT DestVT = VA.getLocVT(); | |
1969 | Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); | |
1a4d82fc | 1970 | assert (Arg != 0 && "Failed to emit a zext"); |
223e47cc LB |
1971 | ArgVT = DestVT; |
1972 | break; | |
1973 | } | |
1974 | case CCValAssign::BCvt: { | |
1a4d82fc | 1975 | unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, |
223e47cc LB |
1976 | /*TODO: Kill=*/false); |
1977 | assert(BC != 0 && "Failed to emit a bitcast!"); | |
1978 | Arg = BC; | |
1979 | ArgVT = VA.getLocVT(); | |
1980 | break; | |
1981 | } | |
1982 | default: llvm_unreachable("Unknown arg promotion!"); | |
1983 | } | |
1984 | ||
1985 | // Now copy/store arg to correct locations. | |
1986 | if (VA.isRegLoc() && !VA.needsCustom()) { | |
1a4d82fc JJ |
1987 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
1988 | TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); | |
223e47cc LB |
1989 | RegArgs.push_back(VA.getLocReg()); |
1990 | } else if (VA.needsCustom()) { | |
1991 | // TODO: We need custom lowering for vector (v2f64) args. | |
1992 | assert(VA.getLocVT() == MVT::f64 && | |
1993 | "Custom lowering for v2f64 args not available"); | |
1994 | ||
1995 | CCValAssign &NextVA = ArgLocs[++i]; | |
1996 | ||
1997 | assert(VA.isRegLoc() && NextVA.isRegLoc() && | |
1998 | "We only handle register args!"); | |
1999 | ||
1a4d82fc | 2000 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
2001 | TII.get(ARM::VMOVRRD), VA.getLocReg()) |
2002 | .addReg(NextVA.getLocReg(), RegState::Define) | |
2003 | .addReg(Arg)); | |
2004 | RegArgs.push_back(VA.getLocReg()); | |
2005 | RegArgs.push_back(NextVA.getLocReg()); | |
2006 | } else { | |
2007 | assert(VA.isMemLoc()); | |
2008 | // Need to store on the stack. | |
1a4d82fc JJ |
2009 | |
2010 | // Don't emit stores for undef values. | |
2011 | if (isa<UndefValue>(ArgVal)) | |
2012 | continue; | |
2013 | ||
223e47cc LB |
2014 | Address Addr; |
2015 | Addr.BaseType = Address::RegBase; | |
2016 | Addr.Base.Reg = ARM::SP; | |
2017 | Addr.Offset = VA.getLocMemOffset(); | |
2018 | ||
2019 | bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet; | |
2020 | assert(EmitRet && "Could not emit a store for argument!"); | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | return true; | |
2025 | } | |
2026 | ||
2027 | bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, | |
2028 | const Instruction *I, CallingConv::ID CC, | |
2029 | unsigned &NumBytes, bool isVarArg) { | |
2030 | // Issue CALLSEQ_END | |
2031 | unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); | |
1a4d82fc | 2032 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
2033 | TII.get(AdjStackUp)) |
2034 | .addImm(NumBytes).addImm(0)); | |
2035 | ||
2036 | // Now the return value. | |
2037 | if (RetVT != MVT::isVoid) { | |
2038 | SmallVector<CCValAssign, 16> RVLocs; | |
1a4d82fc | 2039 | CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); |
223e47cc LB |
2040 | CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); |
2041 | ||
2042 | // Copy all of the result registers out of their specified physreg. | |
2043 | if (RVLocs.size() == 2 && RetVT == MVT::f64) { | |
2044 | // For this move we copy into two registers and then move into the | |
2045 | // double fp reg we want. | |
970d7e83 | 2046 | MVT DestVT = RVLocs[0].getValVT(); |
223e47cc LB |
2047 | const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); |
2048 | unsigned ResultReg = createResultReg(DstRC); | |
1a4d82fc | 2049 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
2050 | TII.get(ARM::VMOVDRR), ResultReg) |
2051 | .addReg(RVLocs[0].getLocReg()) | |
2052 | .addReg(RVLocs[1].getLocReg())); | |
2053 | ||
2054 | UsedRegs.push_back(RVLocs[0].getLocReg()); | |
2055 | UsedRegs.push_back(RVLocs[1].getLocReg()); | |
2056 | ||
2057 | // Finally update the result. | |
1a4d82fc | 2058 | updateValueMap(I, ResultReg); |
223e47cc LB |
2059 | } else { |
2060 | assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); | |
970d7e83 | 2061 | MVT CopyVT = RVLocs[0].getValVT(); |
223e47cc LB |
2062 | |
2063 | // Special handling for extended integers. | |
2064 | if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) | |
2065 | CopyVT = MVT::i32; | |
2066 | ||
2067 | const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); | |
2068 | ||
2069 | unsigned ResultReg = createResultReg(DstRC); | |
1a4d82fc JJ |
2070 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
2071 | TII.get(TargetOpcode::COPY), | |
223e47cc LB |
2072 | ResultReg).addReg(RVLocs[0].getLocReg()); |
2073 | UsedRegs.push_back(RVLocs[0].getLocReg()); | |
2074 | ||
2075 | // Finally update the result. | |
1a4d82fc | 2076 | updateValueMap(I, ResultReg); |
223e47cc LB |
2077 | } |
2078 | } | |
2079 | ||
2080 | return true; | |
2081 | } | |
2082 | ||
2083 | bool ARMFastISel::SelectRet(const Instruction *I) { | |
2084 | const ReturnInst *Ret = cast<ReturnInst>(I); | |
2085 | const Function &F = *I->getParent()->getParent(); | |
2086 | ||
2087 | if (!FuncInfo.CanLowerReturn) | |
2088 | return false; | |
2089 | ||
970d7e83 LB |
2090 | // Build a list of return value registers. |
2091 | SmallVector<unsigned, 4> RetRegs; | |
2092 | ||
223e47cc LB |
2093 | CallingConv::ID CC = F.getCallingConv(); |
2094 | if (Ret->getNumOperands() > 0) { | |
2095 | SmallVector<ISD::OutputArg, 4> Outs; | |
970d7e83 | 2096 | GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); |
223e47cc LB |
2097 | |
2098 | // Analyze operands of the call, assigning locations to each operand. | |
2099 | SmallVector<CCValAssign, 16> ValLocs; | |
1a4d82fc | 2100 | CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext()); |
223e47cc LB |
2101 | CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */, |
2102 | F.isVarArg())); | |
2103 | ||
2104 | const Value *RV = Ret->getOperand(0); | |
2105 | unsigned Reg = getRegForValue(RV); | |
2106 | if (Reg == 0) | |
2107 | return false; | |
2108 | ||
2109 | // Only handle a single return value for now. | |
2110 | if (ValLocs.size() != 1) | |
2111 | return false; | |
2112 | ||
2113 | CCValAssign &VA = ValLocs[0]; | |
2114 | ||
2115 | // Don't bother handling odd stuff for now. | |
2116 | if (VA.getLocInfo() != CCValAssign::Full) | |
2117 | return false; | |
2118 | // Only handle register returns for now. | |
2119 | if (!VA.isRegLoc()) | |
2120 | return false; | |
2121 | ||
2122 | unsigned SrcReg = Reg + VA.getValNo(); | |
970d7e83 LB |
2123 | EVT RVEVT = TLI.getValueType(RV->getType()); |
2124 | if (!RVEVT.isSimple()) return false; | |
2125 | MVT RVVT = RVEVT.getSimpleVT(); | |
2126 | MVT DestVT = VA.getValVT(); | |
223e47cc LB |
2127 | // Special handling for extended integers. |
2128 | if (RVVT != DestVT) { | |
2129 | if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) | |
2130 | return false; | |
2131 | ||
2132 | assert(DestVT == MVT::i32 && "ARM should always ext to i32"); | |
2133 | ||
2134 | // Perform extension if flagged as either zext or sext. Otherwise, do | |
2135 | // nothing. | |
2136 | if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { | |
2137 | SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt()); | |
2138 | if (SrcReg == 0) return false; | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | // Make the copy. | |
2143 | unsigned DstReg = VA.getLocReg(); | |
2144 | const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); | |
2145 | // Avoid a cross-class copy. This is very unlikely. | |
2146 | if (!SrcRC->contains(DstReg)) | |
2147 | return false; | |
1a4d82fc JJ |
2148 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
2149 | TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg); | |
223e47cc | 2150 | |
970d7e83 LB |
2151 | // Add register to return instruction. |
2152 | RetRegs.push_back(VA.getLocReg()); | |
223e47cc LB |
2153 | } |
2154 | ||
2155 | unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET; | |
1a4d82fc | 2156 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
970d7e83 LB |
2157 | TII.get(RetOpc)); |
2158 | AddOptionalDefs(MIB); | |
2159 | for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) | |
2160 | MIB.addReg(RetRegs[i], RegState::Implicit); | |
223e47cc LB |
2161 | return true; |
2162 | } | |
2163 | ||
2164 | unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { | |
2165 | if (UseReg) | |
2166 | return isThumb2 ? ARM::tBLXr : ARM::BLX; | |
2167 | else | |
2168 | return isThumb2 ? ARM::tBL : ARM::BL; | |
2169 | } | |
2170 | ||
2171 | unsigned ARMFastISel::getLibcallReg(const Twine &Name) { | |
1a4d82fc JJ |
2172 | // Manually compute the global's type to avoid building it when unnecessary. |
2173 | Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0); | |
2174 | EVT LCREVT = TLI.getValueType(GVTy); | |
970d7e83 | 2175 | if (!LCREVT.isSimple()) return 0; |
1a4d82fc JJ |
2176 | |
2177 | GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false, | |
2178 | GlobalValue::ExternalLinkage, nullptr, | |
2179 | Name); | |
2180 | assert(GV->getType() == GVTy && "We miscomputed the type for the global!"); | |
970d7e83 | 2181 | return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); |
223e47cc LB |
2182 | } |
2183 | ||
2184 | // A quick function that will emit a call for a named libcall in F with the | |
2185 | // vector of passed arguments for the Instruction in I. We can assume that we | |
2186 | // can emit a call for any libcall we can produce. This is an abridged version | |
2187 | // of the full call infrastructure since we won't need to worry about things | |
2188 | // like computed function pointers or strange arguments at call sites. | |
2189 | // TODO: Try to unify this and the normal call bits for ARM, then try to unify | |
2190 | // with X86. | |
2191 | bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { | |
2192 | CallingConv::ID CC = TLI.getLibcallCallingConv(Call); | |
2193 | ||
2194 | // Handle *simple* calls for now. | |
2195 | Type *RetTy = I->getType(); | |
2196 | MVT RetVT; | |
2197 | if (RetTy->isVoidTy()) | |
2198 | RetVT = MVT::isVoid; | |
2199 | else if (!isTypeLegal(RetTy, RetVT)) | |
2200 | return false; | |
2201 | ||
2202 | // Can't handle non-double multi-reg retvals. | |
2203 | if (RetVT != MVT::isVoid && RetVT != MVT::i32) { | |
2204 | SmallVector<CCValAssign, 16> RVLocs; | |
1a4d82fc | 2205 | CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); |
223e47cc LB |
2206 | CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false)); |
2207 | if (RVLocs.size() >= 2 && RetVT != MVT::f64) | |
2208 | return false; | |
2209 | } | |
2210 | ||
2211 | // Set up the argument vectors. | |
2212 | SmallVector<Value*, 8> Args; | |
2213 | SmallVector<unsigned, 8> ArgRegs; | |
2214 | SmallVector<MVT, 8> ArgVTs; | |
2215 | SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; | |
2216 | Args.reserve(I->getNumOperands()); | |
2217 | ArgRegs.reserve(I->getNumOperands()); | |
2218 | ArgVTs.reserve(I->getNumOperands()); | |
2219 | ArgFlags.reserve(I->getNumOperands()); | |
2220 | for (unsigned i = 0; i < I->getNumOperands(); ++i) { | |
2221 | Value *Op = I->getOperand(i); | |
2222 | unsigned Arg = getRegForValue(Op); | |
2223 | if (Arg == 0) return false; | |
2224 | ||
2225 | Type *ArgTy = Op->getType(); | |
2226 | MVT ArgVT; | |
2227 | if (!isTypeLegal(ArgTy, ArgVT)) return false; | |
2228 | ||
2229 | ISD::ArgFlagsTy Flags; | |
1a4d82fc | 2230 | unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy); |
223e47cc LB |
2231 | Flags.setOrigAlign(OriginalAlignment); |
2232 | ||
2233 | Args.push_back(Op); | |
2234 | ArgRegs.push_back(Arg); | |
2235 | ArgVTs.push_back(ArgVT); | |
2236 | ArgFlags.push_back(Flags); | |
2237 | } | |
2238 | ||
2239 | // Handle the arguments now that we've gotten them. | |
2240 | SmallVector<unsigned, 4> RegArgs; | |
2241 | unsigned NumBytes; | |
2242 | if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, | |
2243 | RegArgs, CC, NumBytes, false)) | |
2244 | return false; | |
2245 | ||
2246 | unsigned CalleeReg = 0; | |
2247 | if (EnableARMLongCalls) { | |
2248 | CalleeReg = getLibcallReg(TLI.getLibcallName(Call)); | |
2249 | if (CalleeReg == 0) return false; | |
2250 | } | |
2251 | ||
2252 | // Issue the call. | |
2253 | unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls); | |
2254 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, | |
1a4d82fc | 2255 | DbgLoc, TII.get(CallOpc)); |
223e47cc LB |
2256 | // BL / BLX don't take a predicate, but tBL / tBLX do. |
2257 | if (isThumb2) | |
2258 | AddDefaultPred(MIB); | |
2259 | if (EnableARMLongCalls) | |
2260 | MIB.addReg(CalleeReg); | |
2261 | else | |
2262 | MIB.addExternalSymbol(TLI.getLibcallName(Call)); | |
2263 | ||
2264 | // Add implicit physical register uses to the call. | |
2265 | for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) | |
2266 | MIB.addReg(RegArgs[i], RegState::Implicit); | |
2267 | ||
2268 | // Add a register mask with the call-preserved registers. | |
2269 | // Proper defs for return values will be added by setPhysRegsDeadExcept(). | |
2270 | MIB.addRegMask(TRI.getCallPreservedMask(CC)); | |
2271 | ||
2272 | // Finish off the call including any return values. | |
2273 | SmallVector<unsigned, 4> UsedRegs; | |
2274 | if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; | |
2275 | ||
2276 | // Set all unused physreg defs as dead. | |
2277 | static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); | |
2278 | ||
2279 | return true; | |
2280 | } | |
2281 | ||
2282 | bool ARMFastISel::SelectCall(const Instruction *I, | |
1a4d82fc | 2283 | const char *IntrMemName = nullptr) { |
223e47cc LB |
2284 | const CallInst *CI = cast<CallInst>(I); |
2285 | const Value *Callee = CI->getCalledValue(); | |
2286 | ||
2287 | // Can't handle inline asm. | |
2288 | if (isa<InlineAsm>(Callee)) return false; | |
2289 | ||
970d7e83 LB |
2290 | // Allow SelectionDAG isel to handle tail calls. |
2291 | if (CI->isTailCall()) return false; | |
2292 | ||
223e47cc LB |
2293 | // Check the calling convention. |
2294 | ImmutableCallSite CS(CI); | |
2295 | CallingConv::ID CC = CS.getCallingConv(); | |
2296 | ||
2297 | // TODO: Avoid some calling conventions? | |
2298 | ||
2299 | PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); | |
2300 | FunctionType *FTy = cast<FunctionType>(PT->getElementType()); | |
2301 | bool isVarArg = FTy->isVarArg(); | |
2302 | ||
2303 | // Handle *simple* calls for now. | |
2304 | Type *RetTy = I->getType(); | |
2305 | MVT RetVT; | |
2306 | if (RetTy->isVoidTy()) | |
2307 | RetVT = MVT::isVoid; | |
2308 | else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && | |
2309 | RetVT != MVT::i8 && RetVT != MVT::i1) | |
2310 | return false; | |
2311 | ||
2312 | // Can't handle non-double multi-reg retvals. | |
2313 | if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 && | |
2314 | RetVT != MVT::i16 && RetVT != MVT::i32) { | |
2315 | SmallVector<CCValAssign, 16> RVLocs; | |
1a4d82fc | 2316 | CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); |
223e47cc LB |
2317 | CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); |
2318 | if (RVLocs.size() >= 2 && RetVT != MVT::f64) | |
2319 | return false; | |
2320 | } | |
2321 | ||
2322 | // Set up the argument vectors. | |
2323 | SmallVector<Value*, 8> Args; | |
2324 | SmallVector<unsigned, 8> ArgRegs; | |
2325 | SmallVector<MVT, 8> ArgVTs; | |
2326 | SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; | |
2327 | unsigned arg_size = CS.arg_size(); | |
2328 | Args.reserve(arg_size); | |
2329 | ArgRegs.reserve(arg_size); | |
2330 | ArgVTs.reserve(arg_size); | |
2331 | ArgFlags.reserve(arg_size); | |
2332 | for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); | |
2333 | i != e; ++i) { | |
2334 | // If we're lowering a memory intrinsic instead of a regular call, skip the | |
2335 | // last two arguments, which shouldn't be passed to the underlying function. | |
2336 | if (IntrMemName && e-i <= 2) | |
2337 | break; | |
2338 | ||
2339 | ISD::ArgFlagsTy Flags; | |
2340 | unsigned AttrInd = i - CS.arg_begin() + 1; | |
2341 | if (CS.paramHasAttr(AttrInd, Attribute::SExt)) | |
2342 | Flags.setSExt(); | |
2343 | if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) | |
2344 | Flags.setZExt(); | |
2345 | ||
2346 | // FIXME: Only handle *easy* calls for now. | |
2347 | if (CS.paramHasAttr(AttrInd, Attribute::InReg) || | |
2348 | CS.paramHasAttr(AttrInd, Attribute::StructRet) || | |
2349 | CS.paramHasAttr(AttrInd, Attribute::Nest) || | |
2350 | CS.paramHasAttr(AttrInd, Attribute::ByVal)) | |
2351 | return false; | |
2352 | ||
2353 | Type *ArgTy = (*i)->getType(); | |
2354 | MVT ArgVT; | |
2355 | if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && | |
2356 | ArgVT != MVT::i1) | |
2357 | return false; | |
2358 | ||
2359 | unsigned Arg = getRegForValue(*i); | |
2360 | if (Arg == 0) | |
2361 | return false; | |
2362 | ||
1a4d82fc | 2363 | unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy); |
223e47cc LB |
2364 | Flags.setOrigAlign(OriginalAlignment); |
2365 | ||
2366 | Args.push_back(*i); | |
2367 | ArgRegs.push_back(Arg); | |
2368 | ArgVTs.push_back(ArgVT); | |
2369 | ArgFlags.push_back(Flags); | |
2370 | } | |
2371 | ||
2372 | // Handle the arguments now that we've gotten them. | |
2373 | SmallVector<unsigned, 4> RegArgs; | |
2374 | unsigned NumBytes; | |
2375 | if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, | |
2376 | RegArgs, CC, NumBytes, isVarArg)) | |
2377 | return false; | |
2378 | ||
2379 | bool UseReg = false; | |
2380 | const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); | |
2381 | if (!GV || EnableARMLongCalls) UseReg = true; | |
2382 | ||
2383 | unsigned CalleeReg = 0; | |
2384 | if (UseReg) { | |
2385 | if (IntrMemName) | |
2386 | CalleeReg = getLibcallReg(IntrMemName); | |
2387 | else | |
2388 | CalleeReg = getRegForValue(Callee); | |
2389 | ||
2390 | if (CalleeReg == 0) return false; | |
2391 | } | |
2392 | ||
2393 | // Issue the call. | |
2394 | unsigned CallOpc = ARMSelectCallOp(UseReg); | |
2395 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, | |
1a4d82fc JJ |
2396 | DbgLoc, TII.get(CallOpc)); |
2397 | ||
2398 | unsigned char OpFlags = 0; | |
2399 | ||
2400 | // Add MO_PLT for global address or external symbol in the PIC relocation | |
2401 | // model. | |
2402 | if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_) | |
2403 | OpFlags = ARMII::MO_PLT; | |
223e47cc LB |
2404 | |
2405 | // ARM calls don't take a predicate, but tBL / tBLX do. | |
2406 | if(isThumb2) | |
2407 | AddDefaultPred(MIB); | |
2408 | if (UseReg) | |
2409 | MIB.addReg(CalleeReg); | |
2410 | else if (!IntrMemName) | |
1a4d82fc | 2411 | MIB.addGlobalAddress(GV, 0, OpFlags); |
223e47cc | 2412 | else |
1a4d82fc | 2413 | MIB.addExternalSymbol(IntrMemName, OpFlags); |
223e47cc LB |
2414 | |
2415 | // Add implicit physical register uses to the call. | |
2416 | for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) | |
2417 | MIB.addReg(RegArgs[i], RegState::Implicit); | |
2418 | ||
2419 | // Add a register mask with the call-preserved registers. | |
2420 | // Proper defs for return values will be added by setPhysRegsDeadExcept(). | |
2421 | MIB.addRegMask(TRI.getCallPreservedMask(CC)); | |
2422 | ||
2423 | // Finish off the call including any return values. | |
2424 | SmallVector<unsigned, 4> UsedRegs; | |
2425 | if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) | |
2426 | return false; | |
2427 | ||
2428 | // Set all unused physreg defs as dead. | |
2429 | static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); | |
2430 | ||
2431 | return true; | |
2432 | } | |
2433 | ||
2434 | bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) { | |
2435 | return Len <= 16; | |
2436 | } | |
2437 | ||
2438 | bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, | |
970d7e83 | 2439 | uint64_t Len, unsigned Alignment) { |
223e47cc LB |
2440 | // Make sure we don't bloat code by inlining very large memcpy's. |
2441 | if (!ARMIsMemCpySmall(Len)) | |
2442 | return false; | |
2443 | ||
223e47cc LB |
2444 | while (Len) { |
2445 | MVT VT; | |
970d7e83 LB |
2446 | if (!Alignment || Alignment >= 4) { |
2447 | if (Len >= 4) | |
2448 | VT = MVT::i32; | |
2449 | else if (Len >= 2) | |
2450 | VT = MVT::i16; | |
2451 | else { | |
2452 | assert (Len == 1 && "Expected a length of 1!"); | |
2453 | VT = MVT::i8; | |
2454 | } | |
2455 | } else { | |
2456 | // Bound based on alignment. | |
2457 | if (Len >= 2 && Alignment == 2) | |
2458 | VT = MVT::i16; | |
2459 | else { | |
2460 | VT = MVT::i8; | |
2461 | } | |
223e47cc LB |
2462 | } |
2463 | ||
2464 | bool RV; | |
2465 | unsigned ResultReg; | |
2466 | RV = ARMEmitLoad(VT, ResultReg, Src); | |
2467 | assert (RV == true && "Should be able to handle this load."); | |
2468 | RV = ARMEmitStore(VT, ResultReg, Dest); | |
2469 | assert (RV == true && "Should be able to handle this store."); | |
2470 | (void)RV; | |
2471 | ||
2472 | unsigned Size = VT.getSizeInBits()/8; | |
2473 | Len -= Size; | |
2474 | Dest.Offset += Size; | |
2475 | Src.Offset += Size; | |
2476 | } | |
2477 | ||
2478 | return true; | |
2479 | } | |
2480 | ||
2481 | bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) { | |
2482 | // FIXME: Handle more intrinsics. | |
2483 | switch (I.getIntrinsicID()) { | |
2484 | default: return false; | |
2485 | case Intrinsic::frameaddress: { | |
2486 | MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo(); | |
2487 | MFI->setFrameAddressIsTaken(true); | |
2488 | ||
85aaf69f SL |
2489 | unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; |
2490 | const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass | |
2491 | : &ARM::GPRRegClass; | |
223e47cc LB |
2492 | |
2493 | const ARMBaseRegisterInfo *RegInfo = | |
1a4d82fc JJ |
2494 | static_cast<const ARMBaseRegisterInfo *>( |
2495 | TM.getSubtargetImpl()->getRegisterInfo()); | |
223e47cc LB |
2496 | unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF)); |
2497 | unsigned SrcReg = FramePtr; | |
2498 | ||
2499 | // Recursively load frame address | |
2500 | // ldr r0 [fp] | |
2501 | // ldr r0 [r0] | |
2502 | // ldr r0 [r0] | |
2503 | // ... | |
2504 | unsigned DestReg; | |
2505 | unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue(); | |
2506 | while (Depth--) { | |
2507 | DestReg = createResultReg(RC); | |
1a4d82fc | 2508 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
2509 | TII.get(LdrOpc), DestReg) |
2510 | .addReg(SrcReg).addImm(0)); | |
2511 | SrcReg = DestReg; | |
2512 | } | |
1a4d82fc | 2513 | updateValueMap(&I, SrcReg); |
223e47cc LB |
2514 | return true; |
2515 | } | |
2516 | case Intrinsic::memcpy: | |
2517 | case Intrinsic::memmove: { | |
2518 | const MemTransferInst &MTI = cast<MemTransferInst>(I); | |
2519 | // Don't handle volatile. | |
2520 | if (MTI.isVolatile()) | |
2521 | return false; | |
2522 | ||
2523 | // Disable inlining for memmove before calls to ComputeAddress. Otherwise, | |
2524 | // we would emit dead code because we don't currently handle memmoves. | |
2525 | bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy); | |
2526 | if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) { | |
2527 | // Small memcpy's are common enough that we want to do them without a call | |
2528 | // if possible. | |
2529 | uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue(); | |
2530 | if (ARMIsMemCpySmall(Len)) { | |
2531 | Address Dest, Src; | |
2532 | if (!ARMComputeAddress(MTI.getRawDest(), Dest) || | |
2533 | !ARMComputeAddress(MTI.getRawSource(), Src)) | |
2534 | return false; | |
970d7e83 LB |
2535 | unsigned Alignment = MTI.getAlignment(); |
2536 | if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment)) | |
223e47cc LB |
2537 | return true; |
2538 | } | |
2539 | } | |
2540 | ||
2541 | if (!MTI.getLength()->getType()->isIntegerTy(32)) | |
2542 | return false; | |
2543 | ||
2544 | if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255) | |
2545 | return false; | |
2546 | ||
2547 | const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove"; | |
2548 | return SelectCall(&I, IntrMemName); | |
2549 | } | |
2550 | case Intrinsic::memset: { | |
2551 | const MemSetInst &MSI = cast<MemSetInst>(I); | |
2552 | // Don't handle volatile. | |
2553 | if (MSI.isVolatile()) | |
2554 | return false; | |
2555 | ||
2556 | if (!MSI.getLength()->getType()->isIntegerTy(32)) | |
2557 | return false; | |
2558 | ||
2559 | if (MSI.getDestAddressSpace() > 255) | |
2560 | return false; | |
2561 | ||
2562 | return SelectCall(&I, "memset"); | |
2563 | } | |
2564 | case Intrinsic::trap: { | |
1a4d82fc | 2565 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get( |
970d7e83 | 2566 | Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP)); |
223e47cc LB |
2567 | return true; |
2568 | } | |
2569 | } | |
2570 | } | |
2571 | ||
2572 | bool ARMFastISel::SelectTrunc(const Instruction *I) { | |
2573 | // The high bits for a type smaller than the register size are assumed to be | |
2574 | // undefined. | |
2575 | Value *Op = I->getOperand(0); | |
2576 | ||
2577 | EVT SrcVT, DestVT; | |
2578 | SrcVT = TLI.getValueType(Op->getType(), true); | |
2579 | DestVT = TLI.getValueType(I->getType(), true); | |
2580 | ||
2581 | if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) | |
2582 | return false; | |
2583 | if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) | |
2584 | return false; | |
2585 | ||
2586 | unsigned SrcReg = getRegForValue(Op); | |
2587 | if (!SrcReg) return false; | |
2588 | ||
2589 | // Because the high bits are undefined, a truncate doesn't generate | |
2590 | // any code. | |
1a4d82fc | 2591 | updateValueMap(I, SrcReg); |
223e47cc LB |
2592 | return true; |
2593 | } | |
2594 | ||
970d7e83 | 2595 | unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, |
223e47cc LB |
2596 | bool isZExt) { |
2597 | if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) | |
2598 | return 0; | |
1a4d82fc JJ |
2599 | if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1) |
2600 | return 0; | |
223e47cc | 2601 | |
1a4d82fc JJ |
2602 | // Table of which combinations can be emitted as a single instruction, |
2603 | // and which will require two. | |
2604 | static const uint8_t isSingleInstrTbl[3][2][2][2] = { | |
2605 | // ARM Thumb | |
2606 | // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops | |
2607 | // ext: s z s z s z s z | |
2608 | /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } }, | |
2609 | /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }, | |
2610 | /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } } | |
2611 | }; | |
2612 | ||
2613 | // Target registers for: | |
2614 | // - For ARM can never be PC. | |
2615 | // - For 16-bit Thumb are restricted to lower 8 registers. | |
2616 | // - For 32-bit Thumb are restricted to non-SP and non-PC. | |
2617 | static const TargetRegisterClass *RCTbl[2][2] = { | |
2618 | // Instructions: Two Single | |
2619 | /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass }, | |
2620 | /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass } | |
2621 | }; | |
2622 | ||
2623 | // Table governing the instruction(s) to be emitted. | |
2624 | static const struct InstructionTable { | |
2625 | uint32_t Opc : 16; | |
2626 | uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0. | |
2627 | uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. | |
2628 | uint32_t Imm : 8; // All instructions have either a shift or a mask. | |
2629 | } IT[2][2][3][2] = { | |
2630 | { // Two instructions (first is left shift, second is in this table). | |
2631 | { // ARM Opc S Shift Imm | |
2632 | /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, | |
2633 | /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } }, | |
2634 | /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, | |
2635 | /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } }, | |
2636 | /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, | |
2637 | /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } } | |
2638 | }, | |
2639 | { // Thumb Opc S Shift Imm | |
2640 | /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, | |
2641 | /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, | |
2642 | /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, | |
2643 | /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, | |
2644 | /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, | |
2645 | /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } | |
2646 | } | |
2647 | }, | |
2648 | { // Single instruction. | |
2649 | { // ARM Opc S Shift Imm | |
2650 | /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, | |
2651 | /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, | |
2652 | /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, | |
2653 | /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, | |
2654 | /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, | |
2655 | /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } | |
2656 | }, | |
2657 | { // Thumb Opc S Shift Imm | |
2658 | /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, | |
2659 | /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } }, | |
2660 | /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 }, | |
2661 | /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } }, | |
2662 | /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 }, | |
2663 | /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } } | |
2664 | } | |
223e47cc | 2665 | } |
1a4d82fc JJ |
2666 | }; |
2667 | ||
2668 | unsigned SrcBits = SrcVT.getSizeInBits(); | |
2669 | unsigned DestBits = DestVT.getSizeInBits(); | |
2670 | (void) DestBits; | |
2671 | assert((SrcBits < DestBits) && "can only extend to larger types"); | |
2672 | assert((DestBits == 32 || DestBits == 16 || DestBits == 8) && | |
2673 | "other sizes unimplemented"); | |
2674 | assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) && | |
2675 | "other sizes unimplemented"); | |
2676 | ||
2677 | bool hasV6Ops = Subtarget->hasV6Ops(); | |
2678 | unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2} | |
2679 | assert((Bitness < 3) && "sanity-check table bounds"); | |
2680 | ||
2681 | bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; | |
2682 | const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; | |
2683 | const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt]; | |
2684 | unsigned Opc = ITP->Opc; | |
2685 | assert(ARM::KILL != Opc && "Invalid table entry"); | |
2686 | unsigned hasS = ITP->hasS; | |
2687 | ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; | |
2688 | assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && | |
2689 | "only MOVsi has shift operand addressing mode"); | |
2690 | unsigned Imm = ITP->Imm; | |
2691 | ||
2692 | // 16-bit Thumb instructions always set CPSR (unless they're in an IT block). | |
2693 | bool setsCPSR = &ARM::tGPRRegClass == RC; | |
2694 | unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi; | |
2695 | unsigned ResultReg; | |
2696 | // MOVsi encodes shift and immediate in shift operand addressing mode. | |
2697 | // The following condition has the same value when emitting two | |
2698 | // instruction sequences: both are shifts. | |
2699 | bool ImmIsSO = (Shift != ARM_AM::no_shift); | |
2700 | ||
2701 | // Either one or two instructions are emitted. | |
2702 | // They're always of the form: | |
2703 | // dst = in OP imm | |
2704 | // CPSR is set only by 16-bit Thumb instructions. | |
2705 | // Predicate, if any, is AL. | |
2706 | // S bit, if available, is always 0. | |
2707 | // When two are emitted the first's result will feed as the second's input, | |
2708 | // that value is then dead. | |
2709 | unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2; | |
2710 | for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) { | |
2711 | ResultReg = createResultReg(RC); | |
2712 | bool isLsl = (0 == Instr) && !isSingleInstr; | |
2713 | unsigned Opcode = isLsl ? LSLOpc : Opc; | |
2714 | ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; | |
2715 | unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm; | |
2716 | bool isKill = 1 == Instr; | |
2717 | MachineInstrBuilder MIB = BuildMI( | |
2718 | *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); | |
2719 | if (setsCPSR) | |
2720 | MIB.addReg(ARM::CPSR, RegState::Define); | |
2721 | SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR); | |
2722 | AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc)); | |
2723 | if (hasS) | |
2724 | AddDefaultCC(MIB); | |
2725 | // Second instruction consumes the first's result. | |
2726 | SrcReg = ResultReg; | |
223e47cc LB |
2727 | } |
2728 | ||
223e47cc LB |
2729 | return ResultReg; |
2730 | } | |
2731 | ||
2732 | bool ARMFastISel::SelectIntExt(const Instruction *I) { | |
2733 | // On ARM, in general, integer casts don't involve legal types; this code | |
2734 | // handles promotable integers. | |
2735 | Type *DestTy = I->getType(); | |
2736 | Value *Src = I->getOperand(0); | |
2737 | Type *SrcTy = Src->getType(); | |
2738 | ||
223e47cc LB |
2739 | bool isZExt = isa<ZExtInst>(I); |
2740 | unsigned SrcReg = getRegForValue(Src); | |
2741 | if (!SrcReg) return false; | |
2742 | ||
970d7e83 LB |
2743 | EVT SrcEVT, DestEVT; |
2744 | SrcEVT = TLI.getValueType(SrcTy, true); | |
2745 | DestEVT = TLI.getValueType(DestTy, true); | |
2746 | if (!SrcEVT.isSimple()) return false; | |
2747 | if (!DestEVT.isSimple()) return false; | |
2748 | ||
2749 | MVT SrcVT = SrcEVT.getSimpleVT(); | |
2750 | MVT DestVT = DestEVT.getSimpleVT(); | |
223e47cc LB |
2751 | unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); |
2752 | if (ResultReg == 0) return false; | |
1a4d82fc | 2753 | updateValueMap(I, ResultReg); |
223e47cc LB |
2754 | return true; |
2755 | } | |
2756 | ||
2757 | bool ARMFastISel::SelectShift(const Instruction *I, | |
2758 | ARM_AM::ShiftOpc ShiftTy) { | |
2759 | // We handle thumb2 mode by target independent selector | |
2760 | // or SelectionDAG ISel. | |
2761 | if (isThumb2) | |
2762 | return false; | |
2763 | ||
2764 | // Only handle i32 now. | |
2765 | EVT DestVT = TLI.getValueType(I->getType(), true); | |
2766 | if (DestVT != MVT::i32) | |
2767 | return false; | |
2768 | ||
2769 | unsigned Opc = ARM::MOVsr; | |
2770 | unsigned ShiftImm; | |
2771 | Value *Src2Value = I->getOperand(1); | |
2772 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) { | |
2773 | ShiftImm = CI->getZExtValue(); | |
2774 | ||
2775 | // Fall back to selection DAG isel if the shift amount | |
2776 | // is zero or greater than the width of the value type. | |
2777 | if (ShiftImm == 0 || ShiftImm >=32) | |
2778 | return false; | |
2779 | ||
2780 | Opc = ARM::MOVsi; | |
2781 | } | |
2782 | ||
2783 | Value *Src1Value = I->getOperand(0); | |
2784 | unsigned Reg1 = getRegForValue(Src1Value); | |
2785 | if (Reg1 == 0) return false; | |
2786 | ||
2787 | unsigned Reg2 = 0; | |
2788 | if (Opc == ARM::MOVsr) { | |
2789 | Reg2 = getRegForValue(Src2Value); | |
2790 | if (Reg2 == 0) return false; | |
2791 | } | |
2792 | ||
1a4d82fc | 2793 | unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); |
223e47cc LB |
2794 | if(ResultReg == 0) return false; |
2795 | ||
1a4d82fc | 2796 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
223e47cc LB |
2797 | TII.get(Opc), ResultReg) |
2798 | .addReg(Reg1); | |
2799 | ||
2800 | if (Opc == ARM::MOVsi) | |
2801 | MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); | |
2802 | else if (Opc == ARM::MOVsr) { | |
2803 | MIB.addReg(Reg2); | |
2804 | MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); | |
2805 | } | |
2806 | ||
2807 | AddOptionalDefs(MIB); | |
1a4d82fc | 2808 | updateValueMap(I, ResultReg); |
223e47cc LB |
2809 | return true; |
2810 | } | |
2811 | ||
2812 | // TODO: SoftFP support. | |
1a4d82fc | 2813 | bool ARMFastISel::fastSelectInstruction(const Instruction *I) { |
223e47cc LB |
2814 | |
2815 | switch (I->getOpcode()) { | |
2816 | case Instruction::Load: | |
2817 | return SelectLoad(I); | |
2818 | case Instruction::Store: | |
2819 | return SelectStore(I); | |
2820 | case Instruction::Br: | |
2821 | return SelectBranch(I); | |
2822 | case Instruction::IndirectBr: | |
2823 | return SelectIndirectBr(I); | |
2824 | case Instruction::ICmp: | |
2825 | case Instruction::FCmp: | |
2826 | return SelectCmp(I); | |
2827 | case Instruction::FPExt: | |
2828 | return SelectFPExt(I); | |
2829 | case Instruction::FPTrunc: | |
2830 | return SelectFPTrunc(I); | |
2831 | case Instruction::SIToFP: | |
2832 | return SelectIToFP(I, /*isSigned*/ true); | |
2833 | case Instruction::UIToFP: | |
2834 | return SelectIToFP(I, /*isSigned*/ false); | |
2835 | case Instruction::FPToSI: | |
2836 | return SelectFPToI(I, /*isSigned*/ true); | |
2837 | case Instruction::FPToUI: | |
2838 | return SelectFPToI(I, /*isSigned*/ false); | |
2839 | case Instruction::Add: | |
2840 | return SelectBinaryIntOp(I, ISD::ADD); | |
2841 | case Instruction::Or: | |
2842 | return SelectBinaryIntOp(I, ISD::OR); | |
2843 | case Instruction::Sub: | |
2844 | return SelectBinaryIntOp(I, ISD::SUB); | |
2845 | case Instruction::FAdd: | |
2846 | return SelectBinaryFPOp(I, ISD::FADD); | |
2847 | case Instruction::FSub: | |
2848 | return SelectBinaryFPOp(I, ISD::FSUB); | |
2849 | case Instruction::FMul: | |
2850 | return SelectBinaryFPOp(I, ISD::FMUL); | |
2851 | case Instruction::SDiv: | |
2852 | return SelectDiv(I, /*isSigned*/ true); | |
2853 | case Instruction::UDiv: | |
2854 | return SelectDiv(I, /*isSigned*/ false); | |
2855 | case Instruction::SRem: | |
2856 | return SelectRem(I, /*isSigned*/ true); | |
2857 | case Instruction::URem: | |
2858 | return SelectRem(I, /*isSigned*/ false); | |
2859 | case Instruction::Call: | |
2860 | if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) | |
2861 | return SelectIntrinsicCall(*II); | |
2862 | return SelectCall(I); | |
2863 | case Instruction::Select: | |
2864 | return SelectSelect(I); | |
2865 | case Instruction::Ret: | |
2866 | return SelectRet(I); | |
2867 | case Instruction::Trunc: | |
2868 | return SelectTrunc(I); | |
2869 | case Instruction::ZExt: | |
2870 | case Instruction::SExt: | |
2871 | return SelectIntExt(I); | |
2872 | case Instruction::Shl: | |
2873 | return SelectShift(I, ARM_AM::lsl); | |
2874 | case Instruction::LShr: | |
2875 | return SelectShift(I, ARM_AM::lsr); | |
2876 | case Instruction::AShr: | |
2877 | return SelectShift(I, ARM_AM::asr); | |
2878 | default: break; | |
2879 | } | |
2880 | return false; | |
2881 | } | |
2882 | ||
1a4d82fc JJ |
2883 | namespace { |
2884 | // This table describes sign- and zero-extend instructions which can be | |
2885 | // folded into a preceding load. All of these extends have an immediate | |
2886 | // (sometimes a mask and sometimes a shift) that's applied after | |
2887 | // extension. | |
2888 | const struct FoldableLoadExtendsStruct { | |
2889 | uint16_t Opc[2]; // ARM, Thumb. | |
2890 | uint8_t ExpectedImm; | |
2891 | uint8_t isZExt : 1; | |
2892 | uint8_t ExpectedVT : 7; | |
2893 | } FoldableLoadExtends[] = { | |
2894 | { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 }, | |
2895 | { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 }, | |
2896 | { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 }, | |
2897 | { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 }, | |
2898 | { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 } | |
2899 | }; | |
2900 | } | |
2901 | ||
2902 | /// \brief The specified machine instr operand is a vreg, and that | |
223e47cc LB |
2903 | /// vreg is being provided by the specified load instruction. If possible, |
2904 | /// try to fold the load as an operand to the instruction, returning true if | |
2905 | /// successful. | |
1a4d82fc JJ |
2906 | bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, |
2907 | const LoadInst *LI) { | |
223e47cc LB |
2908 | // Verify we have a legal type before going any further. |
2909 | MVT VT; | |
2910 | if (!isLoadTypeLegal(LI->getType(), VT)) | |
2911 | return false; | |
2912 | ||
2913 | // Combine load followed by zero- or sign-extend. | |
2914 | // ldrb r1, [r0] ldrb r1, [r0] | |
2915 | // uxtb r2, r1 => | |
2916 | // mov r3, r2 mov r3, r1 | |
1a4d82fc JJ |
2917 | if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm()) |
2918 | return false; | |
2919 | const uint64_t Imm = MI->getOperand(2).getImm(); | |
2920 | ||
2921 | bool Found = false; | |
2922 | bool isZExt; | |
2923 | for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends); | |
2924 | i != e; ++i) { | |
2925 | if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() && | |
2926 | (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm && | |
2927 | MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) { | |
2928 | Found = true; | |
2929 | isZExt = FoldableLoadExtends[i].isZExt; | |
2930 | } | |
223e47cc | 2931 | } |
1a4d82fc JJ |
2932 | if (!Found) return false; |
2933 | ||
223e47cc LB |
2934 | // See if we can handle this address. |
2935 | Address Addr; | |
2936 | if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false; | |
2937 | ||
2938 | unsigned ResultReg = MI->getOperand(0).getReg(); | |
2939 | if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) | |
2940 | return false; | |
2941 | MI->eraseFromParent(); | |
2942 | return true; | |
2943 | } | |
2944 | ||
2945 | unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, | |
970d7e83 | 2946 | unsigned Align, MVT VT) { |
223e47cc LB |
2947 | bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); |
2948 | ARMConstantPoolConstant *CPV = | |
2949 | ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); | |
2950 | unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); | |
2951 | ||
2952 | unsigned Opc; | |
2953 | unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT)); | |
2954 | // Load value. | |
2955 | if (isThumb2) { | |
1a4d82fc JJ |
2956 | DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0); |
2957 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | |
223e47cc LB |
2958 | TII.get(ARM::t2LDRpci), DestReg1) |
2959 | .addConstantPoolIndex(Idx)); | |
2960 | Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs; | |
2961 | } else { | |
2962 | // The extra immediate is for addrmode2. | |
1a4d82fc | 2963 | DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0); |
223e47cc | 2964 | AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, |
1a4d82fc | 2965 | DbgLoc, TII.get(ARM::LDRcp), DestReg1) |
223e47cc LB |
2966 | .addConstantPoolIndex(Idx).addImm(0)); |
2967 | Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs; | |
2968 | } | |
2969 | ||
2970 | unsigned GlobalBaseReg = AFI->getGlobalBaseReg(); | |
2971 | if (GlobalBaseReg == 0) { | |
2972 | GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT)); | |
2973 | AFI->setGlobalBaseReg(GlobalBaseReg); | |
2974 | } | |
2975 | ||
2976 | unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT)); | |
1a4d82fc JJ |
2977 | DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0); |
2978 | DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1); | |
2979 | GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2); | |
223e47cc | 2980 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, |
1a4d82fc | 2981 | DbgLoc, TII.get(Opc), DestReg2) |
223e47cc LB |
2982 | .addReg(DestReg1) |
2983 | .addReg(GlobalBaseReg); | |
2984 | if (!UseGOTOFF) | |
2985 | MIB.addImm(0); | |
2986 | AddOptionalDefs(MIB); | |
2987 | ||
2988 | return DestReg2; | |
2989 | } | |
2990 | ||
1a4d82fc | 2991 | bool ARMFastISel::fastLowerArguments() { |
970d7e83 LB |
2992 | if (!FuncInfo.CanLowerReturn) |
2993 | return false; | |
2994 | ||
2995 | const Function *F = FuncInfo.Fn; | |
2996 | if (F->isVarArg()) | |
2997 | return false; | |
2998 | ||
2999 | CallingConv::ID CC = F->getCallingConv(); | |
3000 | switch (CC) { | |
3001 | default: | |
3002 | return false; | |
3003 | case CallingConv::Fast: | |
3004 | case CallingConv::C: | |
3005 | case CallingConv::ARM_AAPCS_VFP: | |
3006 | case CallingConv::ARM_AAPCS: | |
3007 | case CallingConv::ARM_APCS: | |
3008 | break; | |
3009 | } | |
3010 | ||
3011 | // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments | |
3012 | // which are passed in r0 - r3. | |
3013 | unsigned Idx = 1; | |
3014 | for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); | |
3015 | I != E; ++I, ++Idx) { | |
3016 | if (Idx > 4) | |
3017 | return false; | |
3018 | ||
3019 | if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) || | |
3020 | F->getAttributes().hasAttribute(Idx, Attribute::StructRet) || | |
3021 | F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) | |
3022 | return false; | |
3023 | ||
3024 | Type *ArgTy = I->getType(); | |
3025 | if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) | |
3026 | return false; | |
3027 | ||
3028 | EVT ArgVT = TLI.getValueType(ArgTy); | |
3029 | if (!ArgVT.isSimple()) return false; | |
3030 | switch (ArgVT.getSimpleVT().SimpleTy) { | |
3031 | case MVT::i8: | |
3032 | case MVT::i16: | |
3033 | case MVT::i32: | |
3034 | break; | |
3035 | default: | |
3036 | return false; | |
3037 | } | |
3038 | } | |
3039 | ||
3040 | ||
3041 | static const uint16_t GPRArgRegs[] = { | |
3042 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 | |
3043 | }; | |
3044 | ||
1a4d82fc | 3045 | const TargetRegisterClass *RC = &ARM::rGPRRegClass; |
970d7e83 LB |
3046 | Idx = 0; |
3047 | for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); | |
3048 | I != E; ++I, ++Idx) { | |
970d7e83 LB |
3049 | unsigned SrcReg = GPRArgRegs[Idx]; |
3050 | unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); | |
3051 | // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. | |
3052 | // Without this, EmitLiveInCopies may eliminate the livein if its only | |
3053 | // use is a bitcast (which isn't turned into an instruction). | |
3054 | unsigned ResultReg = createResultReg(RC); | |
1a4d82fc JJ |
3055 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
3056 | TII.get(TargetOpcode::COPY), | |
970d7e83 | 3057 | ResultReg).addReg(DstReg, getKillRegState(true)); |
1a4d82fc | 3058 | updateValueMap(I, ResultReg); |
970d7e83 LB |
3059 | } |
3060 | ||
3061 | return true; | |
3062 | } | |
3063 | ||
223e47cc LB |
3064 | namespace llvm { |
3065 | FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, | |
970d7e83 | 3066 | const TargetLibraryInfo *libInfo) { |
223e47cc LB |
3067 | const TargetMachine &TM = funcInfo.MF->getTarget(); |
3068 | ||
223e47cc | 3069 | const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>(); |
1a4d82fc JJ |
3070 | // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl. |
3071 | bool UseFastISel = false; | |
3072 | UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only(); | |
3073 | UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb(); | |
3074 | UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb(); | |
3075 | ||
3076 | if (UseFastISel) { | |
3077 | // iOS always has a FP for backtracking, force other targets | |
3078 | // to keep their FP when doing FastISel. The emitted code is | |
3079 | // currently superior, and in cases like test-suite's lencod | |
3080 | // FastISel isn't quite correct when FP is eliminated. | |
3081 | TM.Options.NoFramePointerElim = true; | |
970d7e83 | 3082 | return new ARMFastISel(funcInfo, libInfo); |
1a4d82fc JJ |
3083 | } |
3084 | return nullptr; | |
223e47cc LB |
3085 | } |
3086 | } |