]> git.proxmox.com Git - rustc.git/blame - src/llvm/lib/Target/ARM/ARMInstrInfo.td
projects / rustc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Imported Upstream version 1.0.0+dfsg1
[rustc.git] / src / llvm / lib / Target / ARM / ARMInstrInfo.td
CommitLineData
223e47cc
LB		 1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// ARM specific DAG Nodes.
16//
17
18// Type profiles.
19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
24
25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
26
27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
28
29def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
31 SDTCisVT<3, i32>]>;
32
33def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
35
36def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
38 SDTCisVT<2, i32>]>;
39
40def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
43
44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 [SDTCisVT<0, i32>,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
49
50def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
52 SDTCisVT<2, i32>]>;
53
54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55
56def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58
59def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 SDTCisInt<2>]>;
62def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
63
64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65
66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
67 SDTCisInt<1>]>;
68
69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70
71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73
1a4d82fc
JJ		 74def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
76
223e47cc
LB		 77def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
78 [SDTCisSameAs<0, 2>,
79 SDTCisSameAs<0, 3>,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
81
82// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 [SDTCisSameAs<0, 2>,
85 SDTCisSameAs<0, 3>,
86 SDTCisInt<0>,
87 SDTCisVT<1, i32>,
88 SDTCisVT<4, i32>]>;
89
90def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
95
96// Node definitions.
97def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
223e47cc
LB		 98def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
100
101def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
107 SDT_ARMStructByVal,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
110
111def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
113 SDNPVariadic]>;
114def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 SDNPVariadic]>;
117def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 SDNPVariadic]>;
120
121def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
970d7e83 122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1a4d82fc
JJ		 123def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
223e47cc
LB		 125def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
126 [SDNPInGlue]>;
127
128def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
130
131def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
132 [SDNPHasChain]>;
133def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
134 [SDNPHasChain]>;
135
136def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
137 [SDNPHasChain]>;
138
139def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
140 [SDNPOutGlue]>;
141
142def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
143 [SDNPOutGlue]>;
144
145def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
147
148def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
149
150def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
153
154def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
155 [SDNPCommutative]>;
156def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
159
160def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167
223e47cc
LB		 168def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172
173def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174
175def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
177
223e47cc
LB		 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
179
1a4d82fc
JJ		 180def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
182
223e47cc
LB		 183//===----------------------------------------------------------------------===//
184// ARM Instruction Predicate Definitions.
185//
186def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
1a4d82fc
JJ		 189def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
223e47cc
LB		 191def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
1a4d82fc
JJ		 196def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
223e47cc
LB		 199def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
1a4d82fc
JJ		 204def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
223e47cc
LB		 208def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
1a4d82fc
JJ		 215def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
216 AssemblerPredicate<"!FeatureVFPOnlySP",
217 "double precision VFP">;
218def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
223e47cc
LB		 220def HasNEON : Predicate<"Subtarget->hasNEON()">,
221 AssemblerPredicate<"FeatureNEON", "NEON">;
1a4d82fc
JJ		 222def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
223 AssemblerPredicate<"FeatureCrypto", "crypto">;
224def HasCRC : Predicate<"Subtarget->hasCRC()">,
225 AssemblerPredicate<"FeatureCRC", "crc">;
223e47cc
LB		 226def HasFP16 : Predicate<"Subtarget->hasFP16()">,
227 AssemblerPredicate<"FeatureFP16","half-float">;
228def HasDivide : Predicate<"Subtarget->hasDivide()">,
1a4d82fc 229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
223e47cc 230def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
1a4d82fc 231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
223e47cc
LB		 232def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
233 AssemblerPredicate<"FeatureT2XtPk",
234 "pack/extract">;
235def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
236 AssemblerPredicate<"FeatureDSPThumb2",
237 "thumb2-dsp">;
238def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
239 AssemblerPredicate<"FeatureDB",
240 "data-barriers">;
241def HasMP : Predicate<"Subtarget->hasMPExtension()">,
242 AssemblerPredicate<"FeatureMP",
243 "mp-extensions">;
1a4d82fc
JJ		 244def HasVirtualization: Predicate<"false">,
245 AssemblerPredicate<"FeatureVirtualization",
246 "virtualization-extensions">;
247def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
248 AssemblerPredicate<"FeatureTrustZone",
249 "TrustZone">;
250def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
223e47cc
LB		 251def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
252def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
253def IsThumb : Predicate<"Subtarget->isThumb()">,
254 AssemblerPredicate<"ModeThumb", "thumb">;
255def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
256def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
257 AssemblerPredicate<"ModeThumb,FeatureThumb2",
258 "thumb2">;
259def IsMClass : Predicate<"Subtarget->isMClass()">,
1a4d82fc
JJ		 260 AssemblerPredicate<"FeatureMClass", "armv*m">;
261def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
223e47cc 262 AssemblerPredicate<"!FeatureMClass",
1a4d82fc 263 "!armv*m">;
223e47cc
LB		 264def IsARM : Predicate<"!Subtarget->isThumb()">,
265 AssemblerPredicate<"!ModeThumb", "arm-mode">;
1a4d82fc
JJ		 266def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
267def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
223e47cc 268def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
970d7e83
LB		 269def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
270 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
271def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
223e47cc
LB		 272
273// FIXME: Eventually this will be just "hasV6T2Ops".
1a4d82fc
JJ		 274def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
275def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
223e47cc
LB		 276def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
277def UseMulOps : Predicate<"Subtarget->useMulOps()">;
278
279// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
280// But only select them if more precision in FP computation is allowed.
281// Do not use them for Darwin platforms.
282def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
1a4d82fc
JJ		 283 " FPOpFusion::Fast && "
284 " Subtarget->hasVFP4()) && "
223e47cc 285 "!Subtarget->isTargetDarwin()">;
1a4d82fc
JJ		 286def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
287 " FPOpFusion::Fast &&"
288 " Subtarget->hasVFP4()) || "
223e47cc
LB		 289 "Subtarget->isTargetDarwin()">;
290
291// VGETLNi32 is microcoded on Swift - prefer VMOV.
292def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
293def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
294
295// VDUP.32 is microcoded on Swift - prefer VMOV.
296def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
297def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
298
299// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
300// this allows more effective execution domain optimization. See
301// setExecutionDomain().
302def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
303def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
304
1a4d82fc
JJ		 305def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
306def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
223e47cc
LB		 307
308//===----------------------------------------------------------------------===//
309// ARM Flag Definitions.
310
311class RegConstraint<string C> {
312 string Constraints = C;
313}
314
315//===----------------------------------------------------------------------===//
316// ARM specific transformation functions and pattern fragments.
317//
318
970d7e83 319// imm_neg_XFORM - Return the negation of an i32 immediate value.
223e47cc
LB		 320def imm_neg_XFORM : SDNodeXForm<imm, [{
321 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
322}]>;
323
970d7e83
LB		 324// imm_not_XFORM - Return the complement of a i32 immediate value.
325def imm_not_XFORM : SDNodeXForm<imm, [{
223e47cc
LB		 326 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
327}]>;
328
329/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
330def imm16_31 : ImmLeaf<i32, [{
331 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
332}]>;
333
223e47cc
LB		 334// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
335def sext_16_node : PatLeaf<(i32 GPR:$a), [{
336 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
337}]>;
338
339/// Split a 32-bit immediate into two 16 bit parts.
340def hi16 : SDNodeXForm<imm, [{
341 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
342}]>;
343
344def lo16AllZero : PatLeaf<(i32 imm), [{
345 // Returns true if all low 16-bits are 0.
346 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
347}], hi16>;
348
349class BinOpWithFlagFrag<dag res> :
350 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
351class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
352class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
353
354// An 'and' node with a single use.
355def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
356 return N->hasOneUse();
357}]>;
358
359// An 'xor' node with a single use.
360def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
361 return N->hasOneUse();
362}]>;
363
364// An 'fmul' node with a single use.
365def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
366 return N->hasOneUse();
367}]>;
368
369// An 'fadd' node which checks for single non-hazardous use.
370def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
371 return hasNoVMLxHazardUse(N);
372}]>;
373
374// An 'fsub' node which checks for single non-hazardous use.
375def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
376 return hasNoVMLxHazardUse(N);
377}]>;
378
379//===----------------------------------------------------------------------===//
380// Operand Definitions.
381//
382
383// Immediate operands with a shared generic asm render method.
384class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
385
386// Branch target.
387// FIXME: rename brtarget to t2_brtarget
388def brtarget : Operand<OtherVT> {
389 let EncoderMethod = "getBranchTargetOpValue";
390 let OperandType = "OPERAND_PCREL";
391 let DecoderMethod = "DecodeT2BROperand";
392}
393
394// FIXME: get rid of this one?
395def uncondbrtarget : Operand<OtherVT> {
396 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
397 let OperandType = "OPERAND_PCREL";
398}
399
400// Branch target for ARM. Handles conditional/unconditional
401def br_target : Operand<OtherVT> {
402 let EncoderMethod = "getARMBranchTargetOpValue";
403 let OperandType = "OPERAND_PCREL";
404}
405
406// Call target.
407// FIXME: rename bltarget to t2_bl_target?
408def bltarget : Operand<i32> {
409 // Encoded the same as branch targets.
410 let EncoderMethod = "getBranchTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
412}
413
414// Call target for ARM. Handles conditional/unconditional
415// FIXME: rename bl_target to t2_bltarget?
416def bl_target : Operand<i32> {
417 let EncoderMethod = "getARMBLTargetOpValue";
418 let OperandType = "OPERAND_PCREL";
419}
420
421def blx_target : Operand<i32> {
422 let EncoderMethod = "getARMBLXTargetOpValue";
423 let OperandType = "OPERAND_PCREL";
424}
425
426// A list of registers separated by comma. Used by load/store multiple.
427def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
428def reglist : Operand<i32> {
429 let EncoderMethod = "getRegisterListOpValue";
430 let ParserMatchClass = RegListAsmOperand;
431 let PrintMethod = "printRegisterList";
432 let DecoderMethod = "DecodeRegListOperand";
433}
434
970d7e83
LB		 435def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
436
223e47cc
LB		 437def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
438def dpr_reglist : Operand<i32> {
439 let EncoderMethod = "getRegisterListOpValue";
440 let ParserMatchClass = DPRRegListAsmOperand;
441 let PrintMethod = "printRegisterList";
442 let DecoderMethod = "DecodeDPRRegListOperand";
443}
444
445def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
446def spr_reglist : Operand<i32> {
447 let EncoderMethod = "getRegisterListOpValue";
448 let ParserMatchClass = SPRRegListAsmOperand;
449 let PrintMethod = "printRegisterList";
450 let DecoderMethod = "DecodeSPRRegListOperand";
451}
452
453// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
454def cpinst_operand : Operand<i32> {
455 let PrintMethod = "printCPInstOperand";
456}
457
458// Local PC labels.
459def pclabel : Operand<i32> {
460 let PrintMethod = "printPCLabel";
461}
462
463// ADR instruction labels.
464def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
465def adrlabel : Operand<i32> {
466 let EncoderMethod = "getAdrLabelOpValue";
467 let ParserMatchClass = AdrLabelAsmOperand;
1a4d82fc 468 let PrintMethod = "printAdrLabelOperand<0>";
223e47cc
LB		 469}
470
471def neon_vcvt_imm32 : Operand<i32> {
472 let EncoderMethod = "getNEONVcvtImm32OpValue";
473 let DecoderMethod = "DecodeVCVTImmOperand";
474}
475
476// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
477def rot_imm_XFORM: SDNodeXForm<imm, [{
478 switch (N->getZExtValue()){
1a4d82fc 479 default: llvm_unreachable(nullptr);
223e47cc
LB		 480 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
481 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
482 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
483 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
484 }
485}]>;
486def RotImmAsmOperand : AsmOperandClass {
487 let Name = "RotImm";
488 let ParserMethod = "parseRotImm";
489}
490def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
491 int32_t v = N->getZExtValue();
492 return v == 8 || v == 16 || v == 24; }],
493 rot_imm_XFORM> {
494 let PrintMethod = "printRotImmOperand";
495 let ParserMatchClass = RotImmAsmOperand;
496}
497
498// shift_imm: An integer that encodes a shift amount and the type of shift
499// (asr or lsl). The 6-bit immediate encodes as:
500// {5} 0 ==> lsl
501// 1 asr
502// {4-0} imm5 shift amount.
503// asr #32 encoded as imm5 == 0.
504def ShifterImmAsmOperand : AsmOperandClass {
505 let Name = "ShifterImm";
506 let ParserMethod = "parseShifterImm";
507}
508def shift_imm : Operand<i32> {
509 let PrintMethod = "printShiftImmOperand";
510 let ParserMatchClass = ShifterImmAsmOperand;
511}
512
85aaf69f 513// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
223e47cc
LB		 514def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
515def so_reg_reg : Operand<i32>, // reg reg imm
516 ComplexPattern<i32, 3, "SelectRegShifterOperand",
517 [shl, srl, sra, rotr]> {
518 let EncoderMethod = "getSORegRegOpValue";
519 let PrintMethod = "printSORegRegOperand";
520 let DecoderMethod = "DecodeSORegRegOperand";
521 let ParserMatchClass = ShiftedRegAsmOperand;
522 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
523}
524
525def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
526def so_reg_imm : Operand<i32>, // reg imm
527 ComplexPattern<i32, 2, "SelectImmShifterOperand",
528 [shl, srl, sra, rotr]> {
529 let EncoderMethod = "getSORegImmOpValue";
530 let PrintMethod = "printSORegImmOperand";
531 let DecoderMethod = "DecodeSORegImmOperand";
532 let ParserMatchClass = ShiftedImmAsmOperand;
533 let MIOperandInfo = (ops GPR, i32imm);
534}
535
536// FIXME: Does this need to be distinct from so_reg?
537def shift_so_reg_reg : Operand<i32>, // reg reg imm
538 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
539 [shl,srl,sra,rotr]> {
540 let EncoderMethod = "getSORegRegOpValue";
541 let PrintMethod = "printSORegRegOperand";
542 let DecoderMethod = "DecodeSORegRegOperand";
543 let ParserMatchClass = ShiftedRegAsmOperand;
544 let MIOperandInfo = (ops GPR, GPR, i32imm);
545}
546
547// FIXME: Does this need to be distinct from so_reg?
548def shift_so_reg_imm : Operand<i32>, // reg reg imm
549 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
550 [shl,srl,sra,rotr]> {
551 let EncoderMethod = "getSORegImmOpValue";
552 let PrintMethod = "printSORegImmOperand";
553 let DecoderMethod = "DecodeSORegImmOperand";
554 let ParserMatchClass = ShiftedImmAsmOperand;
555 let MIOperandInfo = (ops GPR, i32imm);
556}
557
85aaf69f
SL		 558// mod_imm: match a 32-bit immediate operand, which can be encoded into
559// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
560// - "Modified Immediate Constants"). Within the MC layer we keep this
561// immediate in its encoded form.
562def ModImmAsmOperand: AsmOperandClass {
563 let Name = "ModImm";
564 let ParserMethod = "parseModImm";
565}
566def mod_imm : Operand<i32>, ImmLeaf<i32, [{
223e47cc
LB		 567 return ARM_AM::getSOImmVal(Imm) != -1;
568 }]> {
85aaf69f
SL		 569 let EncoderMethod = "getModImmOpValue";
570 let PrintMethod = "printModImmOperand";
571 let ParserMatchClass = ModImmAsmOperand;
223e47cc
LB		 572}
573
85aaf69f
SL		 574// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
575// method and such, as they are only used on aliases (Pat<> and InstAlias<>).
576// The actual parsing, encoding, decoding are handled by the destination
577// instructions, which use mod_imm.
223e47cc 578
85aaf69f
SL		 579def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
580def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
581 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
582 }], imm_not_XFORM> {
583 let ParserMatchClass = ModImmNotAsmOperand;
584}
585
586def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
587def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
588 unsigned Value = -(unsigned)N->getZExtValue();
589 return Value && ARM_AM::getSOImmVal(Value) != -1;
590 }], imm_neg_XFORM> {
591 let ParserMatchClass = ModImmNegAsmOperand;
592}
593
594/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
223e47cc 595def arm_i32imm : PatLeaf<(imm), [{
1a4d82fc 596 if (Subtarget->useMovt(*MF))
223e47cc
LB		 597 return true;
598 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
599}]>;
600
601/// imm0_1 predicate - Immediate in the range [0,1].
602def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
603def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
604
605/// imm0_3 predicate - Immediate in the range [0,3].
606def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
607def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
608
609/// imm0_7 predicate - Immediate in the range [0,7].
610def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
611def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
612 return Imm >= 0 && Imm < 8;
613}]> {
614 let ParserMatchClass = Imm0_7AsmOperand;
615}
616
617/// imm8 predicate - Immediate is exactly 8.
618def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
619def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
620 let ParserMatchClass = Imm8AsmOperand;
621}
622
623/// imm16 predicate - Immediate is exactly 16.
624def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
625def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
626 let ParserMatchClass = Imm16AsmOperand;
627}
628
629/// imm32 predicate - Immediate is exactly 32.
630def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
631def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
632 let ParserMatchClass = Imm32AsmOperand;
633}
634
1a4d82fc
JJ		 635def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
636
223e47cc
LB		 637/// imm1_7 predicate - Immediate in the range [1,7].
638def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
639def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
640 let ParserMatchClass = Imm1_7AsmOperand;
641}
642
643/// imm1_15 predicate - Immediate in the range [1,15].
644def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
645def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
646 let ParserMatchClass = Imm1_15AsmOperand;
647}
648
649/// imm1_31 predicate - Immediate in the range [1,31].
650def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
651def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
652 let ParserMatchClass = Imm1_31AsmOperand;
653}
654
655/// imm0_15 predicate - Immediate in the range [0,15].
656def Imm0_15AsmOperand: ImmAsmOperand {
657 let Name = "Imm0_15";
658 let DiagnosticType = "ImmRange0_15";
659}
660def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
661 return Imm >= 0 && Imm < 16;
662}]> {
663 let ParserMatchClass = Imm0_15AsmOperand;
664}
665
666/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
667def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
668def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 32;
670}]> {
671 let ParserMatchClass = Imm0_31AsmOperand;
672}
673
674/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
675def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
676def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 32;
678}]> {
679 let ParserMatchClass = Imm0_32AsmOperand;
680}
681
682/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
683def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
684def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 64;
686}]> {
687 let ParserMatchClass = Imm0_63AsmOperand;
688}
689
1a4d82fc
JJ		 690/// imm0_239 predicate - Immediate in the range [0,239].
691def Imm0_239AsmOperand : ImmAsmOperand {
692 let Name = "Imm0_239";
693 let DiagnosticType = "ImmRange0_239";
694}
695def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
696 let ParserMatchClass = Imm0_239AsmOperand;
697}
698
223e47cc
LB		 699/// imm0_255 predicate - Immediate in the range [0,255].
700def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
701def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
702 let ParserMatchClass = Imm0_255AsmOperand;
703}
704
705/// imm0_65535 - An immediate is in the range [0.65535].
706def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
707def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
708 return Imm >= 0 && Imm < 65536;
709}]> {
710 let ParserMatchClass = Imm0_65535AsmOperand;
711}
712
713// imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
714def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
715 return -Imm >= 0 && -Imm < 65536;
716}]>;
717
718// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
719// a relocatable expression.
720//
721// FIXME: This really needs a Thumb version separate from the ARM version.
722// While the range is the same, and can thus use the same match class,
723// the encoding is different so it should have a different encoder method.
724def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
725def imm0_65535_expr : Operand<i32> {
726 let EncoderMethod = "getHiLo16ImmOpValue";
727 let ParserMatchClass = Imm0_65535ExprAsmOperand;
728}
729
1a4d82fc
JJ		 730def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
731def imm256_65535_expr : Operand<i32> {
732 let ParserMatchClass = Imm256_65535ExprAsmOperand;
733}
734
223e47cc
LB		 735/// imm24b - True if the 32-bit immediate is encodable in 24 bits.
736def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
737def imm24b : Operand<i32>, ImmLeaf<i32, [{
738 return Imm >= 0 && Imm <= 0xffffff;
739}]> {
740 let ParserMatchClass = Imm24bitAsmOperand;
741}
742
743
744/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
745/// e.g., 0xf000ffff
746def BitfieldAsmOperand : AsmOperandClass {
747 let Name = "Bitfield";
748 let ParserMethod = "parseBitfield";
749}
750
751def bf_inv_mask_imm : Operand<i32>,
752 PatLeaf<(imm), [{
753 return ARM::isBitFieldInvertedMask(N->getZExtValue());
754}] > {
755 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
756 let PrintMethod = "printBitfieldInvMaskImmOperand";
757 let DecoderMethod = "DecodeBitfieldMaskOperand";
758 let ParserMatchClass = BitfieldAsmOperand;
759}
760
761def imm1_32_XFORM: SDNodeXForm<imm, [{
762 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
763}]>;
764def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
765def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
766 uint64_t Imm = N->getZExtValue();
767 return Imm > 0 && Imm <= 32;
768 }],
769 imm1_32_XFORM> {
770 let PrintMethod = "printImmPlusOneOperand";
771 let ParserMatchClass = Imm1_32AsmOperand;
772}
773
774def imm1_16_XFORM: SDNodeXForm<imm, [{
775 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
776}]>;
777def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
778def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
779 imm1_16_XFORM> {
780 let PrintMethod = "printImmPlusOneOperand";
781 let ParserMatchClass = Imm1_16AsmOperand;
782}
783
784// Define ARM specific addressing modes.
785// addrmode_imm12 := reg +/- imm12
786//
787def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
1a4d82fc 788class AddrMode_Imm12 : Operand<i32>,
223e47cc
LB		 789 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
790 // 12-bit immediate operand. Note that instructions using this encode
791 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
792 // immediate values are as normal.
793
794 let EncoderMethod = "getAddrModeImm12OpValue";
223e47cc
LB		 795 let DecoderMethod = "DecodeAddrModeImm12Operand";
796 let ParserMatchClass = MemImm12OffsetAsmOperand;
797 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
798}
1a4d82fc
JJ		 799
800def addrmode_imm12 : AddrMode_Imm12 {
801 let PrintMethod = "printAddrModeImm12Operand<false>";
802}
803
804def addrmode_imm12_pre : AddrMode_Imm12 {
805 let PrintMethod = "printAddrModeImm12Operand<true>";
806}
807
223e47cc
LB		 808// ldst_so_reg := reg +/- reg shop imm
809//
810def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
811def ldst_so_reg : Operand<i32>,
812 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
813 let EncoderMethod = "getLdStSORegOpValue";
814 // FIXME: Simplify the printer
815 let PrintMethod = "printAddrMode2Operand";
816 let DecoderMethod = "DecodeSORegMemOperand";
817 let ParserMatchClass = MemRegOffsetAsmOperand;
818 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
819}
820
821// postidx_imm8 := +/- [0,255]
822//
823// 9 bit value:
824// {8} 1 is imm8 is non-negative. 0 otherwise.
825// {7-0} [0,255] imm8 value.
826def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
827def postidx_imm8 : Operand<i32> {
828 let PrintMethod = "printPostIdxImm8Operand";
829 let ParserMatchClass = PostIdxImm8AsmOperand;
830 let MIOperandInfo = (ops i32imm);
831}
832
833// postidx_imm8s4 := +/- [0,1020]
834//
835// 9 bit value:
836// {8} 1 is imm8 is non-negative. 0 otherwise.
837// {7-0} [0,255] imm8 value, scaled by 4.
838def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
839def postidx_imm8s4 : Operand<i32> {
840 let PrintMethod = "printPostIdxImm8s4Operand";
841 let ParserMatchClass = PostIdxImm8s4AsmOperand;
842 let MIOperandInfo = (ops i32imm);
843}
844
845
846// postidx_reg := +/- reg
847//
848def PostIdxRegAsmOperand : AsmOperandClass {
849 let Name = "PostIdxReg";
850 let ParserMethod = "parsePostIdxReg";
851}
852def postidx_reg : Operand<i32> {
853 let EncoderMethod = "getPostIdxRegOpValue";
854 let DecoderMethod = "DecodePostIdxReg";
855 let PrintMethod = "printPostIdxRegOperand";
856 let ParserMatchClass = PostIdxRegAsmOperand;
857 let MIOperandInfo = (ops GPRnopc, i32imm);
858}
859
860
861// addrmode2 := reg +/- imm12
862// := reg +/- reg shop imm
863//
864// FIXME: addrmode2 should be refactored the rest of the way to always
865// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
866def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
867def addrmode2 : Operand<i32>,
868 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
869 let EncoderMethod = "getAddrMode2OpValue";
870 let PrintMethod = "printAddrMode2Operand";
871 let ParserMatchClass = AddrMode2AsmOperand;
872 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
873}
874
875def PostIdxRegShiftedAsmOperand : AsmOperandClass {
876 let Name = "PostIdxRegShifted";
877 let ParserMethod = "parsePostIdxReg";
878}
879def am2offset_reg : Operand<i32>,
880 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
881 [], [SDNPWantRoot]> {
882 let EncoderMethod = "getAddrMode2OffsetOpValue";
883 let PrintMethod = "printAddrMode2OffsetOperand";
884 // When using this for assembly, it's always as a post-index offset.
885 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
886 let MIOperandInfo = (ops GPRnopc, i32imm);
887}
888
889// FIXME: am2offset_imm should only need the immediate, not the GPR. Having
890// the GPR is purely vestigal at this point.
891def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
892def am2offset_imm : Operand<i32>,
893 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
894 [], [SDNPWantRoot]> {
895 let EncoderMethod = "getAddrMode2OffsetOpValue";
896 let PrintMethod = "printAddrMode2OffsetOperand";
897 let ParserMatchClass = AM2OffsetImmAsmOperand;
898 let MIOperandInfo = (ops GPRnopc, i32imm);
899}
900
901
902// addrmode3 := reg +/- reg
903// addrmode3 := reg +/- imm8
904//
905// FIXME: split into imm vs. reg versions.
906def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
1a4d82fc
JJ		 907class AddrMode3 : Operand<i32>,
908 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
223e47cc 909 let EncoderMethod = "getAddrMode3OpValue";
223e47cc
LB		 910 let ParserMatchClass = AddrMode3AsmOperand;
911 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
912}
913
1a4d82fc
JJ		 914def addrmode3 : AddrMode3
915{
916 let PrintMethod = "printAddrMode3Operand<false>";
917}
918
919def addrmode3_pre : AddrMode3
920{
921 let PrintMethod = "printAddrMode3Operand<true>";
922}
923
223e47cc
LB		 924// FIXME: split into imm vs. reg versions.
925// FIXME: parser method to handle +/- register.
926def AM3OffsetAsmOperand : AsmOperandClass {
927 let Name = "AM3Offset";
928 let ParserMethod = "parseAM3Offset";
929}
930def am3offset : Operand<i32>,
931 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
932 [], [SDNPWantRoot]> {
933 let EncoderMethod = "getAddrMode3OffsetOpValue";
934 let PrintMethod = "printAddrMode3OffsetOperand";
935 let ParserMatchClass = AM3OffsetAsmOperand;
936 let MIOperandInfo = (ops GPR, i32imm);
937}
938
939// ldstm_mode := {ia, ib, da, db}
940//
941def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
942 let EncoderMethod = "getLdStmModeOpValue";
943 let PrintMethod = "printLdStmModeOperand";
944}
945
946// addrmode5 := reg +/- imm8*4
947//
948def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
1a4d82fc
JJ		 949class AddrMode5 : Operand<i32>,
950 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
223e47cc
LB		 951 let EncoderMethod = "getAddrMode5OpValue";
952 let DecoderMethod = "DecodeAddrMode5Operand";
953 let ParserMatchClass = AddrMode5AsmOperand;
954 let MIOperandInfo = (ops GPR:$base, i32imm);
955}
956
1a4d82fc
JJ		 957def addrmode5 : AddrMode5 {
958 let PrintMethod = "printAddrMode5Operand<false>";
959}
960
961def addrmode5_pre : AddrMode5 {
962 let PrintMethod = "printAddrMode5Operand<true>";
963}
964
223e47cc
LB		 965// addrmode6 := reg with optional alignment
966//
967def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
968def addrmode6 : Operand<i32>,
969 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
970 let PrintMethod = "printAddrMode6Operand";
971 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
972 let EncoderMethod = "getAddrMode6AddressOpValue";
973 let DecoderMethod = "DecodeAddrMode6Operand";
974 let ParserMatchClass = AddrMode6AsmOperand;
975}
976
977def am6offset : Operand<i32>,
978 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
979 [], [SDNPWantRoot]> {
980 let PrintMethod = "printAddrMode6OffsetOperand";
981 let MIOperandInfo = (ops GPR);
982 let EncoderMethod = "getAddrMode6OffsetOpValue";
983 let DecoderMethod = "DecodeGPRRegisterClass";
984}
985
986// Special version of addrmode6 to handle alignment encoding for VST1/VLD1
987// (single element from one lane) for size 32.
988def addrmode6oneL32 : Operand<i32>,
989 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
990 let PrintMethod = "printAddrMode6Operand";
991 let MIOperandInfo = (ops GPR:$addr, i32imm);
992 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
993}
994
1a4d82fc
JJ		 995// Base class for addrmode6 with specific alignment restrictions.
996class AddrMode6Align : Operand<i32>,
997 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
998 let PrintMethod = "printAddrMode6Operand";
999 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1000 let EncoderMethod = "getAddrMode6AddressOpValue";
1001 let DecoderMethod = "DecodeAddrMode6Operand";
1002}
1003
1004// Special version of addrmode6 to handle no allowed alignment encoding for
1005// VLD/VST instructions and checking the alignment is not specified.
1006def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1007 let Name = "AlignedMemoryNone";
1008 let DiagnosticType = "AlignedMemoryRequiresNone";
1009}
1010def addrmode6alignNone : AddrMode6Align {
1011 // The alignment specifier can only be omitted.
1012 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1013}
1014
1015// Special version of addrmode6 to handle 16-bit alignment encoding for
1016// VLD/VST instructions and checking the alignment value.
1017def AddrMode6Align16AsmOperand : AsmOperandClass {
1018 let Name = "AlignedMemory16";
1019 let DiagnosticType = "AlignedMemoryRequires16";
1020}
1021def addrmode6align16 : AddrMode6Align {
1022 // The alignment specifier can only be 16 or omitted.
1023 let ParserMatchClass = AddrMode6Align16AsmOperand;
1024}
1025
1026// Special version of addrmode6 to handle 32-bit alignment encoding for
1027// VLD/VST instructions and checking the alignment value.
1028def AddrMode6Align32AsmOperand : AsmOperandClass {
1029 let Name = "AlignedMemory32";
1030 let DiagnosticType = "AlignedMemoryRequires32";
1031}
1032def addrmode6align32 : AddrMode6Align {
1033 // The alignment specifier can only be 32 or omitted.
1034 let ParserMatchClass = AddrMode6Align32AsmOperand;
1035}
1036
1037// Special version of addrmode6 to handle 64-bit alignment encoding for
1038// VLD/VST instructions and checking the alignment value.
1039def AddrMode6Align64AsmOperand : AsmOperandClass {
1040 let Name = "AlignedMemory64";
1041 let DiagnosticType = "AlignedMemoryRequires64";
1042}
1043def addrmode6align64 : AddrMode6Align {
1044 // The alignment specifier can only be 64 or omitted.
1045 let ParserMatchClass = AddrMode6Align64AsmOperand;
1046}
1047
1048// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1049// for VLD/VST instructions and checking the alignment value.
1050def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1051 let Name = "AlignedMemory64or128";
1052 let DiagnosticType = "AlignedMemoryRequires64or128";
1053}
1054def addrmode6align64or128 : AddrMode6Align {
1055 // The alignment specifier can only be 64, 128 or omitted.
1056 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1057}
1058
1059// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1060// encoding for VLD/VST instructions and checking the alignment value.
1061def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1062 let Name = "AlignedMemory64or128or256";
1063 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1064}
1065def addrmode6align64or128or256 : AddrMode6Align {
1066 // The alignment specifier can only be 64, 128, 256 or omitted.
1067 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1068}
1069
223e47cc
LB		 1070// Special version of addrmode6 to handle alignment encoding for VLD-dup
1071// instructions, specifically VLD4-dup.
1072def addrmode6dup : Operand<i32>,
1073 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1074 let PrintMethod = "printAddrMode6Operand";
1075 let MIOperandInfo = (ops GPR:$addr, i32imm);
1076 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1077 // FIXME: This is close, but not quite right. The alignment specifier is
1078 // different.
1079 let ParserMatchClass = AddrMode6AsmOperand;
1080}
1081
1a4d82fc
JJ		 1082// Base class for addrmode6dup with specific alignment restrictions.
1083class AddrMode6DupAlign : Operand<i32>,
1084 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1085 let PrintMethod = "printAddrMode6Operand";
1086 let MIOperandInfo = (ops GPR:$addr, i32imm);
1087 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1088}
1089
1090// Special version of addrmode6 to handle no allowed alignment encoding for
1091// VLD-dup instruction and checking the alignment is not specified.
1092def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1093 let Name = "DupAlignedMemoryNone";
1094 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1095}
1096def addrmode6dupalignNone : AddrMode6DupAlign {
1097 // The alignment specifier can only be omitted.
1098 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1099}
1100
1101// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1102// instruction and checking the alignment value.
1103def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1104 let Name = "DupAlignedMemory16";
1105 let DiagnosticType = "DupAlignedMemoryRequires16";
1106}
1107def addrmode6dupalign16 : AddrMode6DupAlign {
1108 // The alignment specifier can only be 16 or omitted.
1109 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1110}
1111
1112// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1113// instruction and checking the alignment value.
1114def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1115 let Name = "DupAlignedMemory32";
1116 let DiagnosticType = "DupAlignedMemoryRequires32";
1117}
1118def addrmode6dupalign32 : AddrMode6DupAlign {
1119 // The alignment specifier can only be 32 or omitted.
1120 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1121}
1122
1123// Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1124// instructions and checking the alignment value.
1125def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1126 let Name = "DupAlignedMemory64";
1127 let DiagnosticType = "DupAlignedMemoryRequires64";
1128}
1129def addrmode6dupalign64 : AddrMode6DupAlign {
1130 // The alignment specifier can only be 64 or omitted.
1131 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1132}
1133
1134// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1135// for VLD instructions and checking the alignment value.
1136def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1137 let Name = "DupAlignedMemory64or128";
1138 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1139}
1140def addrmode6dupalign64or128 : AddrMode6DupAlign {
1141 // The alignment specifier can only be 64, 128 or omitted.
1142 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1143}
1144
223e47cc
LB		 1145// addrmodepc := pc + reg
1146//
1147def addrmodepc : Operand<i32>,
1148 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1149 let PrintMethod = "printAddrModePCOperand";
1150 let MIOperandInfo = (ops GPR, i32imm);
1151}
1152
1153// addr_offset_none := reg
1154//
1155def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1156def addr_offset_none : Operand<i32>,
1157 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1158 let PrintMethod = "printAddrMode7Operand";
1159 let DecoderMethod = "DecodeAddrMode7Operand";
1160 let ParserMatchClass = MemNoOffsetAsmOperand;
1161 let MIOperandInfo = (ops GPR:$base);
1162}
1163
1164def nohash_imm : Operand<i32> {
1165 let PrintMethod = "printNoHashImmediate";
1166}
1167
1168def CoprocNumAsmOperand : AsmOperandClass {
1169 let Name = "CoprocNum";
1170 let ParserMethod = "parseCoprocNumOperand";
1171}
1172def p_imm : Operand<i32> {
1173 let PrintMethod = "printPImmediate";
1174 let ParserMatchClass = CoprocNumAsmOperand;
1175 let DecoderMethod = "DecodeCoprocessor";
1176}
1177
223e47cc
LB		 1178def CoprocRegAsmOperand : AsmOperandClass {
1179 let Name = "CoprocReg";
1180 let ParserMethod = "parseCoprocRegOperand";
1181}
1182def c_imm : Operand<i32> {
1183 let PrintMethod = "printCImmediate";
1184 let ParserMatchClass = CoprocRegAsmOperand;
1185}
1186def CoprocOptionAsmOperand : AsmOperandClass {
1187 let Name = "CoprocOption";
1188 let ParserMethod = "parseCoprocOptionOperand";
1189}
1190def coproc_option_imm : Operand<i32> {
1191 let PrintMethod = "printCoprocOptionImm";
1192 let ParserMatchClass = CoprocOptionAsmOperand;
1193}
1194
1195//===----------------------------------------------------------------------===//
1196
1197include "ARMInstrFormats.td"
1198
1199//===----------------------------------------------------------------------===//
1200// Multiclass helpers...
1201//
1202
85aaf69f 1203/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
223e47cc
LB		 1204/// binop that produces a value.
1205let TwoOperandAliasConstraint = "$Rn = $Rd" in
1206multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1207 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1208 PatFrag opnode, bit Commutable = 0> {
1209 // The register-immediate version is re-materializable. This is useful
1210 // in particular for taking the address of a local.
1211 let isReMaterializable = 1 in {
85aaf69f 1212 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
223e47cc 1213 iii, opc, "\t$Rd, $Rn, $imm",
85aaf69f 1214 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1a4d82fc 1215 Sched<[WriteALU, ReadALU]> {
223e47cc
LB		 1216 bits<4> Rd;
1217 bits<4> Rn;
1218 bits<12> imm;
1219 let Inst{25} = 1;
1220 let Inst{19-16} = Rn;
1221 let Inst{15-12} = Rd;
1222 let Inst{11-0} = imm;
1223 }
1224 }
1225 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1226 iir, opc, "\t$Rd, $Rn, $Rm",
1a4d82fc
JJ		 1227 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1228 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 1229 bits<4> Rd;
1230 bits<4> Rn;
1231 bits<4> Rm;
1232 let Inst{25} = 0;
1233 let isCommutable = Commutable;
1234 let Inst{19-16} = Rn;
1235 let Inst{15-12} = Rd;
1236 let Inst{11-4} = 0b00000000;
1237 let Inst{3-0} = Rm;
1238 }
1239
1240 def rsi : AsI1<opcod, (outs GPR:$Rd),
1241 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1242 iis, opc, "\t$Rd, $Rn, $shift",
1a4d82fc
JJ		 1243 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1244 Sched<[WriteALUsi, ReadALU]> {
223e47cc
LB		 1245 bits<4> Rd;
1246 bits<4> Rn;
1247 bits<12> shift;
1248 let Inst{25} = 0;
1249 let Inst{19-16} = Rn;
1250 let Inst{15-12} = Rd;
1251 let Inst{11-5} = shift{11-5};
1252 let Inst{4} = 0;
1253 let Inst{3-0} = shift{3-0};
1254 }
1255
1256 def rsr : AsI1<opcod, (outs GPR:$Rd),
1257 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1258 iis, opc, "\t$Rd, $Rn, $shift",
1a4d82fc
JJ		 1259 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1260 Sched<[WriteALUsr, ReadALUsr]> {
223e47cc
LB		 1261 bits<4> Rd;
1262 bits<4> Rn;
1263 bits<12> shift;
1264 let Inst{25} = 0;
1265 let Inst{19-16} = Rn;
1266 let Inst{15-12} = Rd;
1267 let Inst{11-8} = shift{11-8};
1268 let Inst{7} = 0;
1269 let Inst{6-5} = shift{6-5};
1270 let Inst{4} = 1;
1271 let Inst{3-0} = shift{3-0};
1272 }
1273}
1274
1275/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1276/// reversed. The 'rr' form is only defined for the disassembler; for codegen
1277/// it is equivalent to the AsI1_bin_irs counterpart.
1278let TwoOperandAliasConstraint = "$Rn = $Rd" in
1279multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1280 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1281 PatFrag opnode, bit Commutable = 0> {
1282 // The register-immediate version is re-materializable. This is useful
1283 // in particular for taking the address of a local.
1284 let isReMaterializable = 1 in {
85aaf69f 1285 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
223e47cc 1286 iii, opc, "\t$Rd, $Rn, $imm",
85aaf69f 1287 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1a4d82fc 1288 Sched<[WriteALU, ReadALU]> {
223e47cc
LB		 1289 bits<4> Rd;
1290 bits<4> Rn;
1291 bits<12> imm;
1292 let Inst{25} = 1;
1293 let Inst{19-16} = Rn;
1294 let Inst{15-12} = Rd;
1295 let Inst{11-0} = imm;
1296 }
1297 }
1298 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1299 iir, opc, "\t$Rd, $Rn, $Rm",
1a4d82fc
JJ		 1300 [/* pattern left blank */]>,
1301 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 1302 bits<4> Rd;
1303 bits<4> Rn;
1304 bits<4> Rm;
1305 let Inst{11-4} = 0b00000000;
1306 let Inst{25} = 0;
1307 let Inst{3-0} = Rm;
1308 let Inst{15-12} = Rd;
1309 let Inst{19-16} = Rn;
1310 }
1311
1312 def rsi : AsI1<opcod, (outs GPR:$Rd),
1313 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1314 iis, opc, "\t$Rd, $Rn, $shift",
1a4d82fc
JJ		 1315 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1316 Sched<[WriteALUsi, ReadALU]> {
223e47cc
LB		 1317 bits<4> Rd;
1318 bits<4> Rn;
1319 bits<12> shift;
1320 let Inst{25} = 0;
1321 let Inst{19-16} = Rn;
1322 let Inst{15-12} = Rd;
1323 let Inst{11-5} = shift{11-5};
1324 let Inst{4} = 0;
1325 let Inst{3-0} = shift{3-0};
1326 }
1327
1328 def rsr : AsI1<opcod, (outs GPR:$Rd),
1329 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1330 iis, opc, "\t$Rd, $Rn, $shift",
1a4d82fc
JJ		 1331 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1332 Sched<[WriteALUsr, ReadALUsr]> {
223e47cc
LB		 1333 bits<4> Rd;
1334 bits<4> Rn;
1335 bits<12> shift;
1336 let Inst{25} = 0;
1337 let Inst{19-16} = Rn;
1338 let Inst{15-12} = Rd;
1339 let Inst{11-8} = shift{11-8};
1340 let Inst{7} = 0;
1341 let Inst{6-5} = shift{6-5};
1342 let Inst{4} = 1;
1343 let Inst{3-0} = shift{3-0};
1344 }
1345}
1346
1347/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1348///
1349/// These opcodes will be converted to the real non-S opcodes by
1350/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1351let hasPostISelHook = 1, Defs = [CPSR] in {
1352multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1353 InstrItinClass iis, PatFrag opnode,
1354 bit Commutable = 0> {
85aaf69f 1355 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
223e47cc 1356 4, iii,
85aaf69f 1357 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1a4d82fc 1358 Sched<[WriteALU, ReadALU]>;
223e47cc
LB		 1359
1360 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1361 4, iir,
1a4d82fc
JJ		 1362 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1363 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 1364 let isCommutable = Commutable;
1365 }
1366 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1367 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1368 4, iis,
1369 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1a4d82fc
JJ		 1370 so_reg_imm:$shift))]>,
1371 Sched<[WriteALUsi, ReadALU]>;
223e47cc
LB		 1372
1373 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1374 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1375 4, iis,
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1a4d82fc
JJ		 1377 so_reg_reg:$shift))]>,
1378 Sched<[WriteALUSsr, ReadALUsr]>;
223e47cc
LB		 1379}
1380}
1381
1382/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1383/// operands are reversed.
1384let hasPostISelHook = 1, Defs = [CPSR] in {
1385multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1386 InstrItinClass iis, PatFrag opnode,
1387 bit Commutable = 0> {
85aaf69f 1388 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
223e47cc 1389 4, iii,
85aaf69f 1390 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1a4d82fc 1391 Sched<[WriteALU, ReadALU]>;
223e47cc
LB		 1392
1393 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1394 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1395 4, iis,
1396 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1a4d82fc
JJ		 1397 GPR:$Rn))]>,
1398 Sched<[WriteALUsi, ReadALU]>;
223e47cc
LB		 1399
1400 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1401 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1402 4, iis,
1403 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1a4d82fc
JJ		 1404 GPR:$Rn))]>,
1405 Sched<[WriteALUSsr, ReadALUsr]>;
223e47cc
LB		 1406}
1407}
1408
85aaf69f 1409/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
223e47cc
LB		 1410/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1411/// a explicit result, only implicitly set CPSR.
1412let isCompare = 1, Defs = [CPSR] in {
1413multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1414 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1415 PatFrag opnode, bit Commutable = 0> {
85aaf69f 1416 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
223e47cc 1417 opc, "\t$Rn, $imm",
85aaf69f 1418 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1a4d82fc 1419 Sched<[WriteCMP, ReadALU]> {
223e47cc
LB		 1420 bits<4> Rn;
1421 bits<12> imm;
1422 let Inst{25} = 1;
1423 let Inst{20} = 1;
1424 let Inst{19-16} = Rn;
1425 let Inst{15-12} = 0b0000;
1426 let Inst{11-0} = imm;
1427
1428 let Unpredictable{15-12} = 0b1111;
1429 }
1430 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1431 opc, "\t$Rn, $Rm",
1a4d82fc
JJ		 1432 [(opnode GPR:$Rn, GPR:$Rm)]>,
1433 Sched<[WriteCMP, ReadALU, ReadALU]> {
223e47cc
LB		 1434 bits<4> Rn;
1435 bits<4> Rm;
1436 let isCommutable = Commutable;
1437 let Inst{25} = 0;
1438 let Inst{20} = 1;
1439 let Inst{19-16} = Rn;
1440 let Inst{15-12} = 0b0000;
1441 let Inst{11-4} = 0b00000000;
1442 let Inst{3-0} = Rm;
1443
1444 let Unpredictable{15-12} = 0b1111;
1445 }
1446 def rsi : AI1<opcod, (outs),
1447 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1448 opc, "\t$Rn, $shift",
1a4d82fc
JJ		 1449 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1450 Sched<[WriteCMPsi, ReadALU]> {
223e47cc
LB		 1451 bits<4> Rn;
1452 bits<12> shift;
1453 let Inst{25} = 0;
1454 let Inst{20} = 1;
1455 let Inst{19-16} = Rn;
1456 let Inst{15-12} = 0b0000;
1457 let Inst{11-5} = shift{11-5};
1458 let Inst{4} = 0;
1459 let Inst{3-0} = shift{3-0};
1460
1461 let Unpredictable{15-12} = 0b1111;
1462 }
1463 def rsr : AI1<opcod, (outs),
1464 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1465 opc, "\t$Rn, $shift",
1a4d82fc
JJ		 1466 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1467 Sched<[WriteCMPsr, ReadALU]> {
223e47cc
LB		 1468 bits<4> Rn;
1469 bits<12> shift;
1470 let Inst{25} = 0;
1471 let Inst{20} = 1;
1472 let Inst{19-16} = Rn;
1473 let Inst{15-12} = 0b0000;
1474 let Inst{11-8} = shift{11-8};
1475 let Inst{7} = 0;
1476 let Inst{6-5} = shift{6-5};
1477 let Inst{4} = 1;
1478 let Inst{3-0} = shift{3-0};
1479
1480 let Unpredictable{15-12} = 0b1111;
1481 }
1482
1483}
1484}
1485
1486/// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1487/// register and one whose operand is a register rotated by 8/16/24.
1488/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1489class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1490 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1491 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1492 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1a4d82fc 1493 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
223e47cc
LB		 1494 bits<4> Rd;
1495 bits<4> Rm;
1496 bits<2> rot;
1497 let Inst{19-16} = 0b1111;
1498 let Inst{15-12} = Rd;
1499 let Inst{11-10} = rot;
1500 let Inst{3-0} = Rm;
1501}
1502
1503class AI_ext_rrot_np<bits<8> opcod, string opc>
1504 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1505 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1a4d82fc 1506 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
223e47cc
LB		 1507 bits<2> rot;
1508 let Inst{19-16} = 0b1111;
1509 let Inst{11-10} = rot;
1a4d82fc 1510 }
223e47cc
LB		 1511
1512/// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1513/// register and one whose operand is a register rotated by 8/16/24.
1514class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1515 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1516 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1517 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1518 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1a4d82fc 1519 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
223e47cc
LB		 1520 bits<4> Rd;
1521 bits<4> Rm;
1522 bits<4> Rn;
1523 bits<2> rot;
1524 let Inst{19-16} = Rn;
1525 let Inst{15-12} = Rd;
1526 let Inst{11-10} = rot;
1527 let Inst{9-4} = 0b000111;
1528 let Inst{3-0} = Rm;
1529}
1530
1531class AI_exta_rrot_np<bits<8> opcod, string opc>
1532 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1533 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1a4d82fc 1534 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
223e47cc
LB		 1535 bits<4> Rn;
1536 bits<2> rot;
1537 let Inst{19-16} = Rn;
1538 let Inst{11-10} = rot;
1539}
1540
1541/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1542let TwoOperandAliasConstraint = "$Rn = $Rd" in
1543multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1544 bit Commutable = 0> {
1545 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
85aaf69f 1546 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
223e47cc 1547 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
85aaf69f 1548 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1a4d82fc
JJ		 1549 Requires<[IsARM]>,
1550 Sched<[WriteALU, ReadALU]> {
223e47cc
LB		 1551 bits<4> Rd;
1552 bits<4> Rn;
1553 bits<12> imm;
1554 let Inst{25} = 1;
1555 let Inst{15-12} = Rd;
1556 let Inst{19-16} = Rn;
1557 let Inst{11-0} = imm;
1558 }
1559 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1560 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1561 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1a4d82fc
JJ		 1562 Requires<[IsARM]>,
1563 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 1564 bits<4> Rd;
1565 bits<4> Rn;
1566 bits<4> Rm;
1567 let Inst{11-4} = 0b00000000;
1568 let Inst{25} = 0;
1569 let isCommutable = Commutable;
1570 let Inst{3-0} = Rm;
1571 let Inst{15-12} = Rd;
1572 let Inst{19-16} = Rn;
1573 }
1574 def rsi : AsI1<opcod, (outs GPR:$Rd),
1575 (ins GPR:$Rn, so_reg_imm:$shift),
1576 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1577 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1a4d82fc
JJ		 1578 Requires<[IsARM]>,
1579 Sched<[WriteALUsi, ReadALU]> {
223e47cc
LB		 1580 bits<4> Rd;
1581 bits<4> Rn;
1582 bits<12> shift;
1583 let Inst{25} = 0;
1584 let Inst{19-16} = Rn;
1585 let Inst{15-12} = Rd;
1586 let Inst{11-5} = shift{11-5};
1587 let Inst{4} = 0;
1588 let Inst{3-0} = shift{3-0};
1589 }
1590 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1591 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1592 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1593 [(set GPRnopc:$Rd, CPSR,
1594 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1a4d82fc
JJ		 1595 Requires<[IsARM]>,
1596 Sched<[WriteALUsr, ReadALUsr]> {
223e47cc
LB		 1597 bits<4> Rd;
1598 bits<4> Rn;
1599 bits<12> shift;
1600 let Inst{25} = 0;
1601 let Inst{19-16} = Rn;
1602 let Inst{15-12} = Rd;
1603 let Inst{11-8} = shift{11-8};
1604 let Inst{7} = 0;
1605 let Inst{6-5} = shift{6-5};
1606 let Inst{4} = 1;
1607 let Inst{3-0} = shift{3-0};
1608 }
1609 }
1610}
1611
1612/// AI1_rsc_irs - Define instructions and patterns for rsc
1613let TwoOperandAliasConstraint = "$Rn = $Rd" in
1614multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1615 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
85aaf69f 1616 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
223e47cc 1617 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
85aaf69f 1618 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1a4d82fc
JJ		 1619 Requires<[IsARM]>,
1620 Sched<[WriteALU, ReadALU]> {
223e47cc
LB		 1621 bits<4> Rd;
1622 bits<4> Rn;
1623 bits<12> imm;
1624 let Inst{25} = 1;
1625 let Inst{15-12} = Rd;
1626 let Inst{19-16} = Rn;
1627 let Inst{11-0} = imm;
1628 }
1629 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1630 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1a4d82fc
JJ		 1631 [/* pattern left blank */]>,
1632 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 1633 bits<4> Rd;
1634 bits<4> Rn;
1635 bits<4> Rm;
1636 let Inst{11-4} = 0b00000000;
1637 let Inst{25} = 0;
1638 let Inst{3-0} = Rm;
1639 let Inst{15-12} = Rd;
1640 let Inst{19-16} = Rn;
1641 }
1642 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1643 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1644 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1a4d82fc
JJ		 1645 Requires<[IsARM]>,
1646 Sched<[WriteALUsi, ReadALU]> {
223e47cc
LB		 1647 bits<4> Rd;
1648 bits<4> Rn;
1649 bits<12> shift;
1650 let Inst{25} = 0;
1651 let Inst{19-16} = Rn;
1652 let Inst{15-12} = Rd;
1653 let Inst{11-5} = shift{11-5};
1654 let Inst{4} = 0;
1655 let Inst{3-0} = shift{3-0};
1656 }
1657 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1658 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1659 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1a4d82fc
JJ		 1660 Requires<[IsARM]>,
1661 Sched<[WriteALUsr, ReadALUsr]> {
223e47cc
LB		 1662 bits<4> Rd;
1663 bits<4> Rn;
1664 bits<12> shift;
1665 let Inst{25} = 0;
1666 let Inst{19-16} = Rn;
1667 let Inst{15-12} = Rd;
1668 let Inst{11-8} = shift{11-8};
1669 let Inst{7} = 0;
1670 let Inst{6-5} = shift{6-5};
1671 let Inst{4} = 1;
1672 let Inst{3-0} = shift{3-0};
1673 }
1674 }
1675}
1676
1677let canFoldAsLoad = 1, isReMaterializable = 1 in {
1678multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1679 InstrItinClass iir, PatFrag opnode> {
1680 // Note: We use the complex addrmode_imm12 rather than just an input
1681 // GPR and a constrained immediate so that we can use this to match
1682 // frame index references and avoid matching constant pool references.
1683 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1684 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1685 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1686 bits<4> Rt;
1687 bits<17> addr;
1688 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1689 let Inst{19-16} = addr{16-13}; // Rn
1690 let Inst{15-12} = Rt;
1691 let Inst{11-0} = addr{11-0}; // imm12
1692 }
1693 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1694 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1695 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1696 bits<4> Rt;
1697 bits<17> shift;
1698 let shift{4} = 0; // Inst{4} = 0
1699 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1700 let Inst{19-16} = shift{16-13}; // Rn
1701 let Inst{15-12} = Rt;
1702 let Inst{11-0} = shift{11-0};
1703 }
1704}
1705}
1706
1707let canFoldAsLoad = 1, isReMaterializable = 1 in {
1708multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1709 InstrItinClass iir, PatFrag opnode> {
1710 // Note: We use the complex addrmode_imm12 rather than just an input
1711 // GPR and a constrained immediate so that we can use this to match
1712 // frame index references and avoid matching constant pool references.
1713 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1714 (ins addrmode_imm12:$addr),
1715 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1716 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1717 bits<4> Rt;
1718 bits<17> addr;
1719 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1720 let Inst{19-16} = addr{16-13}; // Rn
1721 let Inst{15-12} = Rt;
1722 let Inst{11-0} = addr{11-0}; // imm12
1723 }
1724 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1725 (ins ldst_so_reg:$shift),
1726 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1727 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1728 bits<4> Rt;
1729 bits<17> shift;
1730 let shift{4} = 0; // Inst{4} = 0
1731 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1732 let Inst{19-16} = shift{16-13}; // Rn
1733 let Inst{15-12} = Rt;
1734 let Inst{11-0} = shift{11-0};
1735 }
1736}
1737}
1738
1739
1740multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1741 InstrItinClass iir, PatFrag opnode> {
1742 // Note: We use the complex addrmode_imm12 rather than just an input
1743 // GPR and a constrained immediate so that we can use this to match
1744 // frame index references and avoid matching constant pool references.
1745 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1746 (ins GPR:$Rt, addrmode_imm12:$addr),
1747 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1748 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1749 bits<4> Rt;
1750 bits<17> addr;
1751 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1752 let Inst{19-16} = addr{16-13}; // Rn
1753 let Inst{15-12} = Rt;
1754 let Inst{11-0} = addr{11-0}; // imm12
1755 }
1756 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1757 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1758 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1759 bits<4> Rt;
1760 bits<17> shift;
1761 let shift{4} = 0; // Inst{4} = 0
1762 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1763 let Inst{19-16} = shift{16-13}; // Rn
1764 let Inst{15-12} = Rt;
1765 let Inst{11-0} = shift{11-0};
1766 }
1767}
1768
1769multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1770 InstrItinClass iir, PatFrag opnode> {
1771 // Note: We use the complex addrmode_imm12 rather than just an input
1772 // GPR and a constrained immediate so that we can use this to match
1773 // frame index references and avoid matching constant pool references.
1774 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1775 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1776 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1777 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1778 bits<4> Rt;
1779 bits<17> addr;
1780 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1781 let Inst{19-16} = addr{16-13}; // Rn
1782 let Inst{15-12} = Rt;
1783 let Inst{11-0} = addr{11-0}; // imm12
1784 }
1785 def rs : AI2ldst<0b011, 0, isByte, (outs),
1786 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1787 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1788 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1789 bits<4> Rt;
1790 bits<17> shift;
1791 let shift{4} = 0; // Inst{4} = 0
1792 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1793 let Inst{19-16} = shift{16-13}; // Rn
1794 let Inst{15-12} = Rt;
1795 let Inst{11-0} = shift{11-0};
1796 }
1797}
1798
1799
1800//===----------------------------------------------------------------------===//
1801// Instructions
1802//===----------------------------------------------------------------------===//
1803
1804//===----------------------------------------------------------------------===//
1805// Miscellaneous Instructions.
1806//
1807
1808/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1809/// the function. The first operand is the ID# for this instruction, the second
1810/// is the index into the MachineConstantPool that this is, the third is the
1811/// size in bytes of this constant pool entry.
85aaf69f 1812let hasSideEffects = 0, isNotDuplicable = 1 in
223e47cc
LB		 1813def CONSTPOOL_ENTRY :
1814PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1815 i32imm:$size), NoItinerary, []>;
1816
1817// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1818// from removing one half of the matched pairs. That breaks PEI, which assumes
1819// these will always be in pairs, and asserts if it finds otherwise. Better way?
1820let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1821def ADJCALLSTACKUP :
1822PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1823 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1824
1825def ADJCALLSTACKDOWN :
1826PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1827 [(ARMcallseq_start timm:$amt)]>;
1828}
1829
1a4d82fc
JJ		 1830def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1831 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1832 Requires<[IsARM, HasV6]> {
223e47cc
LB		 1833 bits<8> imm;
1834 let Inst{27-8} = 0b00110010000011110000;
1835 let Inst{7-0} = imm;
1836}
1837
1838def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1839def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1840def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1841def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1842def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1a4d82fc 1843def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
223e47cc
LB		 1844
1845def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1846 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1847 bits<4> Rd;
1848 bits<4> Rn;
1849 bits<4> Rm;
1850 let Inst{3-0} = Rm;
1851 let Inst{15-12} = Rd;
1852 let Inst{19-16} = Rn;
1853 let Inst{27-20} = 0b01101000;
1854 let Inst{7-4} = 0b1011;
1855 let Inst{11-8} = 0b1111;
1856 let Unpredictable{11-8} = 0b1111;
1857}
1858
1859// The 16-bit operand $val can be used by a debugger to store more information
1860// about the breakpoint.
1a4d82fc
JJ		 1861def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1862 "bkpt", "\t$val", []>, Requires<[IsARM]> {
223e47cc
LB		 1863 bits<16> val;
1864 let Inst{3-0} = val{3-0};
1865 let Inst{19-8} = val{15-4};
1866 let Inst{27-20} = 0b00010010;
1a4d82fc
JJ		 1867 let Inst{31-28} = 0xe; // AL
1868 let Inst{7-4} = 0b0111;
1869}
1870// default immediate for breakpoint mnemonic
1871def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1872
1873def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1874 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1875 bits<16> val;
1876 let Inst{3-0} = val{3-0};
1877 let Inst{19-8} = val{15-4};
1878 let Inst{27-20} = 0b00010000;
1879 let Inst{31-28} = 0xe; // AL
223e47cc
LB		 1880 let Inst{7-4} = 0b0111;
1881}
1882
1883// Change Processor State
1884// FIXME: We should use InstAlias to handle the optional operands.
1885class CPS<dag iops, string asm_ops>
1886 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1887 []>, Requires<[IsARM]> {
1888 bits<2> imod;
1889 bits<3> iflags;
1890 bits<5> mode;
1891 bit M;
1892
1893 let Inst{31-28} = 0b1111;
1894 let Inst{27-20} = 0b00010000;
1895 let Inst{19-18} = imod;
1896 let Inst{17} = M; // Enabled if mode is set;
1897 let Inst{16-9} = 0b00000000;
1898 let Inst{8-6} = iflags;
1899 let Inst{5} = 0;
1900 let Inst{4-0} = mode;
1901}
1902
1903let DecoderMethod = "DecodeCPSInstruction" in {
1904let M = 1 in
1905 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1906 "$imod\t$iflags, $mode">;
1907let mode = 0, M = 0 in
1908 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1909
1910let imod = 0, iflags = 0, M = 1 in
1911 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1912}
1913
1914// Preload signals the memory system of possible future data/instruction access.
1915multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1916
1a4d82fc
JJ		 1917 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1918 IIC_Preload, !strconcat(opc, "\t$addr"),
1919 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1920 Sched<[WritePreLd]> {
223e47cc
LB		 1921 bits<4> Rt;
1922 bits<17> addr;
1923 let Inst{31-26} = 0b111101;
1924 let Inst{25} = 0; // 0 for immediate form
1925 let Inst{24} = data;
1926 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1927 let Inst{22} = read;
1928 let Inst{21-20} = 0b01;
1929 let Inst{19-16} = addr{16-13}; // Rn
1930 let Inst{15-12} = 0b1111;
1931 let Inst{11-0} = addr{11-0}; // imm12
1932 }
1933
1934 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1935 !strconcat(opc, "\t$shift"),
1a4d82fc
JJ		 1936 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1937 Sched<[WritePreLd]> {
223e47cc
LB		 1938 bits<17> shift;
1939 let Inst{31-26} = 0b111101;
1940 let Inst{25} = 1; // 1 for register form
1941 let Inst{24} = data;
1942 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1943 let Inst{22} = read;
1944 let Inst{21-20} = 0b01;
1945 let Inst{19-16} = shift{16-13}; // Rn
1946 let Inst{15-12} = 0b1111;
1947 let Inst{11-0} = shift{11-0};
1948 let Inst{4} = 0;
1949 }
1950}
1951
1952defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1953defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1954defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1955
1956def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1a4d82fc 1957 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
223e47cc
LB		 1958 bits<1> end;
1959 let Inst{31-10} = 0b1111000100000001000000;
1960 let Inst{9} = end;
1961 let Inst{8-0} = 0;
1962}
1963
1964def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1a4d82fc 1965 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
223e47cc
LB		 1966 bits<4> opt;
1967 let Inst{27-4} = 0b001100100000111100001111;
1968 let Inst{3-0} = opt;
1969}
1970
1a4d82fc
JJ		 1971// A8.8.247 UDF - Undefined (Encoding A1)
1972def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1973 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1974 bits<16> imm16;
1975 let Inst{31-28} = 0b1110; // AL
1976 let Inst{27-25} = 0b011;
1977 let Inst{24-20} = 0b11111;
1978 let Inst{19-8} = imm16{15-4};
1979 let Inst{7-4} = 0b1111;
1980 let Inst{3-0} = imm16{3-0};
1981}
1982
970d7e83
LB		 1983/*
1984 * A5.4 Permanently UNDEFINED instructions.
1985 *
1986 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1987 * Other UDF encodings generate SIGILL.
1988 *
1989 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1990 * Encoding A1:
1991 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1992 * Encoding T1:
1993 * 1101 1110 iiii iiii
1994 * It uses the following encoding:
1995 * 1110 0111 1111 1110 1101 1110 1111 0000
1996 * - In ARM: UDF #60896;
1997 * - In Thumb: UDF #254 followed by a branch-to-self.
1998 */
1999let isBarrier = 1, isTerminator = 1 in
2000def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2001 "trap", [(trap)]>,
2002 Requires<[IsARM,UseNaClTrap]> {
2003 let Inst = 0xe7fedef0;
2004}
223e47cc
LB		 2005let isBarrier = 1, isTerminator = 1 in
2006def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2007 "trap", [(trap)]>,
970d7e83 2008 Requires<[IsARM,DontUseNaClTrap]> {
223e47cc
LB		 2009 let Inst = 0xe7ffdefe;
2010}
2011
2012// Address computation and loads and stores in PIC mode.
2013let isNotDuplicable = 1 in {
2014def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2015 4, IIC_iALUr,
1a4d82fc
JJ		 2016 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2017 Sched<[WriteALU, ReadALU]>;
223e47cc
LB		 2018
2019let AddedComplexity = 10 in {
2020def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2021 4, IIC_iLoad_r,
2022 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2023
2024def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2025 4, IIC_iLoad_bh_r,
2026 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2027
2028def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2029 4, IIC_iLoad_bh_r,
2030 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2031
2032def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2033 4, IIC_iLoad_bh_r,
2034 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2035
2036def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2037 4, IIC_iLoad_bh_r,
2038 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2039}
2040let AddedComplexity = 10 in {
2041def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2042 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2043
2044def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2045 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2046 addrmodepc:$addr)]>;
2047
2048def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2049 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2050}
2051} // isNotDuplicable = 1
2052
2053
2054// LEApcrel - Load a pc-relative address into a register without offending the
2055// assembler.
85aaf69f 2056let hasSideEffects = 0, isReMaterializable = 1 in
223e47cc
LB		 2057// The 'adr' mnemonic encodes differently if the label is before or after
2058// the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2059// know until then which form of the instruction will be used.
2060def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1a4d82fc
JJ		 2061 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2062 Sched<[WriteALU, ReadALU]> {
223e47cc
LB		 2063 bits<4> Rd;
2064 bits<14> label;
2065 let Inst{27-25} = 0b001;
2066 let Inst{24} = 0;
2067 let Inst{23-22} = label{13-12};
2068 let Inst{21} = 0;
2069 let Inst{20} = 0;
2070 let Inst{19-16} = 0b1111;
2071 let Inst{15-12} = Rd;
2072 let Inst{11-0} = label{11-0};
2073}
2074
2075let hasSideEffects = 1 in {
2076def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1a4d82fc 2077 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
223e47cc
LB		 2078
2079def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2080 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1a4d82fc 2081 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
223e47cc
LB		 2082}
2083
2084//===----------------------------------------------------------------------===//
2085// Control Flow Instructions.
2086//
2087
2088let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2089 // ARMV4T and above
2090 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2091 "bx", "\tlr", [(ARMretflag)]>,
1a4d82fc 2092 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
223e47cc
LB		 2093 let Inst{27-0} = 0b0001001011111111111100011110;
2094 }
2095
2096 // ARMV4 only
2097 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2098 "mov", "\tpc, lr", [(ARMretflag)]>,
1a4d82fc 2099 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
223e47cc
LB		 2100 let Inst{27-0} = 0b0001101000001111000000001110;
2101 }
1a4d82fc
JJ		 2102
2103 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2104 // the user-space one).
2105 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2106 4, IIC_Br,
2107 [(ARMintretflag imm:$offset)]>;
223e47cc
LB		 2108}
2109
2110// Indirect branches
2111let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2112 // ARMV4T and above
2113 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2114 [(brind GPR:$dst)]>,
1a4d82fc 2115 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
223e47cc
LB		 2116 bits<4> dst;
2117 let Inst{31-4} = 0b1110000100101111111111110001;
2118 let Inst{3-0} = dst;
2119 }
2120
2121 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2122 "bx", "\t$dst", [/* pattern left blank */]>,
1a4d82fc 2123 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
223e47cc
LB		 2124 bits<4> dst;
2125 let Inst{27-4} = 0b000100101111111111110001;
2126 let Inst{3-0} = dst;
2127 }
2128}
2129
2130// SP is marked as a use to prevent stack-pointer assignments that appear
2131// immediately before calls from potentially appearing dead.
2132let isCall = 1,
2133 // FIXME: Do we really need a non-predicated version? If so, it should
2134 // at least be a pseudo instruction expanding to the predicated version
2135 // at MC lowering time.
2136 Defs = [LR], Uses = [SP] in {
2137 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2138 IIC_Br, "bl\t$func",
2139 [(ARMcall tglobaladdr:$func)]>,
1a4d82fc 2140 Requires<[IsARM]>, Sched<[WriteBrL]> {
223e47cc
LB		 2141 let Inst{31-28} = 0b1110;
2142 bits<24> func;
2143 let Inst{23-0} = func;
2144 let DecoderMethod = "DecodeBranchImmInstruction";
2145 }
2146
2147 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2148 IIC_Br, "bl", "\t$func",
2149 [(ARMcall_pred tglobaladdr:$func)]>,
1a4d82fc 2150 Requires<[IsARM]>, Sched<[WriteBrL]> {
223e47cc
LB		 2151 bits<24> func;
2152 let Inst{23-0} = func;
2153 let DecoderMethod = "DecodeBranchImmInstruction";
2154 }
2155
2156 // ARMv5T and above
2157 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2158 IIC_Br, "blx\t$func",
2159 [(ARMcall GPR:$func)]>,
1a4d82fc 2160 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
223e47cc
LB		 2161 bits<4> func;
2162 let Inst{31-4} = 0b1110000100101111111111110011;
2163 let Inst{3-0} = func;
2164 }
2165
2166 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2167 IIC_Br, "blx", "\t$func",
2168 [(ARMcall_pred GPR:$func)]>,
1a4d82fc 2169 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
223e47cc
LB		 2170 bits<4> func;
2171 let Inst{27-4} = 0b000100101111111111110011;
2172 let Inst{3-0} = func;
2173 }
2174
2175 // ARMv4T
2176 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2177 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2178 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1a4d82fc 2179 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
223e47cc
LB		 2180
2181 // ARMv4
2182 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2183 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1a4d82fc 2184 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
223e47cc
LB		 2185
2186 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2187 // return stack predictor.
2188 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2189 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1a4d82fc 2190 Requires<[IsARM]>, Sched<[WriteBr]>;
223e47cc
LB		 2191}
2192
2193let isBranch = 1, isTerminator = 1 in {
2194 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2195 // a two-value operand where a dag node expects two operands. :(
2196 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2197 IIC_Br, "b", "\t$target",
1a4d82fc
JJ		 2198 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2199 Sched<[WriteBr]> {
223e47cc
LB		 2200 bits<24> target;
2201 let Inst{23-0} = target;
2202 let DecoderMethod = "DecodeBranchImmInstruction";
2203 }
2204
2205 let isBarrier = 1 in {
2206 // B is "predicable" since it's just a Bcc with an 'always' condition.
2207 let isPredicable = 1 in
2208 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2209 // should be sufficient.
2210 // FIXME: Is B really a Barrier? That doesn't seem right.
2211 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1a4d82fc
JJ		 2212 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2213 Sched<[WriteBr]>;
223e47cc
LB		 2214
2215 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2216 def BR_JTr : ARMPseudoInst<(outs),
2217 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2218 0, IIC_Br,
1a4d82fc
JJ		 2219 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2220 Sched<[WriteBr]>;
223e47cc
LB		 2221 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2222 // into i12 and rs suffixed versions.
2223 def BR_JTm : ARMPseudoInst<(outs),
2224 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2225 0, IIC_Br,
2226 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1a4d82fc 2227 imm:$id)]>, Sched<[WriteBrTbl]>;
223e47cc
LB		 2228 def BR_JTadd : ARMPseudoInst<(outs),
2229 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2230 0, IIC_Br,
2231 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1a4d82fc 2232 imm:$id)]>, Sched<[WriteBrTbl]>;
223e47cc
LB		 2233 } // isNotDuplicable = 1, isIndirectBranch = 1
2234 } // isBarrier = 1
2235
2236}
2237
2238// BLX (immediate)
2239def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2240 "blx\t$target", []>,
1a4d82fc 2241 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
223e47cc
LB		 2242 let Inst{31-25} = 0b1111101;
2243 bits<25> target;
2244 let Inst{23-0} = target{24-1};
2245 let Inst{24} = target{0};
2246}
2247
2248// Branch and Exchange Jazelle
2249def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1a4d82fc 2250 [/* pattern left blank */]>, Sched<[WriteBr]> {
223e47cc
LB		 2251 bits<4> func;
2252 let Inst{23-20} = 0b0010;
2253 let Inst{19-8} = 0xfff;
2254 let Inst{7-4} = 0b0010;
2255 let Inst{3-0} = func;
2256}
2257
2258// Tail calls.
2259
2260let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1a4d82fc
JJ		 2261 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2262 Sched<[WriteBr]>;
223e47cc 2263
1a4d82fc
JJ		 2264 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2265 Sched<[WriteBr]>;
223e47cc
LB		 2266
2267 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2268 4, IIC_Br, [],
2269 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1a4d82fc 2270 Requires<[IsARM]>, Sched<[WriteBr]>;
223e47cc
LB		 2271
2272 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2273 4, IIC_Br, [],
1a4d82fc 2274 (BX GPR:$dst)>, Sched<[WriteBr]>,
223e47cc
LB		 2275 Requires<[IsARM]>;
2276}
2277
2278// Secure Monitor Call is a system instruction.
2279def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1a4d82fc 2280 []>, Requires<[IsARM, HasTrustZone]> {
223e47cc
LB		 2281 bits<4> opt;
2282 let Inst{23-4} = 0b01100000000000000111;
2283 let Inst{3-0} = opt;
2284}
2285
2286// Supervisor Call (Software Interrupt)
2287let isCall = 1, Uses = [SP] in {
1a4d82fc
JJ		 2288def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2289 Sched<[WriteBr]> {
223e47cc
LB		 2290 bits<24> svc;
2291 let Inst{23-0} = svc;
2292}
2293}
2294
2295// Store Return State
2296class SRSI<bit wb, string asm>
2297 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2298 NoItinerary, asm, "", []> {
2299 bits<5> mode;
2300 let Inst{31-28} = 0b1111;
2301 let Inst{27-25} = 0b100;
2302 let Inst{22} = 1;
2303 let Inst{21} = wb;
2304 let Inst{20} = 0;
2305 let Inst{19-16} = 0b1101; // SP
2306 let Inst{15-5} = 0b00000101000;
2307 let Inst{4-0} = mode;
2308}
2309
2310def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2311 let Inst{24-23} = 0;
2312}
2313def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2314 let Inst{24-23} = 0;
2315}
2316def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2317 let Inst{24-23} = 0b10;
2318}
2319def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2320 let Inst{24-23} = 0b10;
2321}
2322def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2323 let Inst{24-23} = 0b01;
2324}
2325def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2326 let Inst{24-23} = 0b01;
2327}
2328def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2329 let Inst{24-23} = 0b11;
2330}
2331def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2332 let Inst{24-23} = 0b11;
2333}
2334
970d7e83
LB		 2335def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2336def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2337
2338def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2339def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2340
2341def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2342def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2343
2344def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2345def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2346
223e47cc
LB		 2347// Return From Exception
2348class RFEI<bit wb, string asm>
2349 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2350 NoItinerary, asm, "", []> {
2351 bits<4> Rn;
2352 let Inst{31-28} = 0b1111;
2353 let Inst{27-25} = 0b100;
2354 let Inst{22} = 0;
2355 let Inst{21} = wb;
2356 let Inst{20} = 1;
2357 let Inst{19-16} = Rn;
2358 let Inst{15-0} = 0xa00;
2359}
2360
2361def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2362 let Inst{24-23} = 0;
2363}
2364def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2365 let Inst{24-23} = 0;
2366}
2367def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2368 let Inst{24-23} = 0b10;
2369}
2370def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2371 let Inst{24-23} = 0b10;
2372}
2373def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2374 let Inst{24-23} = 0b01;
2375}
2376def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2377 let Inst{24-23} = 0b01;
2378}
2379def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2380 let Inst{24-23} = 0b11;
2381}
2382def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2383 let Inst{24-23} = 0b11;
2384}
2385
85aaf69f
SL		 2386// Hypervisor Call is a system instruction
2387let isCall = 1 in {
2388def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2389 "hvc", "\t$imm", []>,
2390 Requires<[IsARM, HasVirtualization]> {
2391 bits<16> imm;
2392
2393 // Even though HVC isn't predicable, it's encoding includes a condition field.
2394 // The instruction is undefined if the condition field is 0xf otherwise it is
2395 // unpredictable if it isn't condition AL (0xe).
2396 let Inst{31-28} = 0b1110;
2397 let Unpredictable{31-28} = 0b1111;
2398 let Inst{27-24} = 0b0001;
2399 let Inst{23-20} = 0b0100;
2400 let Inst{19-8} = imm{15-4};
2401 let Inst{7-4} = 0b0111;
2402 let Inst{3-0} = imm{3-0};
2403}
2404}
2405
2406// Return from exception in Hypervisor mode.
2407let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2408def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2409 Requires<[IsARM, HasVirtualization]> {
2410 let Inst{23-0} = 0b011000000000000001101110;
2411}
2412
223e47cc
LB		 2413//===----------------------------------------------------------------------===//
2414// Load / Store Instructions.
2415//
2416
2417// Load
2418
2419
2420defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2421 UnOpFrag<(load node:$Src)>>;
2422defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2423 UnOpFrag<(zextloadi8 node:$Src)>>;
2424defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2425 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2426defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2427 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2428
2429// Special LDR for loads from non-pc-relative constpools.
85aaf69f 2430let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
223e47cc
LB		 2431 isReMaterializable = 1, isCodeGenOnly = 1 in
2432def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2433 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2434 []> {
2435 bits<4> Rt;
2436 bits<17> addr;
2437 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2438 let Inst{19-16} = 0b1111;
2439 let Inst{15-12} = Rt;
2440 let Inst{11-0} = addr{11-0}; // imm12
2441}
2442
2443// Loads with zero extension
2444def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2445 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2446 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2447
2448// Loads with sign extension
2449def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2450 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2451 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2452
2453def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2454 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2455 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2456
85aaf69f 2457let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1a4d82fc
JJ		 2458 // Load doubleword
2459 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2460 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2461 Requires<[IsARM, HasV5TE]>;
223e47cc
LB		 2462}
2463
1a4d82fc
JJ		 2464def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2465 NoItinerary, "lda", "\t$Rt, $addr", []>;
2466def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2467 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2468def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2469 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2470
223e47cc
LB		 2471// Indexed loads
2472multiclass AI2_ldridx<bit isByte, string opc,
2473 InstrItinClass iii, InstrItinClass iir> {
2474 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1a4d82fc 2475 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
223e47cc
LB		 2476 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2477 bits<17> addr;
2478 let Inst{25} = 0;
2479 let Inst{23} = addr{12};
2480 let Inst{19-16} = addr{16-13};
2481 let Inst{11-0} = addr{11-0};
2482 let DecoderMethod = "DecodeLDRPreImm";
223e47cc
LB		 2483 }
2484
2485 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2486 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2487 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2488 bits<17> addr;
2489 let Inst{25} = 1;
2490 let Inst{23} = addr{12};
2491 let Inst{19-16} = addr{16-13};
2492 let Inst{11-0} = addr{11-0};
2493 let Inst{4} = 0;
2494 let DecoderMethod = "DecodeLDRPreReg";
223e47cc
LB		 2495 }
2496
2497 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2498 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2499 IndexModePost, LdFrm, iir,
2500 opc, "\t$Rt, $addr, $offset",
2501 "$addr.base = $Rn_wb", []> {
2502 // {12} isAdd
2503 // {11-0} imm12/Rm
2504 bits<14> offset;
2505 bits<4> addr;
2506 let Inst{25} = 1;
2507 let Inst{23} = offset{12};
2508 let Inst{19-16} = addr;
2509 let Inst{11-0} = offset{11-0};
1a4d82fc 2510 let Inst{4} = 0;
223e47cc
LB		 2511
2512 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2513 }
2514
2515 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2516 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2517 IndexModePost, LdFrm, iii,
2518 opc, "\t$Rt, $addr, $offset",
2519 "$addr.base = $Rn_wb", []> {
2520 // {12} isAdd
2521 // {11-0} imm12/Rm
2522 bits<14> offset;
2523 bits<4> addr;
2524 let Inst{25} = 0;
2525 let Inst{23} = offset{12};
2526 let Inst{19-16} = addr;
2527 let Inst{11-0} = offset{11-0};
2528
2529 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2530 }
2531
2532}
2533
85aaf69f 2534let mayLoad = 1, hasSideEffects = 0 in {
223e47cc
LB		 2535// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2536// IIC_iLoad_siu depending on whether it the offset register is shifted.
2537defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2538defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2539}
2540
2541multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2542 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1a4d82fc 2543 (ins addrmode3_pre:$addr), IndexModePre,
223e47cc
LB		 2544 LdMiscFrm, itin,
2545 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2546 bits<14> addr;
2547 let Inst{23} = addr{8}; // U bit
2548 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2549 let Inst{19-16} = addr{12-9}; // Rn
2550 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2551 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
223e47cc
LB		 2552 let DecoderMethod = "DecodeAddrMode3Instruction";
2553 }
2554 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2555 (ins addr_offset_none:$addr, am3offset:$offset),
2556 IndexModePost, LdMiscFrm, itin,
2557 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2558 []> {
2559 bits<10> offset;
2560 bits<4> addr;
2561 let Inst{23} = offset{8}; // U bit
2562 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2563 let Inst{19-16} = addr;
2564 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2565 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2566 let DecoderMethod = "DecodeAddrMode3Instruction";
2567 }
2568}
2569
85aaf69f 2570let mayLoad = 1, hasSideEffects = 0 in {
223e47cc
LB		 2571defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2572defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2573defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2574let hasExtraDefRegAllocReq = 1 in {
2575def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1a4d82fc 2576 (ins addrmode3_pre:$addr), IndexModePre,
223e47cc
LB		 2577 LdMiscFrm, IIC_iLoad_d_ru,
2578 "ldrd", "\t$Rt, $Rt2, $addr!",
2579 "$addr.base = $Rn_wb", []> {
2580 bits<14> addr;
2581 let Inst{23} = addr{8}; // U bit
2582 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2583 let Inst{19-16} = addr{12-9}; // Rn
2584 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2585 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2586 let DecoderMethod = "DecodeAddrMode3Instruction";
223e47cc
LB		 2587}
2588def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2589 (ins addr_offset_none:$addr, am3offset:$offset),
2590 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2591 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2592 "$addr.base = $Rn_wb", []> {
2593 bits<10> offset;
2594 bits<4> addr;
2595 let Inst{23} = offset{8}; // U bit
2596 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2597 let Inst{19-16} = addr;
2598 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2599 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2600 let DecoderMethod = "DecodeAddrMode3Instruction";
2601}
2602} // hasExtraDefRegAllocReq = 1
85aaf69f 2603} // mayLoad = 1, hasSideEffects = 0
223e47cc
LB		 2604
2605// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
85aaf69f 2606let mayLoad = 1, hasSideEffects = 0 in {
223e47cc
LB		 2607def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2608 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2609 IndexModePost, LdFrm, IIC_iLoad_ru,
2610 "ldrt", "\t$Rt, $addr, $offset",
2611 "$addr.base = $Rn_wb", []> {
2612 // {12} isAdd
2613 // {11-0} imm12/Rm
2614 bits<14> offset;
2615 bits<4> addr;
2616 let Inst{25} = 1;
2617 let Inst{23} = offset{12};
2618 let Inst{21} = 1; // overwrite
2619 let Inst{19-16} = addr;
2620 let Inst{11-5} = offset{11-5};
2621 let Inst{4} = 0;
2622 let Inst{3-0} = offset{3-0};
2623 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2624}
2625
1a4d82fc
JJ		 2626def LDRT_POST_IMM
2627 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2628 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2629 IndexModePost, LdFrm, IIC_iLoad_ru,
2630 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
223e47cc
LB		 2631 // {12} isAdd
2632 // {11-0} imm12/Rm
2633 bits<14> offset;
2634 bits<4> addr;
2635 let Inst{25} = 0;
2636 let Inst{23} = offset{12};
2637 let Inst{21} = 1; // overwrite
2638 let Inst{19-16} = addr;
2639 let Inst{11-0} = offset{11-0};
2640 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2641}
2642
2643def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2644 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2645 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2646 "ldrbt", "\t$Rt, $addr, $offset",
2647 "$addr.base = $Rn_wb", []> {
2648 // {12} isAdd
2649 // {11-0} imm12/Rm
2650 bits<14> offset;
2651 bits<4> addr;
2652 let Inst{25} = 1;
2653 let Inst{23} = offset{12};
2654 let Inst{21} = 1; // overwrite
2655 let Inst{19-16} = addr;
2656 let Inst{11-5} = offset{11-5};
2657 let Inst{4} = 0;
2658 let Inst{3-0} = offset{3-0};
2659 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2660}
2661
1a4d82fc
JJ		 2662def LDRBT_POST_IMM
2663 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2664 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2665 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2666 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
223e47cc
LB		 2667 // {12} isAdd
2668 // {11-0} imm12/Rm
2669 bits<14> offset;
2670 bits<4> addr;
2671 let Inst{25} = 0;
2672 let Inst{23} = offset{12};
2673 let Inst{21} = 1; // overwrite
2674 let Inst{19-16} = addr;
2675 let Inst{11-0} = offset{11-0};
2676 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2677}
2678
2679multiclass AI3ldrT<bits<4> op, string opc> {
2680 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2681 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2682 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2683 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2684 bits<9> offset;
2685 let Inst{23} = offset{8};
2686 let Inst{22} = 1;
2687 let Inst{11-8} = offset{7-4};
2688 let Inst{3-0} = offset{3-0};
223e47cc
LB		 2689 }
2690 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2691 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2692 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2693 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2694 bits<5> Rm;
2695 let Inst{23} = Rm{4};
2696 let Inst{22} = 0;
2697 let Inst{11-8} = 0;
2698 let Unpredictable{11-8} = 0b1111;
2699 let Inst{3-0} = Rm{3-0};
223e47cc
LB		 2700 let DecoderMethod = "DecodeLDR";
2701 }
2702}
2703
2704defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2705defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2706defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2707}
2708
1a4d82fc
JJ		 2709def LDRT_POST
2710 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2711 (outs GPR:$Rt)>;
2712
2713def LDRBT_POST
2714 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2715 (outs GPR:$Rt)>;
2716
223e47cc
LB		 2717// Store
2718
2719// Stores with truncate
2720def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2721 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2722 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2723
2724// Store doubleword
85aaf69f 2725let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
1a4d82fc
JJ		 2726 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2727 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2728 Requires<[IsARM, HasV5TE]> {
2729 let Inst{21} = 0;
2730 }
223e47cc
LB		 2731}
2732
2733// Indexed stores
2734multiclass AI2_stridx<bit isByte, string opc,
2735 InstrItinClass iii, InstrItinClass iir> {
2736 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
1a4d82fc 2737 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
223e47cc 2738 StFrm, iii,
1a4d82fc
JJ		 2739 opc, "\t$Rt, $addr!",
2740 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
223e47cc
LB		 2741 bits<17> addr;
2742 let Inst{25} = 0;
2743 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2744 let Inst{19-16} = addr{16-13}; // Rn
2745 let Inst{11-0} = addr{11-0}; // imm12
223e47cc
LB		 2746 let DecoderMethod = "DecodeSTRPreImm";
2747 }
2748
2749 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2750 (ins GPR:$Rt, ldst_so_reg:$addr),
2751 IndexModePre, StFrm, iir,
1a4d82fc
JJ		 2752 opc, "\t$Rt, $addr!",
2753 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
223e47cc
LB		 2754 bits<17> addr;
2755 let Inst{25} = 1;
2756 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2757 let Inst{19-16} = addr{16-13}; // Rn
2758 let Inst{11-0} = addr{11-0};
2759 let Inst{4} = 0; // Inst{4} = 0
223e47cc
LB		 2760 let DecoderMethod = "DecodeSTRPreReg";
2761 }
2762 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2763 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2764 IndexModePost, StFrm, iir,
2765 opc, "\t$Rt, $addr, $offset",
1a4d82fc 2766 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
223e47cc
LB		 2767 // {12} isAdd
2768 // {11-0} imm12/Rm
2769 bits<14> offset;
2770 bits<4> addr;
2771 let Inst{25} = 1;
2772 let Inst{23} = offset{12};
2773 let Inst{19-16} = addr;
2774 let Inst{11-0} = offset{11-0};
2775 let Inst{4} = 0;
2776
2777 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2778 }
2779
2780 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2781 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2782 IndexModePost, StFrm, iii,
2783 opc, "\t$Rt, $addr, $offset",
1a4d82fc 2784 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
223e47cc
LB		 2785 // {12} isAdd
2786 // {11-0} imm12/Rm
2787 bits<14> offset;
2788 bits<4> addr;
2789 let Inst{25} = 0;
2790 let Inst{23} = offset{12};
2791 let Inst{19-16} = addr;
2792 let Inst{11-0} = offset{11-0};
2793
2794 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2795 }
2796}
2797
85aaf69f 2798let mayStore = 1, hasSideEffects = 0 in {
223e47cc
LB		 2799// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2800// IIC_iStore_siu depending on whether it the offset register is shifted.
2801defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2802defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2803}
2804
2805def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2806 am2offset_reg:$offset),
2807 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2808 am2offset_reg:$offset)>;
2809def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2810 am2offset_imm:$offset),
2811 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2812 am2offset_imm:$offset)>;
2813def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2814 am2offset_reg:$offset),
2815 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2816 am2offset_reg:$offset)>;
2817def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2818 am2offset_imm:$offset),
2819 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2820 am2offset_imm:$offset)>;
2821
2822// Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2823// put the patterns on the instruction definitions directly as ISel wants
2824// the address base and offset to be separate operands, not a single
2825// complex operand like we represent the instructions themselves. The
2826// pseudos map between the two.
2827let usesCustomInserter = 1,
2828 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2829def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2830 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2831 4, IIC_iStore_ru,
2832 [(set GPR:$Rn_wb,
2833 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2834def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2835 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2836 4, IIC_iStore_ru,
2837 [(set GPR:$Rn_wb,
2838 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2839def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2840 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2841 4, IIC_iStore_ru,
2842 [(set GPR:$Rn_wb,
2843 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2844def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2845 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2846 4, IIC_iStore_ru,
2847 [(set GPR:$Rn_wb,
2848 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2849def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2850 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2851 4, IIC_iStore_ru,
2852 [(set GPR:$Rn_wb,
2853 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2854}
2855
2856
2857
2858def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1a4d82fc 2859 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
223e47cc 2860 StMiscFrm, IIC_iStore_bh_ru,
1a4d82fc
JJ		 2861 "strh", "\t$Rt, $addr!",
2862 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
223e47cc
LB		 2863 bits<14> addr;
2864 let Inst{23} = addr{8}; // U bit
2865 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2866 let Inst{19-16} = addr{12-9}; // Rn
2867 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2868 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
223e47cc
LB		 2869 let DecoderMethod = "DecodeAddrMode3Instruction";
2870}
2871
2872def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2873 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2874 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1a4d82fc
JJ		 2875 "strh", "\t$Rt, $addr, $offset",
2876 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
223e47cc
LB		 2877 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2878 addr_offset_none:$addr,
2879 am3offset:$offset))]> {
2880 bits<10> offset;
2881 bits<4> addr;
2882 let Inst{23} = offset{8}; // U bit
2883 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2884 let Inst{19-16} = addr;
2885 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2886 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2887 let DecoderMethod = "DecodeAddrMode3Instruction";
2888}
2889
85aaf69f 2890let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
223e47cc 2891def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
1a4d82fc 2892 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
223e47cc
LB		 2893 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2894 "strd", "\t$Rt, $Rt2, $addr!",
2895 "$addr.base = $Rn_wb", []> {
2896 bits<14> addr;
2897 let Inst{23} = addr{8}; // U bit
2898 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2899 let Inst{19-16} = addr{12-9}; // Rn
2900 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2901 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2902 let DecoderMethod = "DecodeAddrMode3Instruction";
223e47cc
LB		 2903}
2904
2905def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2906 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2907 am3offset:$offset),
2908 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2909 "strd", "\t$Rt, $Rt2, $addr, $offset",
2910 "$addr.base = $Rn_wb", []> {
2911 bits<10> offset;
2912 bits<4> addr;
2913 let Inst{23} = offset{8}; // U bit
2914 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2915 let Inst{19-16} = addr;
2916 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2917 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2918 let DecoderMethod = "DecodeAddrMode3Instruction";
2919}
85aaf69f 2920} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
223e47cc
LB		 2921
2922// STRT, STRBT, and STRHT
2923
2924def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2925 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2926 IndexModePost, StFrm, IIC_iStore_bh_ru,
2927 "strbt", "\t$Rt, $addr, $offset",
2928 "$addr.base = $Rn_wb", []> {
2929 // {12} isAdd
2930 // {11-0} imm12/Rm
2931 bits<14> offset;
2932 bits<4> addr;
2933 let Inst{25} = 1;
2934 let Inst{23} = offset{12};
2935 let Inst{21} = 1; // overwrite
2936 let Inst{19-16} = addr;
2937 let Inst{11-5} = offset{11-5};
2938 let Inst{4} = 0;
2939 let Inst{3-0} = offset{3-0};
2940 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2941}
2942
1a4d82fc
JJ		 2943def STRBT_POST_IMM
2944 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2945 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2946 IndexModePost, StFrm, IIC_iStore_bh_ru,
2947 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
223e47cc
LB		 2948 // {12} isAdd
2949 // {11-0} imm12/Rm
2950 bits<14> offset;
2951 bits<4> addr;
2952 let Inst{25} = 0;
2953 let Inst{23} = offset{12};
2954 let Inst{21} = 1; // overwrite
2955 let Inst{19-16} = addr;
2956 let Inst{11-0} = offset{11-0};
2957 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2958}
2959
1a4d82fc
JJ		 2960def STRBT_POST
2961 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2962 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2963
85aaf69f 2964let mayStore = 1, hasSideEffects = 0 in {
223e47cc
LB		 2965def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2966 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2967 IndexModePost, StFrm, IIC_iStore_ru,
2968 "strt", "\t$Rt, $addr, $offset",
2969 "$addr.base = $Rn_wb", []> {
2970 // {12} isAdd
2971 // {11-0} imm12/Rm
2972 bits<14> offset;
2973 bits<4> addr;
2974 let Inst{25} = 1;
2975 let Inst{23} = offset{12};
2976 let Inst{21} = 1; // overwrite
2977 let Inst{19-16} = addr;
2978 let Inst{11-5} = offset{11-5};
2979 let Inst{4} = 0;
2980 let Inst{3-0} = offset{3-0};
2981 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2982}
2983
1a4d82fc
JJ		 2984def STRT_POST_IMM
2985 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2986 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2987 IndexModePost, StFrm, IIC_iStore_ru,
2988 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
223e47cc
LB		 2989 // {12} isAdd
2990 // {11-0} imm12/Rm
2991 bits<14> offset;
2992 bits<4> addr;
2993 let Inst{25} = 0;
2994 let Inst{23} = offset{12};
2995 let Inst{21} = 1; // overwrite
2996 let Inst{19-16} = addr;
2997 let Inst{11-0} = offset{11-0};
2998 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2999}
3000}
3001
1a4d82fc
JJ		 3002def STRT_POST
3003 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3004 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
223e47cc
LB		 3005
3006multiclass AI3strT<bits<4> op, string opc> {
3007 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3008 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3009 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3010 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3011 bits<9> offset;
3012 let Inst{23} = offset{8};
3013 let Inst{22} = 1;
3014 let Inst{11-8} = offset{7-4};
3015 let Inst{3-0} = offset{3-0};
223e47cc
LB		 3016 }
3017 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3018 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3019 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3020 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3021 bits<5> Rm;
3022 let Inst{23} = Rm{4};
3023 let Inst{22} = 0;
3024 let Inst{11-8} = 0;
3025 let Inst{3-0} = Rm{3-0};
223e47cc
LB		 3026 }
3027}
3028
3029
3030defm STRHT : AI3strT<0b1011, "strht">;
3031
1a4d82fc
JJ		 3032def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3033 NoItinerary, "stl", "\t$Rt, $addr", []>;
3034def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3035 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3036def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3037 NoItinerary, "stlh", "\t$Rt, $addr", []>;
223e47cc
LB		 3038
3039//===----------------------------------------------------------------------===//
3040// Load / store multiple Instructions.
3041//
3042
3043multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3044 InstrItinClass itin, InstrItinClass itin_upd> {
3045 // IA is the default, so no need for an explicit suffix on the
3046 // mnemonic here. Without it is the canonical spelling.
3047 def IA :
3048 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3049 IndexModeNone, f, itin,
3050 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3051 let Inst{24-23} = 0b01; // Increment After
3052 let Inst{22} = P_bit;
3053 let Inst{21} = 0; // No writeback
3054 let Inst{20} = L_bit;
3055 }
3056 def IA_UPD :
3057 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3058 IndexModeUpd, f, itin_upd,
3059 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3060 let Inst{24-23} = 0b01; // Increment After
3061 let Inst{22} = P_bit;
3062 let Inst{21} = 1; // Writeback
3063 let Inst{20} = L_bit;
3064
3065 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3066 }
3067 def DA :
3068 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3069 IndexModeNone, f, itin,
3070 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3071 let Inst{24-23} = 0b00; // Decrement After
3072 let Inst{22} = P_bit;
3073 let Inst{21} = 0; // No writeback
3074 let Inst{20} = L_bit;
3075 }
3076 def DA_UPD :
3077 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3078 IndexModeUpd, f, itin_upd,
3079 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3080 let Inst{24-23} = 0b00; // Decrement After
3081 let Inst{22} = P_bit;
3082 let Inst{21} = 1; // Writeback
3083 let Inst{20} = L_bit;
3084
3085 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3086 }
3087 def DB :
3088 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3089 IndexModeNone, f, itin,
3090 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3091 let Inst{24-23} = 0b10; // Decrement Before
3092 let Inst{22} = P_bit;
3093 let Inst{21} = 0; // No writeback
3094 let Inst{20} = L_bit;
3095 }
3096 def DB_UPD :
3097 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3098 IndexModeUpd, f, itin_upd,
3099 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3100 let Inst{24-23} = 0b10; // Decrement Before
3101 let Inst{22} = P_bit;
3102 let Inst{21} = 1; // Writeback
3103 let Inst{20} = L_bit;
3104
3105 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3106 }
3107 def IB :
3108 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3109 IndexModeNone, f, itin,
3110 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3111 let Inst{24-23} = 0b11; // Increment Before
3112 let Inst{22} = P_bit;
3113 let Inst{21} = 0; // No writeback
3114 let Inst{20} = L_bit;
3115 }
3116 def IB_UPD :
3117 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3118 IndexModeUpd, f, itin_upd,
3119 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3120 let Inst{24-23} = 0b11; // Increment Before
3121 let Inst{22} = P_bit;
3122 let Inst{21} = 1; // Writeback
3123 let Inst{20} = L_bit;
3124
3125 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3126 }
3127}
3128
85aaf69f 3129let hasSideEffects = 0 in {
223e47cc
LB		 3130
3131let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3132defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
85aaf69f 3133 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
223e47cc
LB		 3134
3135let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3136defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
85aaf69f
SL		 3137 IIC_iStore_mu>,
3138 ComplexDeprecationPredicate<"ARMStore">;
223e47cc 3139
85aaf69f 3140} // hasSideEffects
223e47cc
LB		 3141
3142// FIXME: remove when we have a way to marking a MI with these properties.
3143// FIXME: Should pc be an implicit operand like PICADD, etc?
3144let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3145 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3146def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3147 reglist:$regs, variable_ops),
3148 4, IIC_iLoad_mBr, [],
3149 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3150 RegConstraint<"$Rn = $wb">;
3151
3152let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3153defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3154 IIC_iLoad_mu>;
3155
3156let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3157defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3158 IIC_iStore_mu>;
3159
3160
3161
3162//===----------------------------------------------------------------------===//
3163// Move Instructions.
3164//
3165
85aaf69f 3166let hasSideEffects = 0 in
223e47cc 3167def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1a4d82fc 3168 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3169 bits<4> Rd;
3170 bits<4> Rm;
3171
3172 let Inst{19-16} = 0b0000;
3173 let Inst{11-4} = 0b00000000;
3174 let Inst{25} = 0;
3175 let Inst{3-0} = Rm;
3176 let Inst{15-12} = Rd;
3177}
3178
3179// A version for the smaller set of tail call registers.
85aaf69f 3180let hasSideEffects = 0 in
223e47cc 3181def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1a4d82fc 3182 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3183 bits<4> Rd;
3184 bits<4> Rm;
3185
3186 let Inst{11-4} = 0b00000000;
3187 let Inst{25} = 0;
3188 let Inst{3-0} = Rm;
3189 let Inst{15-12} = Rd;
3190}
3191
3192def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3193 DPSoRegRegFrm, IIC_iMOVsr,
3194 "mov", "\t$Rd, $src",
1a4d82fc
JJ		 3195 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3196 Sched<[WriteALU]> {
223e47cc
LB		 3197 bits<4> Rd;
3198 bits<12> src;
3199 let Inst{15-12} = Rd;
3200 let Inst{19-16} = 0b0000;
3201 let Inst{11-8} = src{11-8};
3202 let Inst{7} = 0;
3203 let Inst{6-5} = src{6-5};
3204 let Inst{4} = 1;
3205 let Inst{3-0} = src{3-0};
3206 let Inst{25} = 0;
3207}
3208
3209def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3210 DPSoRegImmFrm, IIC_iMOVsr,
3211 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
1a4d82fc 3212 UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3213 bits<4> Rd;
3214 bits<12> src;
3215 let Inst{15-12} = Rd;
3216 let Inst{19-16} = 0b0000;
3217 let Inst{11-5} = src{11-5};
3218 let Inst{4} = 0;
3219 let Inst{3-0} = src{3-0};
3220 let Inst{25} = 0;
3221}
3222
3223let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
85aaf69f
SL		 3224def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3225 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
1a4d82fc 3226 Sched<[WriteALU]> {
223e47cc
LB		 3227 bits<4> Rd;
3228 bits<12> imm;
3229 let Inst{25} = 1;
3230 let Inst{15-12} = Rd;
3231 let Inst{19-16} = 0b0000;
3232 let Inst{11-0} = imm;
3233}
3234
3235let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3236def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3237 DPFrm, IIC_iMOVi,
3238 "movw", "\t$Rd, $imm",
3239 [(set GPR:$Rd, imm0_65535:$imm)]>,
1a4d82fc 3240 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3241 bits<4> Rd;
3242 bits<16> imm;
3243 let Inst{15-12} = Rd;
3244 let Inst{11-0} = imm{11-0};
3245 let Inst{19-16} = imm{15-12};
3246 let Inst{20} = 0;
3247 let Inst{25} = 1;
3248 let DecoderMethod = "DecodeArmMOVTWInstruction";
3249}
3250
3251def : InstAlias<"mov${p} $Rd, $imm",
3252 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3253 Requires<[IsARM]>;
3254
3255def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
1a4d82fc
JJ		 3256 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3257 Sched<[WriteALU]>;
223e47cc
LB		 3258
3259let Constraints = "$src = $Rd" in {
3260def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3261 (ins GPR:$src, imm0_65535_expr:$imm),
3262 DPFrm, IIC_iMOVi,
3263 "movt", "\t$Rd, $imm",
3264 [(set GPRnopc:$Rd,
3265 (or (and GPR:$src, 0xffff),
3266 lo16AllZero:$imm))]>, UnaryDP,
1a4d82fc 3267 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
223e47cc
LB		 3268 bits<4> Rd;
3269 bits<16> imm;
3270 let Inst{15-12} = Rd;
3271 let Inst{11-0} = imm{11-0};
3272 let Inst{19-16} = imm{15-12};
3273 let Inst{20} = 0;
3274 let Inst{25} = 1;
3275 let DecoderMethod = "DecodeArmMOVTWInstruction";
3276}
3277
3278def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
1a4d82fc
JJ		 3279 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3280 Sched<[WriteALU]>;
223e47cc
LB		 3281
3282} // Constraints
3283
3284def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3285 Requires<[IsARM, HasV6T2]>;
3286
3287let Uses = [CPSR] in
3288def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3289 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1a4d82fc 3290 Requires<[IsARM]>, Sched<[WriteALU]>;
223e47cc
LB		 3291
3292// These aren't really mov instructions, but we have to define them this way
3293// due to flag operands.
3294
3295let Defs = [CPSR] in {
3296def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3297 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1a4d82fc 3298 Sched<[WriteALU]>, Requires<[IsARM]>;
223e47cc
LB		 3299def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3300 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1a4d82fc 3301 Sched<[WriteALU]>, Requires<[IsARM]>;
223e47cc
LB		 3302}
3303
3304//===----------------------------------------------------------------------===//
3305// Extend Instructions.
3306//
3307
3308// Sign extenders
3309
3310def SXTB : AI_ext_rrot<0b01101010,
3311 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3312def SXTH : AI_ext_rrot<0b01101011,
3313 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3314
3315def SXTAB : AI_exta_rrot<0b01101010,
3316 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3317def SXTAH : AI_exta_rrot<0b01101011,
3318 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3319
3320def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3321
3322def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3323
3324// Zero extenders
3325
3326let AddedComplexity = 16 in {
3327def UXTB : AI_ext_rrot<0b01101110,
3328 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3329def UXTH : AI_ext_rrot<0b01101111,
3330 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3331def UXTB16 : AI_ext_rrot<0b01101100,
3332 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3333
3334// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3335// The transformation should probably be done as a combiner action
3336// instead so we can include a check for masking back in the upper
3337// eight bits of the source into the lower eight bits of the result.
3338//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3339// (UXTB16r_rot GPR:$Src, 3)>;
3340def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3341 (UXTB16 GPR:$Src, 1)>;
3342
3343def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3344 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3345def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3346 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3347}
3348
3349// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3350def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3351
3352
3353def SBFX : I<(outs GPRnopc:$Rd),
3354 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3355 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3356 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3357 Requires<[IsARM, HasV6T2]> {
3358 bits<4> Rd;
3359 bits<4> Rn;
3360 bits<5> lsb;
3361 bits<5> width;
3362 let Inst{27-21} = 0b0111101;
3363 let Inst{6-4} = 0b101;
3364 let Inst{20-16} = width;
3365 let Inst{15-12} = Rd;
3366 let Inst{11-7} = lsb;
3367 let Inst{3-0} = Rn;
3368}
3369
1a4d82fc
JJ		 3370def UBFX : I<(outs GPRnopc:$Rd),
3371 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
223e47cc
LB		 3372 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3373 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3374 Requires<[IsARM, HasV6T2]> {
3375 bits<4> Rd;
3376 bits<4> Rn;
3377 bits<5> lsb;
3378 bits<5> width;
3379 let Inst{27-21} = 0b0111111;
3380 let Inst{6-4} = 0b101;
3381 let Inst{20-16} = width;
3382 let Inst{15-12} = Rd;
3383 let Inst{11-7} = lsb;
3384 let Inst{3-0} = Rn;
3385}
3386
3387//===----------------------------------------------------------------------===//
3388// Arithmetic Instructions.
3389//
3390
3391defm ADD : AsI1_bin_irs<0b0100, "add",
3392 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3393 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3394defm SUB : AsI1_bin_irs<0b0010, "sub",
3395 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3396 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3397
3398// ADD and SUB with 's' bit set.
3399//
3400// Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3401// selection DAG. They are "lowered" to real ADD/SUB opcodes by
3402// AdjustInstrPostInstrSelection where we determine whether or not to
3403// set the "s" bit based on CPSR liveness.
3404//
3405// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3406// support for an optional CPSR definition that corresponds to the DAG
3407// node's second value. We can then eliminate the implicit def of CPSR.
3408defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3409 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3410defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3411 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3412
3413defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3414 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3415defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3416 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3417
3418defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3419 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3420 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3421
3422// FIXME: Eliminate them if we can write def : Pat patterns which defines
3423// CPSR and the implicit def of CPSR is not needed.
3424defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3425 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3426
3427defm RSC : AI1_rsc_irs<0b0111, "rsc",
3428 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3429
3430// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3431// The assume-no-carry-in form uses the negation of the input since add/sub
3432// assume opposite meanings of the carry flag (i.e., carry == !borrow).
3433// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3434// details.
85aaf69f
SL		 3435def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3436 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3437def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3438 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
223e47cc
LB		 3439
3440def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3441 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3442 Requires<[IsARM, HasV6T2]>;
3443def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3444 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3445 Requires<[IsARM, HasV6T2]>;
3446
3447// The with-carry-in form matches bitwise not instead of the negation.
3448// Effectively, the inverse interpretation of the carry flag already accounts
3449// for part of the negation.
85aaf69f
SL		 3450def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3451 (SBCri GPR:$src, mod_imm_not:$imm)>;
970d7e83 3452def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
1a4d82fc
JJ		 3453 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3454 Requires<[IsARM, HasV6T2]>;
223e47cc
LB		 3455
3456// Note: These are implemented in C++ code, because they have to generate
3457// ADD/SUBrs instructions, which use a complex pattern that a xform function
3458// cannot produce.
3459// (mul X, 2^n+1) -> (add (X << n), X)
3460// (mul X, 2^n-1) -> (rsb X, (X << n))
3461
3462// ARM Arithmetic Instruction
3463// GPR:$dst = GPR:$a op GPR:$b
3464class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3465 list<dag> pattern = [],
3466 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3467 string asm = "\t$Rd, $Rn, $Rm">
1a4d82fc
JJ		 3468 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3469 Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 3470 bits<4> Rn;
3471 bits<4> Rd;
3472 bits<4> Rm;
3473 let Inst{27-20} = op27_20;
3474 let Inst{11-4} = op11_4;
3475 let Inst{19-16} = Rn;
3476 let Inst{15-12} = Rd;
3477 let Inst{3-0} = Rm;
3478
3479 let Unpredictable{11-8} = 0b1111;
3480}
3481
3482// Saturating add/subtract
3483
1a4d82fc 3484let DecoderMethod = "DecodeQADDInstruction" in
223e47cc
LB		 3485def QADD : AAI<0b00010000, 0b00000101, "qadd",
3486 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3487 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
1a4d82fc 3488
223e47cc
LB		 3489def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3490 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3491 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3492def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3493 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3494 "\t$Rd, $Rm, $Rn">;
3495def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3496 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3497 "\t$Rd, $Rm, $Rn">;
3498
3499def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3500def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3501def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3502def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3503def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3504def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3505def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3506def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3507def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3508def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3509def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3510def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3511
3512// Signed/Unsigned add/subtract
3513
3514def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3515def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3516def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3517def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3518def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3519def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3520def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3521def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3522def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3523def USAX : AAI<0b01100101, 0b11110101, "usax">;
3524def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3525def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3526
3527// Signed/Unsigned halving add/subtract
3528
3529def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3530def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3531def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3532def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3533def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3534def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3535def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3536def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3537def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3538def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3539def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3540def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3541
3542// Unsigned Sum of Absolute Differences [and Accumulate].
3543
3544def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3545 MulFrm /* for convenience */, NoItinerary, "usad8",
3546 "\t$Rd, $Rn, $Rm", []>,
1a4d82fc 3547 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
223e47cc
LB		 3548 bits<4> Rd;
3549 bits<4> Rn;
3550 bits<4> Rm;
3551 let Inst{27-20} = 0b01111000;
3552 let Inst{15-12} = 0b1111;
3553 let Inst{7-4} = 0b0001;
3554 let Inst{19-16} = Rd;
3555 let Inst{11-8} = Rm;
3556 let Inst{3-0} = Rn;
3557}
3558def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3559 MulFrm /* for convenience */, NoItinerary, "usada8",
3560 "\t$Rd, $Rn, $Rm, $Ra", []>,
1a4d82fc 3561 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
223e47cc
LB		 3562 bits<4> Rd;
3563 bits<4> Rn;
3564 bits<4> Rm;
3565 bits<4> Ra;
3566 let Inst{27-20} = 0b01111000;
3567 let Inst{7-4} = 0b0001;
3568 let Inst{19-16} = Rd;
3569 let Inst{15-12} = Ra;
3570 let Inst{11-8} = Rm;
3571 let Inst{3-0} = Rn;
3572}
3573
3574// Signed/Unsigned saturate
3575
3576def SSAT : AI<(outs GPRnopc:$Rd),
3577 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3578 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3579 bits<4> Rd;
3580 bits<5> sat_imm;
3581 bits<4> Rn;
3582 bits<8> sh;
3583 let Inst{27-21} = 0b0110101;
3584 let Inst{5-4} = 0b01;
3585 let Inst{20-16} = sat_imm;
3586 let Inst{15-12} = Rd;
3587 let Inst{11-7} = sh{4-0};
3588 let Inst{6} = sh{5};
3589 let Inst{3-0} = Rn;
3590}
3591
3592def SSAT16 : AI<(outs GPRnopc:$Rd),
3593 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3594 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3595 bits<4> Rd;
3596 bits<4> sat_imm;
3597 bits<4> Rn;
3598 let Inst{27-20} = 0b01101010;
3599 let Inst{11-4} = 0b11110011;
3600 let Inst{15-12} = Rd;
3601 let Inst{19-16} = sat_imm;
3602 let Inst{3-0} = Rn;
3603}
3604
3605def USAT : AI<(outs GPRnopc:$Rd),
3606 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3607 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3608 bits<4> Rd;
3609 bits<5> sat_imm;
3610 bits<4> Rn;
3611 bits<8> sh;
3612 let Inst{27-21} = 0b0110111;
3613 let Inst{5-4} = 0b01;
3614 let Inst{15-12} = Rd;
3615 let Inst{11-7} = sh{4-0};
3616 let Inst{6} = sh{5};
3617 let Inst{20-16} = sat_imm;
3618 let Inst{3-0} = Rn;
3619}
3620
3621def USAT16 : AI<(outs GPRnopc:$Rd),
3622 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3623 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3624 bits<4> Rd;
3625 bits<4> sat_imm;
3626 bits<4> Rn;
3627 let Inst{27-20} = 0b01101110;
3628 let Inst{11-4} = 0b11110011;
3629 let Inst{15-12} = Rd;
3630 let Inst{19-16} = sat_imm;
3631 let Inst{3-0} = Rn;
3632}
3633
3634def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3635 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3636def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3637 (USAT imm:$pos, GPRnopc:$a, 0)>;
3638
3639//===----------------------------------------------------------------------===//
3640// Bitwise Instructions.
3641//
3642
3643defm AND : AsI1_bin_irs<0b0000, "and",
3644 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3645 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3646defm ORR : AsI1_bin_irs<0b1100, "orr",
3647 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3648 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3649defm EOR : AsI1_bin_irs<0b0001, "eor",
3650 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3651 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3652defm BIC : AsI1_bin_irs<0b1110, "bic",
3653 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3654 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3655
3656// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3657// like in the actual instruction encoding. The complexity of mapping the mask
3658// to the lsb/msb pair should be handled by ISel, not encapsulated in the
3659// instruction description.
3660def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3661 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3662 "bfc", "\t$Rd, $imm", "$src = $Rd",
3663 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3664 Requires<[IsARM, HasV6T2]> {
3665 bits<4> Rd;
3666 bits<10> imm;
3667 let Inst{27-21} = 0b0111110;
3668 let Inst{6-0} = 0b0011111;
3669 let Inst{15-12} = Rd;
3670 let Inst{11-7} = imm{4-0}; // lsb
3671 let Inst{20-16} = imm{9-5}; // msb
3672}
3673
3674// A8.6.18 BFI - Bitfield insert (Encoding A1)
3675def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3676 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3677 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3678 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3679 bf_inv_mask_imm:$imm))]>,
3680 Requires<[IsARM, HasV6T2]> {
3681 bits<4> Rd;
3682 bits<4> Rn;
3683 bits<10> imm;
3684 let Inst{27-21} = 0b0111110;
3685 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3686 let Inst{15-12} = Rd;
3687 let Inst{11-7} = imm{4-0}; // lsb
3688 let Inst{20-16} = imm{9-5}; // width
3689 let Inst{3-0} = Rn;
3690}
3691
3692def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3693 "mvn", "\t$Rd, $Rm",
1a4d82fc 3694 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3695 bits<4> Rd;
3696 bits<4> Rm;
3697 let Inst{25} = 0;
3698 let Inst{19-16} = 0b0000;
3699 let Inst{11-4} = 0b00000000;
3700 let Inst{15-12} = Rd;
3701 let Inst{3-0} = Rm;
3702}
3703def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3704 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
1a4d82fc
JJ		 3705 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3706 Sched<[WriteALU]> {
223e47cc
LB		 3707 bits<4> Rd;
3708 bits<12> shift;
3709 let Inst{25} = 0;
3710 let Inst{19-16} = 0b0000;
3711 let Inst{15-12} = Rd;
3712 let Inst{11-5} = shift{11-5};
3713 let Inst{4} = 0;
3714 let Inst{3-0} = shift{3-0};
3715}
3716def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3717 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
1a4d82fc
JJ		 3718 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3719 Sched<[WriteALU]> {
223e47cc
LB		 3720 bits<4> Rd;
3721 bits<12> shift;
3722 let Inst{25} = 0;
3723 let Inst{19-16} = 0b0000;
3724 let Inst{15-12} = Rd;
3725 let Inst{11-8} = shift{11-8};
3726 let Inst{7} = 0;
3727 let Inst{6-5} = shift{6-5};
3728 let Inst{4} = 1;
3729 let Inst{3-0} = shift{3-0};
3730}
3731let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
85aaf69f 3732def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
223e47cc 3733 IIC_iMVNi, "mvn", "\t$Rd, $imm",
85aaf69f 3734 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
223e47cc
LB		 3735 bits<4> Rd;
3736 bits<12> imm;
3737 let Inst{25} = 1;
3738 let Inst{19-16} = 0b0000;
3739 let Inst{15-12} = Rd;
3740 let Inst{11-0} = imm;
3741}
3742
85aaf69f
SL		 3743def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3744 (BICri GPR:$src, mod_imm_not:$imm)>;
223e47cc
LB		 3745
3746//===----------------------------------------------------------------------===//
3747// Multiply Instructions.
3748//
3749class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3750 string opc, string asm, list<dag> pattern>
3751 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3752 bits<4> Rd;
3753 bits<4> Rm;
3754 bits<4> Rn;
3755 let Inst{19-16} = Rd;
3756 let Inst{11-8} = Rm;
3757 let Inst{3-0} = Rn;
3758}
3759class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3760 string opc, string asm, list<dag> pattern>
3761 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3762 bits<4> RdLo;
3763 bits<4> RdHi;
3764 bits<4> Rm;
3765 bits<4> Rn;
3766 let Inst{19-16} = RdHi;
3767 let Inst{15-12} = RdLo;
3768 let Inst{11-8} = Rm;
3769 let Inst{3-0} = Rn;
3770}
3771class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3772 string opc, string asm, list<dag> pattern>
3773 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3774 bits<4> RdLo;
3775 bits<4> RdHi;
3776 bits<4> Rm;
3777 bits<4> Rn;
3778 let Inst{19-16} = RdHi;
3779 let Inst{15-12} = RdLo;
3780 let Inst{11-8} = Rm;
3781 let Inst{3-0} = Rn;
3782}
3783
3784// FIXME: The v5 pseudos are only necessary for the additional Constraint
3785// property. Remove them when it's possible to add those properties
3786// on an individual MachineInstr, not just an instruction description.
3787let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3788def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3790 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3791 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3792 Requires<[IsARM, HasV6]> {
3793 let Inst{15-12} = 0b0000;
3794 let Unpredictable{15-12} = 0b1111;
3795}
3796
3797let Constraints = "@earlyclobber $Rd" in
3798def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3799 pred:$p, cc_out:$s),
3800 4, IIC_iMUL32,
3801 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3802 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3803 Requires<[IsARM, NoV6, UseMulOps]>;
3804}
3805
1a4d82fc
JJ		 3806def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3807 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
223e47cc 3808 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
1a4d82fc
JJ		 3809 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3810 Requires<[IsARM, HasV6, UseMulOps]> {
223e47cc
LB		 3811 bits<4> Ra;
3812 let Inst{15-12} = Ra;
3813}
3814
3815let Constraints = "@earlyclobber $Rd" in
1a4d82fc
JJ		 3816def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3817 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3818 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3819 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3820 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3821 Requires<[IsARM, NoV6]>;
223e47cc
LB		 3822
3823def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3824 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3825 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3826 Requires<[IsARM, HasV6T2, UseMulOps]> {
3827 bits<4> Rd;
3828 bits<4> Rm;
3829 bits<4> Rn;
3830 bits<4> Ra;
3831 let Inst{19-16} = Rd;
3832 let Inst{15-12} = Ra;
3833 let Inst{11-8} = Rm;
3834 let Inst{3-0} = Rn;
3835}
3836
3837// Extra precision multiplies with low / high results
85aaf69f 3838let hasSideEffects = 0 in {
223e47cc
LB		 3839let isCommutable = 1 in {
3840def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3841 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3842 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3843 Requires<[IsARM, HasV6]>;
3844
3845def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3846 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3847 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3848 Requires<[IsARM, HasV6]>;
3849
3850let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3851def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3852 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3853 4, IIC_iMUL64, [],
3854 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3855 Requires<[IsARM, NoV6]>;
3856
3857def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3858 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3859 4, IIC_iMUL64, [],
3860 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3861 Requires<[IsARM, NoV6]>;
3862}
3863}
3864
3865// Multiply + accumulate
3866def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3867 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3868 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3869 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3870def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3871 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3872 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3873 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3874
3875def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3876 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3877 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3878 Requires<[IsARM, HasV6]> {
3879 bits<4> RdLo;
3880 bits<4> RdHi;
3881 bits<4> Rm;
3882 bits<4> Rn;
3883 let Inst{19-16} = RdHi;
3884 let Inst{15-12} = RdLo;
3885 let Inst{11-8} = Rm;
3886 let Inst{3-0} = Rn;
3887}
3888
1a4d82fc
JJ		 3889let Constraints =
3890 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
223e47cc
LB		 3891def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3892 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3893 4, IIC_iMAC64, [],
3894 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3895 pred:$p, cc_out:$s)>,
3896 Requires<[IsARM, NoV6]>;
3897def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3898 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3899 4, IIC_iMAC64, [],
3900 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3901 pred:$p, cc_out:$s)>,
3902 Requires<[IsARM, NoV6]>;
3903}
3904
85aaf69f 3905} // hasSideEffects
223e47cc
LB		 3906
3907// Most significant word multiply
3908def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3909 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3910 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3911 Requires<[IsARM, HasV6]> {
3912 let Inst{15-12} = 0b1111;
3913}
3914
3915def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3916 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3917 Requires<[IsARM, HasV6]> {
3918 let Inst{15-12} = 0b1111;
3919}
3920
3921def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3922 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3923 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3924 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3925 Requires<[IsARM, HasV6, UseMulOps]>;
3926
3927def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3928 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3929 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3930 Requires<[IsARM, HasV6]>;
3931
3932def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3933 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3934 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3935 Requires<[IsARM, HasV6, UseMulOps]>;
3936
3937def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3938 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3939 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3940 Requires<[IsARM, HasV6]>;
3941
3942multiclass AI_smul<string opc, PatFrag opnode> {
3943 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3944 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3945 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3946 (sext_inreg GPR:$Rm, i16)))]>,
3947 Requires<[IsARM, HasV5TE]>;
3948
3949 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3950 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3951 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3952 (sra GPR:$Rm, (i32 16))))]>,
3953 Requires<[IsARM, HasV5TE]>;
3954
3955 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3956 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3957 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3958 (sext_inreg GPR:$Rm, i16)))]>,
3959 Requires<[IsARM, HasV5TE]>;
3960
3961 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3962 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3963 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3964 (sra GPR:$Rm, (i32 16))))]>,
3965 Requires<[IsARM, HasV5TE]>;
3966
3967 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3968 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
85aaf69f 3969 []>,
223e47cc
LB		 3970 Requires<[IsARM, HasV5TE]>;
3971
3972 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3973 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
85aaf69f 3974 []>,
223e47cc
LB		 3975 Requires<[IsARM, HasV5TE]>;
3976}
3977
3978
3979multiclass AI_smla<string opc, PatFrag opnode> {
3980 let DecoderMethod = "DecodeSMLAInstruction" in {
3981 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3982 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3983 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3984 [(set GPRnopc:$Rd, (add GPR:$Ra,
3985 (opnode (sext_inreg GPRnopc:$Rn, i16),
3986 (sext_inreg GPRnopc:$Rm, i16))))]>,
3987 Requires<[IsARM, HasV5TE, UseMulOps]>;
3988
3989 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3990 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3991 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3992 [(set GPRnopc:$Rd,
3993 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3994 (sra GPRnopc:$Rm, (i32 16)))))]>,
3995 Requires<[IsARM, HasV5TE, UseMulOps]>;
3996
3997 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3998 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3999 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4000 [(set GPRnopc:$Rd,
4001 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4002 (sext_inreg GPRnopc:$Rm, i16))))]>,
4003 Requires<[IsARM, HasV5TE, UseMulOps]>;
4004
4005 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4006 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4007 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4008 [(set GPRnopc:$Rd,
4009 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4010 (sra GPRnopc:$Rm, (i32 16)))))]>,
4011 Requires<[IsARM, HasV5TE, UseMulOps]>;
4012
4013 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4014 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4015 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
85aaf69f 4016 []>,
223e47cc
LB		 4017 Requires<[IsARM, HasV5TE, UseMulOps]>;
4018
4019 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4020 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4021 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
85aaf69f 4022 []>,
223e47cc
LB		 4023 Requires<[IsARM, HasV5TE, UseMulOps]>;
4024 }
4025}
4026
4027defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4028defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4029
4030// Halfword multiply accumulate long: SMLAL<x><y>.
4031def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4032 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4033 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4034 Requires<[IsARM, HasV5TE]>;
4035
4036def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4037 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4038 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4039 Requires<[IsARM, HasV5TE]>;
4040
4041def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4042 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4043 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4044 Requires<[IsARM, HasV5TE]>;
4045
4046def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4047 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4048 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4049 Requires<[IsARM, HasV5TE]>;
4050
4051// Helper class for AI_smld.
4052class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4053 InstrItinClass itin, string opc, string asm>
4054 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4055 bits<4> Rn;
4056 bits<4> Rm;
4057 let Inst{27-23} = 0b01110;
4058 let Inst{22} = long;
4059 let Inst{21-20} = 0b00;
4060 let Inst{11-8} = Rm;
4061 let Inst{7} = 0;
4062 let Inst{6} = sub;
4063 let Inst{5} = swap;
4064 let Inst{4} = 1;
4065 let Inst{3-0} = Rn;
4066}
4067class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4068 InstrItinClass itin, string opc, string asm>
4069 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4070 bits<4> Rd;
4071 let Inst{15-12} = 0b1111;
4072 let Inst{19-16} = Rd;
4073}
4074class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4075 InstrItinClass itin, string opc, string asm>
4076 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4077 bits<4> Ra;
4078 bits<4> Rd;
4079 let Inst{19-16} = Rd;
4080 let Inst{15-12} = Ra;
4081}
4082class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4083 InstrItinClass itin, string opc, string asm>
4084 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4085 bits<4> RdLo;
4086 bits<4> RdHi;
4087 let Inst{19-16} = RdHi;
4088 let Inst{15-12} = RdLo;
4089}
4090
4091multiclass AI_smld<bit sub, string opc> {
4092
4093 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4094 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4095 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4096
4097 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4098 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4099 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4100
4101 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4102 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4103 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4104
4105 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4106 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4107 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4108
4109}
4110
4111defm SMLA : AI_smld<0, "smla">;
4112defm SMLS : AI_smld<1, "smls">;
4113
4114multiclass AI_sdml<bit sub, string opc> {
4115
4116 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4117 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4118 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4119 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4120}
4121
4122defm SMUA : AI_sdml<0, "smua">;
4123defm SMUS : AI_sdml<1, "smus">;
4124
4125//===----------------------------------------------------------------------===//
4126// Division Instructions (ARMv7-A with virtualization extension)
4127//
4128def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4129 "sdiv", "\t$Rd, $Rn, $Rm",
4130 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4131 Requires<[IsARM, HasDivideInARM]>;
4132
4133def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4134 "udiv", "\t$Rd, $Rn, $Rm",
4135 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4136 Requires<[IsARM, HasDivideInARM]>;
4137
4138//===----------------------------------------------------------------------===//
4139// Misc. Arithmetic Instructions.
4140//
4141
1a4d82fc 4142def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
223e47cc 4143 IIC_iUNAr, "clz", "\t$Rd, $Rm",
1a4d82fc
JJ		 4144 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4145 Sched<[WriteALU]>;
223e47cc
LB		 4146
4147def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4148 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4149 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
1a4d82fc
JJ		 4150 Requires<[IsARM, HasV6T2]>,
4151 Sched<[WriteALU]>;
223e47cc
LB		 4152
4153def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4154 IIC_iUNAr, "rev", "\t$Rd, $Rm",
1a4d82fc
JJ		 4155 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4156 Sched<[WriteALU]>;
223e47cc
LB		 4157
4158let AddedComplexity = 5 in
4159def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4160 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4161 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
1a4d82fc
JJ		 4162 Requires<[IsARM, HasV6]>,
4163 Sched<[WriteALU]>;
4164
4165def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4166 (REV16 (LDRH addrmode3:$addr))>;
4167def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4168 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
223e47cc
LB		 4169
4170let AddedComplexity = 5 in
4171def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4172 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4173 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
1a4d82fc
JJ		 4174 Requires<[IsARM, HasV6]>,
4175 Sched<[WriteALU]>;
223e47cc
LB		 4176
4177def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4178 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4179 (REVSH GPR:$Rm)>;
4180
4181def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4182 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4183 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4184 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4185 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4186 0xFFFF0000)))]>,
1a4d82fc
JJ		 4187 Requires<[IsARM, HasV6]>,
4188 Sched<[WriteALUsi, ReadALU]>;
223e47cc
LB		 4189
4190// Alternate cases for PKHBT where identities eliminate some nodes.
4191def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4192 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4193def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4194 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4195
4196// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4197// will match the pattern below.
4198def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4199 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4200 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4201 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4202 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4203 0xFFFF)))]>,
1a4d82fc
JJ		 4204 Requires<[IsARM, HasV6]>,
4205 Sched<[WriteALUsi, ReadALU]>;
223e47cc
LB		 4206
4207// Alternate cases for PKHTB where identities eliminate some nodes. Note that
4208// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1a4d82fc
JJ		 4209// We also can not replace a srl (17..31) by an arithmetic shift we would use in
4210// pkhtb src1, src2, asr (17..31).
223e47cc 4211def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
1a4d82fc
JJ		 4212 (srl GPRnopc:$src2, imm16:$sh)),
4213 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4214def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4215 (sra GPRnopc:$src2, imm16_31:$sh)),
223e47cc
LB		 4216 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4217def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4218 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4219 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4220
1a4d82fc
JJ		 4221//===----------------------------------------------------------------------===//
4222// CRC Instructions
4223//
4224// Polynomials:
4225// + CRC32{B,H,W} 0x04C11DB7
4226// + CRC32C{B,H,W} 0x1EDC6F41
4227//
4228
4229class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4230 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4231 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4232 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4233 Requires<[IsARM, HasV8, HasCRC]> {
4234 bits<4> Rd;
4235 bits<4> Rn;
4236 bits<4> Rm;
4237
4238 let Inst{31-28} = 0b1110;
4239 let Inst{27-23} = 0b00010;
4240 let Inst{22-21} = sz;
4241 let Inst{20} = 0;
4242 let Inst{19-16} = Rn;
4243 let Inst{15-12} = Rd;
4244 let Inst{11-10} = 0b00;
4245 let Inst{9} = C;
4246 let Inst{8} = 0;
4247 let Inst{7-4} = 0b0100;
4248 let Inst{3-0} = Rm;
4249
4250 let Unpredictable{11-8} = 0b1101;
4251}
4252
4253def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4254def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4255def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4256def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4257def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4258def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4259
223e47cc
LB		 4260//===----------------------------------------------------------------------===//
4261// Comparison Instructions...
4262//
4263
4264defm CMP : AI1_cmp_irs<0b1010, "cmp",
4265 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4266 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4267
4268// ARMcmpZ can re-use the above instruction definitions.
85aaf69f
SL		 4269def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4270 (CMPri GPR:$src, mod_imm:$imm)>;
223e47cc
LB		 4271def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4272 (CMPrr GPR:$src, GPR:$rhs)>;
4273def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4274 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4275def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4276 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4277
4278// CMN register-integer
4279let isCompare = 1, Defs = [CPSR] in {
85aaf69f 4280def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
223e47cc 4281 "cmn", "\t$Rn, $imm",
85aaf69f 4282 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
1a4d82fc 4283 Sched<[WriteCMP, ReadALU]> {
223e47cc
LB		 4284 bits<4> Rn;
4285 bits<12> imm;
4286 let Inst{25} = 1;
4287 let Inst{20} = 1;
4288 let Inst{19-16} = Rn;
4289 let Inst{15-12} = 0b0000;
4290 let Inst{11-0} = imm;
4291
4292 let Unpredictable{15-12} = 0b1111;
4293}
4294
4295// CMN register-register/shift
4296def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4297 "cmn", "\t$Rn, $Rm",
4298 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
1a4d82fc 4299 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
223e47cc
LB		 4300 bits<4> Rn;
4301 bits<4> Rm;
4302 let isCommutable = 1;
4303 let Inst{25} = 0;
4304 let Inst{20} = 1;
4305 let Inst{19-16} = Rn;
4306 let Inst{15-12} = 0b0000;
4307 let Inst{11-4} = 0b00000000;
4308 let Inst{3-0} = Rm;
4309
4310 let Unpredictable{15-12} = 0b1111;
4311}
4312
4313def CMNzrsi : AI1<0b1011, (outs),
4314 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4315 "cmn", "\t$Rn, $shift",
4316 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
1a4d82fc
JJ		 4317 GPR:$Rn, so_reg_imm:$shift)]>,
4318 Sched<[WriteCMPsi, ReadALU]> {
223e47cc
LB		 4319 bits<4> Rn;
4320 bits<12> shift;
4321 let Inst{25} = 0;
4322 let Inst{20} = 1;
4323 let Inst{19-16} = Rn;
4324 let Inst{15-12} = 0b0000;
4325 let Inst{11-5} = shift{11-5};
4326 let Inst{4} = 0;
4327 let Inst{3-0} = shift{3-0};
4328
4329 let Unpredictable{15-12} = 0b1111;
4330}
4331
4332def CMNzrsr : AI1<0b1011, (outs),
4333 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4334 "cmn", "\t$Rn, $shift",
4335 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
1a4d82fc
JJ		 4336 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4337 Sched<[WriteCMPsr, ReadALU]> {
223e47cc
LB		 4338 bits<4> Rn;
4339 bits<12> shift;
4340 let Inst{25} = 0;
4341 let Inst{20} = 1;
4342 let Inst{19-16} = Rn;
4343 let Inst{15-12} = 0b0000;
4344 let Inst{11-8} = shift{11-8};
4345 let Inst{7} = 0;
4346 let Inst{6-5} = shift{6-5};
4347 let Inst{4} = 1;
4348 let Inst{3-0} = shift{3-0};
4349
4350 let Unpredictable{15-12} = 0b1111;
4351}
4352
4353}
4354
85aaf69f
SL		 4355def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4356 (CMNri GPR:$src, mod_imm_neg:$imm)>;
223e47cc 4357
85aaf69f
SL		 4358def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4359 (CMNri GPR:$src, mod_imm_neg:$imm)>;
223e47cc
LB		 4360
4361// Note that TST/TEQ don't set all the same flags that CMP does!
4362defm TST : AI1_cmp_irs<0b1000, "tst",
4363 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4364 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4365defm TEQ : AI1_cmp_irs<0b1001, "teq",
4366 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4367 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4368
4369// Pseudo i64 compares for some floating point compares.
4370let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4371 Defs = [CPSR] in {
4372def BCCi64 : PseudoInst<(outs),
4373 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4374 IIC_Br,
1a4d82fc
JJ		 4375 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4376 Sched<[WriteBr]>;
223e47cc
LB		 4377
4378def BCCZi64 : PseudoInst<(outs),
4379 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
1a4d82fc
JJ		 4380 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4381 Sched<[WriteBr]>;
223e47cc
LB		 4382} // usesCustomInserter
4383
4384
4385// Conditional moves
85aaf69f 4386let hasSideEffects = 0 in {
223e47cc
LB		 4387
4388let isCommutable = 1, isSelect = 1 in
1a4d82fc
JJ		 4389def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4390 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
223e47cc 4391 4, IIC_iCMOVr,
1a4d82fc
JJ		 4392 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4393 cmovpred:$p))]>,
4394 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
223e47cc
LB		 4395
4396def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
1a4d82fc
JJ		 4397 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4398 4, IIC_iCMOVsr,
4399 [(set GPR:$Rd,
4400 (ARMcmov GPR:$false, so_reg_imm:$shift,
4401 cmovpred:$p))]>,
4402 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
223e47cc 4403def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
1a4d82fc 4404 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
223e47cc 4405 4, IIC_iCMOVsr,
1a4d82fc
JJ		 4406 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4407 cmovpred:$p))]>,
4408 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
223e47cc
LB		 4409
4410
4411let isMoveImm = 1 in
1a4d82fc
JJ		 4412def MOVCCi16
4413 : ARMPseudoInst<(outs GPR:$Rd),
4414 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4415 4, IIC_iMOVi,
4416 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4417 cmovpred:$p))]>,
4418 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4419 Sched<[WriteALU]>;
223e47cc
LB		 4420
4421let isMoveImm = 1 in
4422def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
85aaf69f 4423 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
223e47cc 4424 4, IIC_iCMOVi,
85aaf69f 4425 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
1a4d82fc
JJ		 4426 cmovpred:$p))]>,
4427 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
223e47cc
LB		 4428
4429// Two instruction predicate mov immediate.
4430let isMoveImm = 1 in
1a4d82fc
JJ		 4431def MOVCCi32imm
4432 : ARMPseudoInst<(outs GPR:$Rd),
4433 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4434 8, IIC_iCMOVix2,
4435 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4436 cmovpred:$p))]>,
4437 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
223e47cc
LB		 4438
4439let isMoveImm = 1 in
4440def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
85aaf69f 4441 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
223e47cc 4442 4, IIC_iCMOVi,
85aaf69f 4443 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
1a4d82fc
JJ		 4444 cmovpred:$p))]>,
4445 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
223e47cc 4446
85aaf69f 4447} // hasSideEffects
223e47cc
LB		 4448
4449
4450//===----------------------------------------------------------------------===//
4451// Atomic operations intrinsics
4452//
4453
4454def MemBarrierOptOperand : AsmOperandClass {
4455 let Name = "MemBarrierOpt";
4456 let ParserMethod = "parseMemBarrierOptOperand";
4457}
4458def memb_opt : Operand<i32> {
4459 let PrintMethod = "printMemBOption";
4460 let ParserMatchClass = MemBarrierOptOperand;
4461 let DecoderMethod = "DecodeMemBarrierOption";
4462}
4463
1a4d82fc
JJ		 4464def InstSyncBarrierOptOperand : AsmOperandClass {
4465 let Name = "InstSyncBarrierOpt";
4466 let ParserMethod = "parseInstSyncBarrierOptOperand";
4467}
4468def instsyncb_opt : Operand<i32> {
4469 let PrintMethod = "printInstSyncBOption";
4470 let ParserMatchClass = InstSyncBarrierOptOperand;
4471 let DecoderMethod = "DecodeInstSyncBarrierOption";
4472}
4473
4474// Memory barriers protect the atomic sequences
223e47cc
LB		 4475let hasSideEffects = 1 in {
4476def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
1a4d82fc 4477 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
223e47cc
LB		 4478 Requires<[IsARM, HasDB]> {
4479 bits<4> opt;
4480 let Inst{31-4} = 0xf57ff05;
4481 let Inst{3-0} = opt;
4482}
223e47cc
LB		 4483
4484def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
1a4d82fc 4485 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
223e47cc
LB		 4486 Requires<[IsARM, HasDB]> {
4487 bits<4> opt;
4488 let Inst{31-4} = 0xf57ff04;
4489 let Inst{3-0} = opt;
4490}
4491
4492// ISB has only full system option
1a4d82fc
JJ		 4493def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4494 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
223e47cc
LB		 4495 Requires<[IsARM, HasDB]> {
4496 bits<4> opt;
4497 let Inst{31-4} = 0xf57ff06;
4498 let Inst{3-0} = opt;
4499}
1a4d82fc
JJ		 4500}
4501
4502let usesCustomInserter = 1, Defs = [CPSR] in {
223e47cc
LB		 4503
4504// Pseudo instruction that combines movs + predicated rsbmi
4505// to implement integer ABS
1a4d82fc 4506 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
223e47cc
LB		 4507}
4508
4509let usesCustomInserter = 1 in {
4510 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4511 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4512 NoItinerary,
4513 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4514}
4515
1a4d82fc
JJ		 4516def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4517 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4518}]>;
4519
4520def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4521 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4522}]>;
4523
4524def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4525 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4526}]>;
4527
4528def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4529 (int_arm_strex node:$val, node:$ptr), [{
4530 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4531}]>;
4532
4533def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4534 (int_arm_strex node:$val, node:$ptr), [{
4535 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4536}]>;
4537
4538def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4539 (int_arm_strex node:$val, node:$ptr), [{
4540 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4541}]>;
4542
4543def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4544 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4545}]>;
4546
4547def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4548 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4549}]>;
4550
4551def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4552 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4553}]>;
4554
4555def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4556 (int_arm_stlex node:$val, node:$ptr), [{
4557 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4558}]>;
4559
4560def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4561 (int_arm_stlex node:$val, node:$ptr), [{
4562 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4563}]>;
4564
4565def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4566 (int_arm_stlex node:$val, node:$ptr), [{
4567 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4568}]>;
4569
223e47cc
LB		 4570let mayLoad = 1 in {
4571def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
1a4d82fc
JJ		 4572 NoItinerary, "ldrexb", "\t$Rt, $addr",
4573 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
223e47cc 4574def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
1a4d82fc
JJ		 4575 NoItinerary, "ldrexh", "\t$Rt, $addr",
4576 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
223e47cc 4577def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
1a4d82fc
JJ		 4578 NoItinerary, "ldrex", "\t$Rt, $addr",
4579 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
223e47cc 4580let hasExtraDefRegAllocReq = 1 in
1a4d82fc 4581def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
970d7e83 4582 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
223e47cc
LB		 4583 let DecoderMethod = "DecodeDoubleRegLoad";
4584}
1a4d82fc
JJ		 4585
4586def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4587 NoItinerary, "ldaexb", "\t$Rt, $addr",
4588 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4589def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4590 NoItinerary, "ldaexh", "\t$Rt, $addr",
4591 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4592def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4593 NoItinerary, "ldaex", "\t$Rt, $addr",
4594 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4595let hasExtraDefRegAllocReq = 1 in
4596def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4597 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4598 let DecoderMethod = "DecodeDoubleRegLoad";
4599}
223e47cc
LB		 4600}
4601
4602let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4603def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
1a4d82fc
JJ		 4604 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4605 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4606 addr_offset_none:$addr))]>;
223e47cc 4607def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
1a4d82fc
JJ		 4608 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4609 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4610 addr_offset_none:$addr))]>;
223e47cc 4611def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
1a4d82fc
JJ		 4612 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4613 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4614 addr_offset_none:$addr))]>;
223e47cc
LB		 4615let hasExtraSrcRegAllocReq = 1 in
4616def STREXD : AIstrex<0b01, (outs GPR:$Rd),
970d7e83
LB		 4617 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4618 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
223e47cc
LB		 4619 let DecoderMethod = "DecodeDoubleRegStore";
4620}
1a4d82fc
JJ		 4621def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4622 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4623 [(set GPR:$Rd,
4624 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4625def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4626 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4627 [(set GPR:$Rd,
4628 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4629def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4630 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4631 [(set GPR:$Rd,
4632 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4633let hasExtraSrcRegAllocReq = 1 in
4634def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4635 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4636 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4637 let DecoderMethod = "DecodeDoubleRegStore";
4638}
223e47cc
LB		 4639}
4640
1a4d82fc
JJ		 4641def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4642 [(int_arm_clrex)]>,
223e47cc
LB		 4643 Requires<[IsARM, HasV7]> {
4644 let Inst{31-0} = 0b11110101011111111111000000011111;
4645}
4646
1a4d82fc
JJ		 4647def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4648 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4649def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4650 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4651
4652def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4653 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4654def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4655 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4656
4657class acquiring_load<PatFrag base>
4658 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4659 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4660 return isAtLeastAcquire(Ordering);
4661}]>;
4662
4663def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4664def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4665def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4666
4667class releasing_store<PatFrag base>
4668 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4669 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4670 return isAtLeastRelease(Ordering);
4671}]>;
4672
4673def atomic_store_release_8 : releasing_store<atomic_store_8>;
4674def atomic_store_release_16 : releasing_store<atomic_store_16>;
4675def atomic_store_release_32 : releasing_store<atomic_store_32>;
4676
4677let AddedComplexity = 8 in {
4678 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4679 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4680 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4681 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4682 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4683 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4684}
4685
223e47cc
LB		 4686// SWP/SWPB are deprecated in V6/V7.
4687let mayLoad = 1, mayStore = 1 in {
4688def SWP : AIswp<0, (outs GPRnopc:$Rt),
1a4d82fc
JJ		 4689 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4690 Requires<[PreV8]>;
223e47cc 4691def SWPB: AIswp<1, (outs GPRnopc:$Rt),
1a4d82fc
JJ		 4692 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4693 Requires<[PreV8]>;
223e47cc
LB		 4694}
4695
4696//===----------------------------------------------------------------------===//
4697// Coprocessor Instructions.
4698//
4699
4700def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4701 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4702 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4703 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1a4d82fc
JJ		 4704 imm:$CRm, imm:$opc2)]>,
4705 Requires<[PreV8]> {
223e47cc
LB		 4706 bits<4> opc1;
4707 bits<4> CRn;
4708 bits<4> CRd;
4709 bits<4> cop;
4710 bits<3> opc2;
4711 bits<4> CRm;
4712
4713 let Inst{3-0} = CRm;
4714 let Inst{4} = 0;
4715 let Inst{7-5} = opc2;
4716 let Inst{11-8} = cop;
4717 let Inst{15-12} = CRd;
4718 let Inst{19-16} = CRn;
4719 let Inst{23-20} = opc1;
4720}
4721
1a4d82fc 4722def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
223e47cc
LB		 4723 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4724 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4725 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1a4d82fc
JJ		 4726 imm:$CRm, imm:$opc2)]>,
4727 Requires<[PreV8]> {
223e47cc
LB		 4728 let Inst{31-28} = 0b1111;
4729 bits<4> opc1;
4730 bits<4> CRn;
4731 bits<4> CRd;
4732 bits<4> cop;
4733 bits<3> opc2;
4734 bits<4> CRm;
4735
4736 let Inst{3-0} = CRm;
4737 let Inst{4} = 0;
4738 let Inst{7-5} = opc2;
4739 let Inst{11-8} = cop;
4740 let Inst{15-12} = CRd;
4741 let Inst{19-16} = CRn;
4742 let Inst{23-20} = opc1;
4743}
4744
4745class ACI<dag oops, dag iops, string opc, string asm,
4746 IndexMode im = IndexModeNone>
4747 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4748 opc, asm, "", []> {
4749 let Inst{27-25} = 0b110;
4750}
4751class ACInoP<dag oops, dag iops, string opc, string asm,
4752 IndexMode im = IndexModeNone>
4753 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4754 opc, asm, "", []> {
4755 let Inst{31-28} = 0b1111;
4756 let Inst{27-25} = 0b110;
4757}
4758multiclass LdStCop<bit load, bit Dbit, string asm> {
4759 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4760 asm, "\t$cop, $CRd, $addr"> {
4761 bits<13> addr;
4762 bits<4> cop;
4763 bits<4> CRd;
4764 let Inst{24} = 1; // P = 1
4765 let Inst{23} = addr{8};
4766 let Inst{22} = Dbit;
4767 let Inst{21} = 0; // W = 0
4768 let Inst{20} = load;
4769 let Inst{19-16} = addr{12-9};
4770 let Inst{15-12} = CRd;
4771 let Inst{11-8} = cop;
4772 let Inst{7-0} = addr{7-0};
4773 let DecoderMethod = "DecodeCopMemInstruction";
4774 }
1a4d82fc 4775 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
223e47cc
LB		 4776 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4777 bits<13> addr;
4778 bits<4> cop;
4779 bits<4> CRd;
4780 let Inst{24} = 1; // P = 1
4781 let Inst{23} = addr{8};
4782 let Inst{22} = Dbit;
4783 let Inst{21} = 1; // W = 1
4784 let Inst{20} = load;
4785 let Inst{19-16} = addr{12-9};
4786 let Inst{15-12} = CRd;
4787 let Inst{11-8} = cop;
4788 let Inst{7-0} = addr{7-0};
4789 let DecoderMethod = "DecodeCopMemInstruction";
4790 }
4791 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4792 postidx_imm8s4:$offset),
4793 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4794 bits<9> offset;
4795 bits<4> addr;
4796 bits<4> cop;
4797 bits<4> CRd;
4798 let Inst{24} = 0; // P = 0
4799 let Inst{23} = offset{8};
4800 let Inst{22} = Dbit;
4801 let Inst{21} = 1; // W = 1
4802 let Inst{20} = load;
4803 let Inst{19-16} = addr;
4804 let Inst{15-12} = CRd;
4805 let Inst{11-8} = cop;
4806 let Inst{7-0} = offset{7-0};
4807 let DecoderMethod = "DecodeCopMemInstruction";
4808 }
4809 def _OPTION : ACI<(outs),
4810 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4811 coproc_option_imm:$option),
4812 asm, "\t$cop, $CRd, $addr, $option"> {
4813 bits<8> option;
4814 bits<4> addr;
4815 bits<4> cop;
4816 bits<4> CRd;
4817 let Inst{24} = 0; // P = 0
4818 let Inst{23} = 1; // U = 1
4819 let Inst{22} = Dbit;
4820 let Inst{21} = 0; // W = 0
4821 let Inst{20} = load;
4822 let Inst{19-16} = addr;
4823 let Inst{15-12} = CRd;
4824 let Inst{11-8} = cop;
4825 let Inst{7-0} = option;
4826 let DecoderMethod = "DecodeCopMemInstruction";
4827 }
4828}
4829multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4830 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4831 asm, "\t$cop, $CRd, $addr"> {
4832 bits<13> addr;
4833 bits<4> cop;
4834 bits<4> CRd;
4835 let Inst{24} = 1; // P = 1
4836 let Inst{23} = addr{8};
4837 let Inst{22} = Dbit;
4838 let Inst{21} = 0; // W = 0
4839 let Inst{20} = load;
4840 let Inst{19-16} = addr{12-9};
4841 let Inst{15-12} = CRd;
4842 let Inst{11-8} = cop;
4843 let Inst{7-0} = addr{7-0};
4844 let DecoderMethod = "DecodeCopMemInstruction";
4845 }
1a4d82fc 4846 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
223e47cc
LB		 4847 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4848 bits<13> addr;
4849 bits<4> cop;
4850 bits<4> CRd;
4851 let Inst{24} = 1; // P = 1
4852 let Inst{23} = addr{8};
4853 let Inst{22} = Dbit;
4854 let Inst{21} = 1; // W = 1
4855 let Inst{20} = load;
4856 let Inst{19-16} = addr{12-9};
4857 let Inst{15-12} = CRd;
4858 let Inst{11-8} = cop;
4859 let Inst{7-0} = addr{7-0};
4860 let DecoderMethod = "DecodeCopMemInstruction";
4861 }
4862 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4863 postidx_imm8s4:$offset),
4864 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4865 bits<9> offset;
4866 bits<4> addr;
4867 bits<4> cop;
4868 bits<4> CRd;
4869 let Inst{24} = 0; // P = 0
4870 let Inst{23} = offset{8};
4871 let Inst{22} = Dbit;
4872 let Inst{21} = 1; // W = 1
4873 let Inst{20} = load;
4874 let Inst{19-16} = addr;
4875 let Inst{15-12} = CRd;
4876 let Inst{11-8} = cop;
4877 let Inst{7-0} = offset{7-0};
4878 let DecoderMethod = "DecodeCopMemInstruction";
4879 }
4880 def _OPTION : ACInoP<(outs),
4881 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4882 coproc_option_imm:$option),
4883 asm, "\t$cop, $CRd, $addr, $option"> {
4884 bits<8> option;
4885 bits<4> addr;
4886 bits<4> cop;
4887 bits<4> CRd;
4888 let Inst{24} = 0; // P = 0
4889 let Inst{23} = 1; // U = 1
4890 let Inst{22} = Dbit;
4891 let Inst{21} = 0; // W = 0
4892 let Inst{20} = load;
4893 let Inst{19-16} = addr;
4894 let Inst{15-12} = CRd;
4895 let Inst{11-8} = cop;
4896 let Inst{7-0} = option;
4897 let DecoderMethod = "DecodeCopMemInstruction";
4898 }
4899}
4900
4901defm LDC : LdStCop <1, 0, "ldc">;
4902defm LDCL : LdStCop <1, 1, "ldcl">;
4903defm STC : LdStCop <0, 0, "stc">;
4904defm STCL : LdStCop <0, 1, "stcl">;
1a4d82fc
JJ		 4905defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4906defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4907defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4908defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
223e47cc
LB		 4909
4910//===----------------------------------------------------------------------===//
4911// Move between coprocessor and ARM core register.
4912//
4913
4914class MovRCopro<string opc, bit direction, dag oops, dag iops,
4915 list<dag> pattern>
4916 : ABI<0b1110, oops, iops, NoItinerary, opc,
4917 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4918 let Inst{20} = direction;
4919 let Inst{4} = 1;
4920
4921 bits<4> Rt;
4922 bits<4> cop;
4923 bits<3> opc1;
4924 bits<3> opc2;
4925 bits<4> CRm;
4926 bits<4> CRn;
4927
4928 let Inst{15-12} = Rt;
4929 let Inst{11-8} = cop;
4930 let Inst{23-21} = opc1;
4931 let Inst{7-5} = opc2;
4932 let Inst{3-0} = CRm;
4933 let Inst{19-16} = CRn;
4934}
4935
4936def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4937 (outs),
4938 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4939 c_imm:$CRm, imm0_7:$opc2),
4940 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1a4d82fc
JJ		 4941 imm:$CRm, imm:$opc2)]>,
4942 ComplexDeprecationPredicate<"MCR">;
223e47cc
LB		 4943def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4944 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4945 c_imm:$CRm, 0, pred:$p)>;
4946def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1a4d82fc 4947 (outs GPRwithAPSR:$Rt),
223e47cc
LB		 4948 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4949 imm0_7:$opc2), []>;
4950def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
1a4d82fc 4951 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
223e47cc
LB		 4952 c_imm:$CRm, 0, pred:$p)>;
4953
4954def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4955 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4956
4957class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4958 list<dag> pattern>
4959 : ABXI<0b1110, oops, iops, NoItinerary,
4960 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
1a4d82fc 4961 let Inst{31-24} = 0b11111110;
223e47cc
LB		 4962 let Inst{20} = direction;
4963 let Inst{4} = 1;
4964
4965 bits<4> Rt;
4966 bits<4> cop;
4967 bits<3> opc1;
4968 bits<3> opc2;
4969 bits<4> CRm;
4970 bits<4> CRn;
4971
4972 let Inst{15-12} = Rt;
4973 let Inst{11-8} = cop;
4974 let Inst{23-21} = opc1;
4975 let Inst{7-5} = opc2;
4976 let Inst{3-0} = CRm;
4977 let Inst{19-16} = CRn;
4978}
4979
4980def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4981 (outs),
4982 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4983 c_imm:$CRm, imm0_7:$opc2),
4984 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1a4d82fc
JJ		 4985 imm:$CRm, imm:$opc2)]>,
4986 Requires<[PreV8]>;
4987def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
223e47cc
LB		 4988 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4989 c_imm:$CRm, 0)>;
4990def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
1a4d82fc 4991 (outs GPRwithAPSR:$Rt),
223e47cc 4992 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
1a4d82fc
JJ		 4993 imm0_7:$opc2), []>,
4994 Requires<[PreV8]>;
4995def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
4996 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
223e47cc
LB		 4997 c_imm:$CRm, 0)>;
4998
4999def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5000 imm:$CRm, imm:$opc2),
5001 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5002
5003class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5004 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5005 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5006 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5007 let Inst{23-21} = 0b010;
5008 let Inst{20} = direction;
5009
5010 bits<4> Rt;
5011 bits<4> Rt2;
5012 bits<4> cop;
5013 bits<4> opc1;
5014 bits<4> CRm;
5015
5016 let Inst{15-12} = Rt;
5017 let Inst{19-16} = Rt2;
5018 let Inst{11-8} = cop;
5019 let Inst{7-4} = opc1;
5020 let Inst{3-0} = CRm;
5021}
5022
5023def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5024 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5025 GPRnopc:$Rt2, imm:$CRm)]>;
5026def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5027
5028class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5029 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5030 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
1a4d82fc
JJ		 5031 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5032 Requires<[PreV8]> {
223e47cc
LB		 5033 let Inst{31-28} = 0b1111;
5034 let Inst{23-21} = 0b010;
5035 let Inst{20} = direction;
5036
5037 bits<4> Rt;
5038 bits<4> Rt2;
5039 bits<4> cop;
5040 bits<4> opc1;
5041 bits<4> CRm;
5042
5043 let Inst{15-12} = Rt;
5044 let Inst{19-16} = Rt2;
5045 let Inst{11-8} = cop;
5046 let Inst{7-4} = opc1;
5047 let Inst{3-0} = CRm;
5048
5049 let DecoderMethod = "DecodeMRRC2";
5050}
5051
5052def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5053 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5054 GPRnopc:$Rt2, imm:$CRm)]>;
5055def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5056
5057//===----------------------------------------------------------------------===//
5058// Move between special register and ARM core register
5059//
5060
5061// Move to ARM core register from Special Register
5062def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5063 "mrs", "\t$Rd, apsr", []> {
5064 bits<4> Rd;
5065 let Inst{23-16} = 0b00001111;
5066 let Unpredictable{19-17} = 0b111;
5067
5068 let Inst{15-12} = Rd;
5069
5070 let Inst{11-0} = 0b000000000000;
5071 let Unpredictable{11-0} = 0b110100001111;
5072}
5073
5074def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5075 Requires<[IsARM]>;
5076
5077// The MRSsys instruction is the MRS instruction from the ARM ARM,
5078// section B9.3.9, with the R bit set to 1.
5079def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5080 "mrs", "\t$Rd, spsr", []> {
5081 bits<4> Rd;
5082 let Inst{23-16} = 0b01001111;
5083 let Unpredictable{19-16} = 0b1111;
5084
5085 let Inst{15-12} = Rd;
5086
5087 let Inst{11-0} = 0b000000000000;
5088 let Unpredictable{11-0} = 0b110100001111;
5089}
5090
1a4d82fc
JJ		 5091// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5092// separate encoding (distinguished by bit 5.
5093def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5094 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5095 Requires<[IsARM, HasVirtualization]> {
5096 bits<6> banked;
5097 bits<4> Rd;
5098
5099 let Inst{23} = 0;
5100 let Inst{22} = banked{5}; // R bit
85aaf69f 5101 let Inst{21-20} = 0b00;
1a4d82fc
JJ		 5102 let Inst{19-16} = banked{3-0};
5103 let Inst{15-12} = Rd;
5104 let Inst{11-9} = 0b001;
5105 let Inst{8} = banked{4};
5106 let Inst{7-0} = 0b00000000;
5107}
5108
223e47cc
LB		 5109// Move from ARM core register to Special Register
5110//
1a4d82fc
JJ		 5111// No need to have both system and application versions of MSR (immediate) or
5112// MSR (register), the encodings are the same and the assembly parser has no way
5113// to distinguish between them. The mask operand contains the special register
5114// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5115// accessed in the special register.
223e47cc
LB		 5116def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5117 "msr", "\t$mask, $Rn", []> {
5118 bits<5> mask;
5119 bits<4> Rn;
5120
5121 let Inst{23} = 0;
5122 let Inst{22} = mask{4}; // R bit
5123 let Inst{21-20} = 0b10;
5124 let Inst{19-16} = mask{3-0};
5125 let Inst{15-12} = 0b1111;
5126 let Inst{11-4} = 0b00000000;
5127 let Inst{3-0} = Rn;
5128}
5129
85aaf69f
SL		 5130def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5131 "msr", "\t$mask, $imm", []> {
223e47cc 5132 bits<5> mask;
85aaf69f 5133 bits<12> imm;
223e47cc
LB		 5134
5135 let Inst{23} = 0;
5136 let Inst{22} = mask{4}; // R bit
5137 let Inst{21-20} = 0b10;
5138 let Inst{19-16} = mask{3-0};
5139 let Inst{15-12} = 0b1111;
85aaf69f 5140 let Inst{11-0} = imm;
223e47cc
LB		 5141}
5142
1a4d82fc
JJ		 5143// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5144// separate encoding (distinguished by bit 5.
5145def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5146 NoItinerary, "msr", "\t$banked, $Rn", []>,
5147 Requires<[IsARM, HasVirtualization]> {
5148 bits<6> banked;
5149 bits<4> Rn;
5150
5151 let Inst{23} = 0;
5152 let Inst{22} = banked{5}; // R bit
5153 let Inst{21-20} = 0b10;
5154 let Inst{19-16} = banked{3-0};
5155 let Inst{15-12} = 0b1111;
5156 let Inst{11-9} = 0b001;
5157 let Inst{8} = banked{4};
5158 let Inst{7-4} = 0b0000;
5159 let Inst{3-0} = Rn;
5160}
5161
5162// Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5163// are needed to probe the stack when allocating more than
5164// 4k bytes in one go. Touching the stack at 4K increments is necessary to
5165// ensure that the guard pages used by the OS virtual memory manager are
5166// allocated in correct sequence.
5167// The main point of having separate instruction are extra unmodelled effects
5168// (compared to ordinary calls) like stack pointer change.
5169
5170def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5171 [SDNPHasChain, SDNPSideEffect]>;
5172let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5173 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5174
223e47cc
LB		 5175//===----------------------------------------------------------------------===//
5176// TLS Instructions
5177//
5178
5179// __aeabi_read_tp preserves the registers r1-r3.
5180// This is a pseudo inst so that we can get the encoding right,
5181// complete with fixup for the aeabi_read_tp function.
1a4d82fc
JJ		 5182// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5183// is defined in "ARMInstrThumb.td".
223e47cc
LB		 5184let isCall = 1,
5185 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
1a4d82fc
JJ		 5186 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5187 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
223e47cc
LB		 5188}
5189
5190//===----------------------------------------------------------------------===//
5191// SJLJ Exception handling intrinsics
5192// eh_sjlj_setjmp() is an instruction sequence to store the return
5193// address and save #0 in R0 for the non-longjmp case.
5194// Since by its nature we may be coming from some other function to get
5195// here, and we're using the stack frame for the containing function to
5196// save/restore registers, we can't keep anything live in regs across
5197// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5198// when we get here from a longjmp(). We force everything out of registers
5199// except for our own input by listing the relevant registers in Defs. By
5200// doing so, we also cause the prologue/epilogue code to actively preserve
5201// all of the callee-saved resgisters, which is exactly what we want.
5202// A constant value is passed in $val, and we use the location as a scratch.
5203//
5204// These are pseudo-instructions and are lowered to individual MC-insts, so
5205// no encoding information is necessary.
5206let Defs =
5207 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5208 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5209 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5210 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5211 NoItinerary,
5212 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5213 Requires<[IsARM, HasVFP2]>;
5214}
5215
5216let Defs =
5217 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5218 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5219 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5220 NoItinerary,
5221 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5222 Requires<[IsARM, NoVFP]>;
5223}
5224
5225// FIXME: Non-IOS version(s)
5226let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5227 Defs = [ R7, LR, SP ] in {
5228def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5229 NoItinerary,
5230 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
85aaf69f 5231 Requires<[IsARM]>;
223e47cc
LB		 5232}
5233
970d7e83
LB		 5234// eh.sjlj.dispatchsetup pseudo-instruction.
5235// This pseudo is used for both ARM and Thumb. Any differences are handled when
5236// the pseudo is expanded (which happens before any passes that need the
5237// instruction size).
5238let isBarrier = 1 in
223e47cc
LB		 5239def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5240
223e47cc
LB		 5241
5242//===----------------------------------------------------------------------===//
5243// Non-Instruction Patterns
5244//
5245
5246// ARMv4 indirect branch using (MOVr PC, dst)
5247let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5248 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5249 4, IIC_Br, [(brind GPR:$dst)],
5250 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
1a4d82fc 5251 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
223e47cc
LB		 5252
5253// Large immediate handling.
5254
85aaf69f 5255// 32-bit immediate using two piece mod_imms or movw + movt.
223e47cc
LB		 5256// This is a single pseudo instruction, the benefit is that it can be remat'd
5257// as a single unit instead of having to handle reg inputs.
5258// FIXME: Remove this when we can do generalized remat.
5259let isReMaterializable = 1, isMoveImm = 1 in
5260def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5261 [(set GPR:$dst, (arm_i32imm:$src))]>,
5262 Requires<[IsARM]>;
5263
1a4d82fc
JJ		 5264def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5265 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5266 Requires<[IsARM, DontUseMovt]>;
5267
223e47cc
LB		 5268// Pseudo instruction that combines movw + movt + add pc (if PIC).
5269// It also makes it possible to rematerialize the instructions.
5270// FIXME: Remove this when we can do generalized remat and when machine licm
5271// can properly the instructions.
5272let isReMaterializable = 1 in {
5273def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5274 IIC_iMOVix2addpc,
5275 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5276 Requires<[IsARM, UseMovt]>;
5277
1a4d82fc
JJ		 5278def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5279 IIC_iLoadiALU,
5280 [(set GPR:$dst,
5281 (ARMWrapperPIC tglobaladdr:$addr))]>,
5282 Requires<[IsARM, DontUseMovt]>;
5283
85aaf69f 5284let AddedComplexity = 10 in
1a4d82fc
JJ		 5285def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5286 NoItinerary,
5287 [(set GPR:$dst,
5288 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5289 Requires<[IsARM, DontUseMovt]>;
223e47cc
LB		 5290
5291let AddedComplexity = 10 in
5292def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5293 IIC_iMOVix2ld,
5294 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5295 Requires<[IsARM, UseMovt]>;
5296} // isReMaterializable
5297
5298// ConstantPool, GlobalAddress, and JumpTable
223e47cc
LB		 5299def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5300def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5301 Requires<[IsARM, UseMovt]>;
5302def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5303 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5304
5305// TODO: add,sub,and, 3-instr forms?
5306
5307// Tail calls. These patterns also apply to Thumb mode.
5308def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5309def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5310def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5311
5312// Direct calls
5313def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5314def : ARMPat<(ARMcall_nolink texternalsym:$func),
5315 (BMOVPCB_CALL texternalsym:$func)>;
5316
5317// zextload i1 -> zextload i8
5318def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5319def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5320
5321// extload -> zextload
5322def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5323def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5324def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5325def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5326
5327def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5328
5329def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5330def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5331
5332// smul* and smla*
5333def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5334 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5335 (SMULBB GPR:$a, GPR:$b)>;
5336def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5337 (SMULBB GPR:$a, GPR:$b)>;
5338def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5339 (sra GPR:$b, (i32 16))),
5340 (SMULBT GPR:$a, GPR:$b)>;
5341def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5342 (SMULBT GPR:$a, GPR:$b)>;
5343def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5344 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5345 (SMULTB GPR:$a, GPR:$b)>;
5346def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5347 (SMULTB GPR:$a, GPR:$b)>;
223e47cc
LB		 5348
5349def : ARMV5MOPat<(add GPR:$acc,
5350 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5351 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5352 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5353def : ARMV5MOPat<(add GPR:$acc,
5354 (mul sext_16_node:$a, sext_16_node:$b)),
5355 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5356def : ARMV5MOPat<(add GPR:$acc,
5357 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5358 (sra GPR:$b, (i32 16)))),
5359 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5360def : ARMV5MOPat<(add GPR:$acc,
5361 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5362 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5363def : ARMV5MOPat<(add GPR:$acc,
5364 (mul (sra GPR:$a, (i32 16)),
5365 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5366 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5367def : ARMV5MOPat<(add GPR:$acc,
5368 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5369 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
223e47cc
LB		 5370
5371
5372// Pre-v7 uses MCR for synchronization barriers.
5373def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5374 Requires<[IsARM, HasV6]>;
5375
5376// SXT/UXT with no rotate
5377let AddedComplexity = 16 in {
5378def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5379def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5380def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5381def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5382 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5383def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5384 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5385}
5386
5387def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5388def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5389
5390def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5391 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5392def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5393 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5394
5395// Atomic load/store patterns
5396def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5397 (LDRBrs ldst_so_reg:$src)>;
5398def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5399 (LDRBi12 addrmode_imm12:$src)>;
5400def : ARMPat<(atomic_load_16 addrmode3:$src),
5401 (LDRH addrmode3:$src)>;
5402def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5403 (LDRrs ldst_so_reg:$src)>;
5404def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5405 (LDRi12 addrmode_imm12:$src)>;
5406def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5407 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5408def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5409 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5410def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5411 (STRH GPR:$val, addrmode3:$ptr)>;
5412def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5413 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5414def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5415 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5416
5417
5418//===----------------------------------------------------------------------===//
5419// Thumb Support
5420//
5421
5422include "ARMInstrThumb.td"
5423
5424//===----------------------------------------------------------------------===//
5425// Thumb2 Support
5426//
5427
5428include "ARMInstrThumb2.td"
5429
5430//===----------------------------------------------------------------------===//
5431// Floating Point Support
5432//
5433
5434include "ARMInstrVFP.td"
5435
5436//===----------------------------------------------------------------------===//
5437// Advanced SIMD (NEON) Support
5438//
5439
5440include "ARMInstrNEON.td"
5441
5442//===----------------------------------------------------------------------===//
5443// Assembler aliases
5444//
5445
5446// Memory barriers
5447def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5448def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5449def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5450
5451// System instructions
5452def : MnemonicAlias<"swi", "svc">;
5453
5454// Load / Store Multiple
5455def : MnemonicAlias<"ldmfd", "ldm">;
5456def : MnemonicAlias<"ldmia", "ldm">;
5457def : MnemonicAlias<"ldmea", "ldmdb">;
5458def : MnemonicAlias<"stmfd", "stmdb">;
5459def : MnemonicAlias<"stmia", "stm">;
5460def : MnemonicAlias<"stmea", "stm">;
5461
5462// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5463// shift amount is zero (i.e., unspecified).
5464def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5465 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5466 Requires<[IsARM, HasV6]>;
5467def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5468 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5469 Requires<[IsARM, HasV6]>;
5470
5471// PUSH/POP aliases for STM/LDM
5472def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5473def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5474
5475// SSAT/USAT optional shift operand.
5476def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5477 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5478def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5479 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5480
5481
5482// Extend instruction optional rotate operand.
5483def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5484 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5485def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5486 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5487def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5488 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5489def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5490 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5491def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5492 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5493def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5494 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5495
5496def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5497 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5498def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5499 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5500def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5501 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5502def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5503 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5504def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5505 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5506def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5507 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5508
5509
5510// RFE aliases
5511def : MnemonicAlias<"rfefa", "rfeda">;
5512def : MnemonicAlias<"rfeea", "rfedb">;
5513def : MnemonicAlias<"rfefd", "rfeia">;
5514def : MnemonicAlias<"rfeed", "rfeib">;
5515def : MnemonicAlias<"rfe", "rfeia">;
5516
5517// SRS aliases
1a4d82fc
JJ		 5518def : MnemonicAlias<"srsfa", "srsib">;
5519def : MnemonicAlias<"srsea", "srsia">;
5520def : MnemonicAlias<"srsfd", "srsdb">;
5521def : MnemonicAlias<"srsed", "srsda">;
223e47cc
LB		 5522def : MnemonicAlias<"srs", "srsia">;
5523
5524// QSAX == QSUBADDX
5525def : MnemonicAlias<"qsubaddx", "qsax">;
5526// SASX == SADDSUBX
5527def : MnemonicAlias<"saddsubx", "sasx">;
5528// SHASX == SHADDSUBX
5529def : MnemonicAlias<"shaddsubx", "shasx">;
5530// SHSAX == SHSUBADDX
5531def : MnemonicAlias<"shsubaddx", "shsax">;
5532// SSAX == SSUBADDX
5533def : MnemonicAlias<"ssubaddx", "ssax">;
5534// UASX == UADDSUBX
5535def : MnemonicAlias<"uaddsubx", "uasx">;
5536// UHASX == UHADDSUBX
5537def : MnemonicAlias<"uhaddsubx", "uhasx">;
5538// UHSAX == UHSUBADDX
5539def : MnemonicAlias<"uhsubaddx", "uhsax">;
5540// UQASX == UQADDSUBX
5541def : MnemonicAlias<"uqaddsubx", "uqasx">;
5542// UQSAX == UQSUBADDX
5543def : MnemonicAlias<"uqsubaddx", "uqsax">;
5544// USAX == USUBADDX
5545def : MnemonicAlias<"usubaddx", "usax">;
5546
85aaf69f 5547// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
223e47cc
LB		 5548// for isel.
5549def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
85aaf69f 5550 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
223e47cc 5551def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
85aaf69f 5552 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
223e47cc
LB		 5553// Same for AND <--> BIC
5554def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
85aaf69f 5555 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
223e47cc
LB		 5556 pred:$p, cc_out:$s)>;
5557def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
85aaf69f 5558 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
223e47cc
LB		 5559 pred:$p, cc_out:$s)>;
5560def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
85aaf69f 5561 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
223e47cc
LB		 5562 pred:$p, cc_out:$s)>;
5563def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
85aaf69f 5564 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
223e47cc
LB		 5565 pred:$p, cc_out:$s)>;
5566
85aaf69f 5567// Likewise, "add Rd, mod_imm_neg" -> sub
223e47cc 5568def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
85aaf69f 5569 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
223e47cc 5570def : ARMInstAlias<"add${s}${p} $Rd, $imm",
85aaf69f
SL		 5571 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5572// Same for CMP <--> CMN via mod_imm_neg
223e47cc 5573def : ARMInstAlias<"cmp${p} $Rd, $imm",
85aaf69f 5574 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
223e47cc 5575def : ARMInstAlias<"cmn${p} $Rd, $imm",
85aaf69f 5576 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
223e47cc
LB		 5577
5578// The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5579// LSR, ROR, and RRX instructions.
5580// FIXME: We need C++ parser hooks to map the alias to the MOV
5581// encoding. It seems we should be able to do that sort of thing
5582// in tblgen, but it could get ugly.
5583let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5584def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5585 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5586 cc_out:$s)>;
5587def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5588 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5589 cc_out:$s)>;
5590def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5591 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5592 cc_out:$s)>;
5593def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5594 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5595 cc_out:$s)>;
5596}
5597def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
1a4d82fc 5598 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
223e47cc
LB		 5599let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5600def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5601 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5602 cc_out:$s)>;
5603def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5604 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5605 cc_out:$s)>;
5606def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5607 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5608 cc_out:$s)>;
5609def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5610 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5611 cc_out:$s)>;
5612}
5613
5614// "neg" is and alias for "rsb rd, rn, #0"
5615def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5616 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5617
5618// Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5619def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5620 Requires<[IsARM, NoV6]>;
5621
1a4d82fc
JJ		 5622// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5623// the instruction definitions need difference constraints pre-v6.
5624// Use these aliases for the assembly parsing on pre-v6.
5625def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5626 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5627 Requires<[IsARM, NoV6]>;
5628def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5629 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5630 pred:$p, cc_out:$s)>,
5631 Requires<[IsARM, NoV6]>;
5632def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5633 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5634 Requires<[IsARM, NoV6]>;
5635def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5636 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5637 Requires<[IsARM, NoV6]>;
223e47cc
LB		 5638def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5639 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5640 Requires<[IsARM, NoV6]>;
5641def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5642 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5643 Requires<[IsARM, NoV6]>;
5644
5645// 'it' blocks in ARM mode just validate the predicates. The IT itself
5646// is discarded.
1a4d82fc
JJ		 5647def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5648 ComplexDeprecationPredicate<"IT">;
85aaf69f
SL		 5649
5650let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5651def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5652 NoItinerary,
5653 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;
backport for Debian buster