[rustc.git] / src / llvm / lib / Target / Hexagon / Makefile

##===- lib/Target/Hexagon/Makefile -------------------------*- Makefile -*-===##
#
#                     The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = LLVMHexagonCodeGen
TARGET = Hexagon

# Make sure that tblgen is run, first thing.
BUILT_SOURCES = HexagonGenRegisterInfo.inc \
                HexagonGenInstrInfo.inc  \
                HexagonGenAsmWriter.inc \
                HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \\r
                HexagonGenCallingConv.inc \\r
                HexagonGenDFAPacketizer.inc \\r
                HexagonGenMCCodeEmitter.inc \\r
                HexagonGenDisassemblerTables.inc\r
\r
DIRS = TargetInfo MCTargetDesc Disassembler\r
\r
include $(LEVEL)/Makefile.common\r
Commit	Line	Data
223e47cc LB	1	##===- lib/Target/Hexagon/Makefile -------------------------- Makefile --===##
	2	#
	3	# The LLVM Compiler Infrastructure
	4	#
	5	# This file is distributed under the University of Illinois Open Source
	6	# License. See LICENSE.TXT for details.
	7	#
	8	##===----------------------------------------------------------------------===##
	9	LEVEL = ../../..
	10	LIBRARYNAME = LLVMHexagonCodeGen
	11	TARGET = Hexagon
	12
	13	# Make sure that tblgen is run, first thing.
	14	BUILT_SOURCES = HexagonGenRegisterInfo.inc \
	15	HexagonGenInstrInfo.inc \
	16	HexagonGenAsmWriter.inc \
85aaf69f SL	17	HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \\r
	18	HexagonGenCallingConv.inc \\r
	19	HexagonGenDFAPacketizer.inc \\r
	20	HexagonGenMCCodeEmitter.inc \\r
	21	HexagonGenDisassemblerTables.inc\r
	22	\r
	23	DIRS = TargetInfo MCTargetDesc Disassembler\r
	24	\r
	25	include $(LEVEL)/Makefile.common\r