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1 | //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file provides Mips specific target descriptions. | |
11 | // | |
12 | //===----------------------------------------------------------------------===// | |
13 | ||
1a4d82fc JJ |
14 | #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H |
15 | #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H | |
223e47cc LB |
16 | |
17 | #include "llvm/Support/DataTypes.h" | |
18 | ||
19 | namespace llvm { | |
20 | class MCAsmBackend; | |
21 | class MCCodeEmitter; | |
22 | class MCContext; | |
23 | class MCInstrInfo; | |
24 | class MCObjectWriter; | |
25 | class MCRegisterInfo; | |
26 | class MCSubtargetInfo; | |
27 | class StringRef; | |
28 | class Target; | |
29 | class raw_ostream; | |
30 | ||
31 | extern Target TheMipsTarget; | |
32 | extern Target TheMipselTarget; | |
33 | extern Target TheMips64Target; | |
34 | extern Target TheMips64elTarget; | |
35 | ||
36 | MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, | |
37 | const MCRegisterInfo &MRI, | |
38 | const MCSubtargetInfo &STI, | |
39 | MCContext &Ctx); | |
40 | MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, | |
41 | const MCRegisterInfo &MRI, | |
42 | const MCSubtargetInfo &STI, | |
43 | MCContext &Ctx); | |
44 | ||
1a4d82fc JJ |
45 | MCAsmBackend *createMipsAsmBackendEB32(const Target &T, |
46 | const MCRegisterInfo &MRI, StringRef TT, | |
223e47cc | 47 | StringRef CPU); |
1a4d82fc JJ |
48 | MCAsmBackend *createMipsAsmBackendEL32(const Target &T, |
49 | const MCRegisterInfo &MRI, StringRef TT, | |
223e47cc | 50 | StringRef CPU); |
1a4d82fc JJ |
51 | MCAsmBackend *createMipsAsmBackendEB64(const Target &T, |
52 | const MCRegisterInfo &MRI, StringRef TT, | |
223e47cc | 53 | StringRef CPU); |
1a4d82fc JJ |
54 | MCAsmBackend *createMipsAsmBackendEL64(const Target &T, |
55 | const MCRegisterInfo &MRI, StringRef TT, | |
223e47cc LB |
56 | StringRef CPU); |
57 | ||
58 | MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, | |
59 | uint8_t OSABI, | |
60 | bool IsLittleEndian, | |
61 | bool Is64Bit); | |
62 | } // End llvm namespace | |
63 | ||
64 | // Defines symbolic names for Mips registers. This defines a mapping from | |
65 | // register name to register number. | |
66 | #define GET_REGINFO_ENUM | |
67 | #include "MipsGenRegisterInfo.inc" | |
68 | ||
69 | // Defines symbolic names for the Mips instructions. | |
70 | #define GET_INSTRINFO_ENUM | |
71 | #include "MipsGenInstrInfo.inc" | |
72 | ||
73 | #define GET_SUBTARGETINFO_ENUM | |
74 | #include "MipsGenSubtargetInfo.inc" | |
75 | ||
76 | #endif |