]>
Commit | Line | Data |
---|---|---|
1a4d82fc JJ |
1 | let isCodeGenOnly = 1, Predicates = [InMicroMips] in { |
2 | def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, | |
3 | ADDS_FM_MM<0, 0x30>; | |
4 | def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, | |
5 | ADDS_FM_MM<0, 0xf0>; | |
6 | def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, | |
7 | ADDS_FM_MM<0, 0xb0>; | |
8 | def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, | |
9 | ADDS_FM_MM<0, 0x70>; | |
10 | ||
11 | def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, | |
12 | ADDS_FM_MM<1, 0x30>; | |
13 | def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, | |
14 | ADDS_FM_MM<1, 0xf0>; | |
15 | def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, | |
16 | ADDS_FM_MM<1, 0xb0>; | |
17 | def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, | |
18 | ADDS_FM_MM<1, 0x70>; | |
19 | ||
20 | def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>; | |
21 | def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, | |
22 | LW_FM_MM<0x26>; | |
23 | def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>; | |
24 | def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, | |
25 | LW_FM_MM<0x2e>; | |
26 | def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, | |
27 | LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6; | |
28 | def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, | |
29 | SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6; | |
30 | def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, | |
31 | LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6; | |
32 | def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, | |
33 | SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; | |
34 | ||
35 | def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, | |
36 | CEQS_FM_MM<0>; | |
37 | def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, | |
38 | CEQS_FM_MM<1>; | |
39 | ||
40 | def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>, | |
41 | BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; | |
42 | def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>, | |
43 | BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6; | |
44 | ||
45 | def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, | |
46 | ROUND_W_FM_MM<0, 0x6c>; | |
47 | def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, | |
48 | ROUND_W_FM_MM<0, 0x24>; | |
49 | def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, | |
50 | ROUND_W_FM_MM<0, 0x2c>; | |
51 | def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, | |
52 | ROUND_W_FM_MM<0, 0xec>; | |
53 | def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, | |
54 | ROUND_W_FM_MM<0, 0xac>; | |
55 | def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, | |
56 | fsqrt>, ROUND_W_FM_MM<0, 0x28>; | |
57 | ||
58 | def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, | |
59 | ROUND_W_FM_MM<1, 0x6c>; | |
60 | def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, | |
61 | ROUND_W_FM_MM<1, 0x24>; | |
62 | def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, | |
63 | ROUND_W_FM_MM<1, 0x2c>; | |
64 | def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>, | |
65 | ROUND_W_FM_MM<1, 0xec>; | |
66 | def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, | |
67 | ROUND_W_FM_MM<1, 0xac>; | |
68 | ||
69 | def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, | |
70 | fsqrt>, ROUND_W_FM_MM<1, 0x28>; | |
71 | ||
72 | def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, | |
73 | ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2; | |
74 | def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, | |
75 | ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2; | |
76 | ||
77 | def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, | |
78 | ABS_FM_MM<0, 0xd>; | |
79 | def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, | |
80 | ABS_FM_MM<0, 0x1>; | |
81 | def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, | |
82 | ABS_FM_MM<0, 0x2d>; | |
83 | def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, | |
84 | ABS_FM_MM<0, 0x4d>; | |
85 | def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, | |
86 | ABS_FM_MM<1, 0x4d>; | |
87 | def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, | |
88 | ABS_FM_MM<0, 0x6d>; | |
89 | def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, | |
90 | ABS_FM_MM<1, 0x6d>; | |
91 | ||
92 | def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, | |
93 | ABS_FM_MM<1, 0xd>; | |
94 | def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, | |
95 | ABS_FM_MM<1, 0x2d>; | |
96 | ||
97 | def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, | |
98 | ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>; | |
99 | ||
100 | def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, | |
101 | II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>; | |
102 | def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, | |
103 | II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>; | |
104 | def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, | |
105 | II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>; | |
106 | def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, | |
107 | II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>; | |
108 | ||
109 | def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, | |
110 | MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>; | |
111 | def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, | |
112 | MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>; | |
113 | def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, | |
114 | MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>; | |
115 | def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, | |
116 | MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>; | |
117 | ||
118 | def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, | |
119 | MFC1_FM_MM<0x40>; | |
120 | def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, | |
121 | MFC1_FM_MM<0x60>; | |
122 | def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, | |
123 | II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; | |
124 | def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, | |
125 | II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; | |
85aaf69f SL |
126 | def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, |
127 | MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; | |
128 | def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, | |
129 | MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; | |
1a4d82fc JJ |
130 | |
131 | def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, | |
132 | MADDS_FM_MM<0x1>; | |
133 | def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, | |
134 | MADDS_FM_MM<0x21>; | |
135 | def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, | |
136 | MADDS_FM_MM<0x2>; | |
137 | def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, | |
138 | MADDS_FM_MM<0x22>; | |
139 | ||
140 | def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, | |
141 | MADDS_FM_MM<0x9>; | |
142 | def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, | |
143 | MADDS_FM_MM<0x29>; | |
144 | def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, | |
145 | MADDS_FM_MM<0xa>; | |
146 | def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, | |
147 | MADDS_FM_MM<0x2a>; | |
148 | } |