[rustc.git] / src / llvm / lib / Target / Mips / Mips64r6InstrInfo.td

//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes Mips64r6 instructions.
//
//===----------------------------------------------------------------------===//

// Notes about removals/changes from MIPS32r6:
// Reencoded: dclo, dclz

//===----------------------------------------------------------------------===//
//
// Instruction Encodings
//
//===----------------------------------------------------------------------===//

class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
class DAUI_ENC    : DAUI_FM;
class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;

//===----------------------------------------------------------------------===//
//
// Instruction Descriptions
//
//===----------------------------------------------------------------------===//

class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
  dag OutOperandList = (outs GPROpnd:$rs);
  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
  string Constraints = "$rs = $rt";
}

class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2>;
class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;

//===----------------------------------------------------------------------===//
//
// Instruction Definitions
//
//===----------------------------------------------------------------------===//

def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
let DecoderNamespace = "Mips32r6_64r6_GP64" in {
  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
}

//===----------------------------------------------------------------------===//
//
// Instruction Aliases
//
//===----------------------------------------------------------------------===//

def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;

//===----------------------------------------------------------------------===//
//
// Patterns and Pseudo Instructions
//
//===----------------------------------------------------------------------===//

// i64 selects
def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, i64:$cond),
                    (SELEQZ64 i64:$f, i64:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
              (OR64 (SELEQZ64 i64:$t, i64:$cond),
                    (SELNEZ64 i64:$f, i64:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, i64:$cond),
                    (SELEQZ64 i64:$f, i64:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
              ISA_MIPS64R6;
def : MipsPat<
  (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
  (OR64 (SELEQZ64 i64:$t,
                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                 sub_32)),
        (SELNEZ64 i64:$f,
                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                 sub_32)))>,
  ISA_MIPS64R6;
def : MipsPat<
  (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
  (OR64 (SELEQZ64 i64:$t,
                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                 sub_32)),
        (SELNEZ64 i64:$f,
                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                 sub_32)))>,
  ISA_MIPS64R6;

def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
              (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
              (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
              (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
              (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;

// i64 selects from an i32 comparison
// One complicating factor here is that bits 32-63 of an i32 are undefined.
// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
//        This would allow us to remove the sign-extensions here.
def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
                                                      immZExt16:$imm))),
                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
                                                      immZExt16:$imm))))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
                                                      immZExt16:$imm))),
                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
                                                      immZExt16:$imm))))>,
              ISA_MIPS64R6;

def : MipsPat<(select i32:$cond, i64:$t, immz),
              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
              (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select i32:$cond, immz, i64:$f),
              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
              (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
              ISA_MIPS64R6;
Commit	Line	Data
1a4d82fc JJ	1	//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -- tablegen --=//
	2	//
	3	// The LLVM Compiler Infrastructure
	4	//
	5	// This file is distributed under the University of Illinois Open Source
	6	// License. See LICENSE.TXT for details.
	7	//
	8	//===----------------------------------------------------------------------===//
	9	//
	10	// This file describes Mips64r6 instructions.
	11	//
	12	//===----------------------------------------------------------------------===//
	13
	14	// Notes about removals/changes from MIPS32r6:
	15	// Reencoded: dclo, dclz
	16
	17	//===----------------------------------------------------------------------===//
	18	//
	19	// Instruction Encodings
	20	//
	21	//===----------------------------------------------------------------------===//
	22
	23	class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
	24	class DAUI_ENC : DAUI_FM;
	25	class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
	26	class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
	27	class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
	28	class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
	29	class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
	30	class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
	31	class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
	32	class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
	33	class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
	34	class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
	35	class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;
	36	class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
	37	class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
	38	class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
	39	class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
	40	class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
	41	class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
	42
	43	//===----------------------------------------------------------------------===//
	44	//
	45	// Instruction Descriptions
	46	//
	47	//===----------------------------------------------------------------------===//
	48
	49	class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
	50	dag OutOperandList = (outs GPROpnd:$rs);
	51	dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
	52	string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
	53	string Constraints = "$rs = $rt";
	54	}
	55
	56	class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
	57	class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
	58	class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
	59	class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
	60	class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
	61	class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
	62	class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
	63	class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
	64	class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
65	class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2>;
66	class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
67	class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
68	class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
69	class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
70	class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
71	class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
72	class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
73	class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
74	class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
75	class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
76	class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
77
78	//===----------------------------------------------------------------------===//
79	//
80	// Instruction Definitions
81	//
82	//===----------------------------------------------------------------------===//
83
84	def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
85	def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
86	def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
87	def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
88	def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
89	def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
90	def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
91	def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
92	def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
93	def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
94	def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
95	def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
96	def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
97	def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
98	def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
99	def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
100	def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
101	def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
102	def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
103	let DecoderNamespace = "Mips32r6_64r6_GP64" in {
104	def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
105	def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
106	}
107
108	//===----------------------------------------------------------------------===//
109	//
110	// Instruction Aliases
111	//
112	//===----------------------------------------------------------------------===//
113
114	def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
115
116	//===----------------------------------------------------------------------===//
117	//
118	// Patterns and Pseudo Instructions
119	//
120	//===----------------------------------------------------------------------===//
121
122	// i64 selects
123	def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
124	(OR64 (SELNEZ64 i64:$t, i64:$cond),
125	(SELEQZ64 i64:$f, i64:$cond))>,
126	ISA_MIPS64R6;
127	def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
128	(OR64 (SELEQZ64 i64:$t, i64:$cond),
129	(SELNEZ64 i64:$f, i64:$cond))>,
130	ISA_MIPS64R6;
131	def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
132	(OR64 (SELNEZ64 i64:$t, i64:$cond),
133	(SELEQZ64 i64:$f, i64:$cond))>,
134	ISA_MIPS64R6;
135	def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
136	(OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
137	(SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
138	ISA_MIPS64R6;
139	def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
140	(OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
141	(SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
142	ISA_MIPS64R6;
143	def : MipsPat<
144	(select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
145	(OR64 (SELEQZ64 i64:$t,
146	(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
147	sub_32)),
148	(SELNEZ64 i64:$f,
149	(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
150	sub_32)))>,
151	ISA_MIPS64R6;
152	def : MipsPat<
153	(select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
154	(OR64 (SELEQZ64 i64:$t,
155	(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
156	sub_32)),
157	(SELNEZ64 i64:$f,
158	(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
159	sub_32)))>,
160	ISA_MIPS64R6;
161
162	def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
163	(SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
164	def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
165	(SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
166	def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
167	(SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
168	def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
169	(SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
170
171	// i64 selects from an i32 comparison
172	// One complicating factor here is that bits 32-63 of an i32 are undefined.
173	// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
174	// This would allow us to remove the sign-extensions here.
175	def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
176	(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
177	(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
178	ISA_MIPS64R6;
179	def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
180	(OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
181	(SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
182	ISA_MIPS64R6;
183	def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
184	(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
185	(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
186	ISA_MIPS64R6;
187	def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
188	(OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
189	immZExt16:$imm))),
190	(SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
191	immZExt16:$imm))))>,
192	ISA_MIPS64R6;
193	def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
194	(OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
195	immZExt16:$imm))),
196	(SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
197	immZExt16:$imm))))>,
198	ISA_MIPS64R6;
199
200	def : MipsPat<(select i32:$cond, i64:$t, immz),
201	(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
202	ISA_MIPS64R6;
203	def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
204	(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
205	ISA_MIPS64R6;
206	def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
207	(SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
208	ISA_MIPS64R6;
209	def : MipsPat<(select i32:$cond, immz, i64:$f),
210	(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
211	ISA_MIPS64R6;
212	def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
213	(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
214	ISA_MIPS64R6;
215	def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
216	(SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
217	ISA_MIPS64R6;