projects / rustc.git / blame
| Commit | Line | Data |
|---|---|---|
| 223e47cc LB |
1 | //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===// |
| 2 | // | |
| 3 | // The LLVM Compiler Infrastructure | |
| 4 | // | |
| 5 | // This file is distributed under the University of Illinois Open Source | |
| 6 | // License. See LICENSE.TXT for details. | |
| 7 | // | |
| 8 | //===----------------------------------------------------------------------===// | |
| 9 | // | |
| 10 | // This is the Conditional Moves implementation. | |
| 11 | // | |
| 12 | //===----------------------------------------------------------------------===// | |
| 13 | ||
| 14 | // Conditional moves: | |
| 15 | // These instructions are expanded in | |
| 16 | // MipsISelLowering::EmitInstrWithCustomInserter if target does not have | |
| 17 | // conditional move instructions. | |
| 18 | // cond:int, data:int | |
| 1a4d82fc | 19 | class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, |
| 970d7e83 LB |
20 | InstrItinClass Itin> : |
| 21 | InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), | |
| 1a4d82fc | 22 | !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> { |
| 223e47cc LB |
23 | let Constraints = "$F = $rd"; |
| 24 | } | |
| 25 | ||
| 26 | // cond:int, data:float | |
| 1a4d82fc | 27 | class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, |
| 970d7e83 LB |
28 | InstrItinClass Itin> : |
| 29 | InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), | |
| 1a4d82fc | 30 | !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr> { |
| 223e47cc LB |
31 | let Constraints = "$F = $fd"; |
| 32 | } | |
| 33 | ||
| 34 | // cond:float, data:int | |
| 1a4d82fc | 35 | class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
| 970d7e83 | 36 | SDPatternOperator OpNode = null_frag> : |
| 1a4d82fc JJ |
37 | InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F), |
| 38 | !strconcat(opstr, "\t$rd, $rs, $fcc"), | |
| 39 | [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))], | |
| 40 | Itin, FrmFR, opstr> { | |
| 223e47cc LB |
41 | let Constraints = "$F = $rd"; |
| 42 | } | |
| 43 | ||
| 44 | // cond:float, data:float | |
| 1a4d82fc | 45 | class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, |
| 970d7e83 | 46 | SDPatternOperator OpNode = null_frag> : |
| 1a4d82fc JJ |
47 | InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F), |
| 48 | !strconcat(opstr, "\t$fd, $fs, $fcc"), | |
| 49 | [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))], | |
| 50 | Itin, FrmFR, opstr> { | |
| 223e47cc LB |
51 | let Constraints = "$F = $fd"; |
| 52 | } | |
| 53 | ||
| 54 | // select patterns | |
| 55 | multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC, | |
| 56 | Instruction MOVZInst, Instruction SLTOp, | |
| 57 | Instruction SLTuOp, Instruction SLTiOp, | |
| 58 | Instruction SLTiuOp> { | |
| 59 | def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), | |
| 60 | (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>; | |
| 970d7e83 LB |
61 | def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), |
| 62 | (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>; | |
| 63 | def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F), | |
| 64 | (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>; | |
| 65 | def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F), | |
| 66 | (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>; | |
| 67 | def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), | |
| 68 | (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>; | |
| 69 | def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), | |
| 70 | (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; | |
| 71 | def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), | |
| 72 | DRC:$T, DRC:$F), | |
| 73 | (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; | |
| 74 | def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), | |
| 75 | DRC:$T, DRC:$F), | |
| 76 | (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), | |
| 77 | DRC:$F)>; | |
| 223e47cc LB |
78 | } |
| 79 | ||
| 80 | multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC, | |
| 81 | Instruction MOVZInst, Instruction XOROp> { | |
| 82 | def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), | |
| 83 | (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; | |
| 84 | def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F), | |
| 85 | (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; | |
| 86 | } | |
| 87 | ||
| 88 | multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC, | |
| 89 | Instruction MOVZInst, Instruction XORiOp> { | |
| 90 | def : MipsPat< | |
| 91 | (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), | |
| 92 | (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; | |
| 93 | } | |
| 94 | ||
| 95 | multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, | |
| 96 | Instruction XOROp> { | |
| 97 | def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), | |
| 98 | (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; | |
| 99 | def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F), | |
| 100 | (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>; | |
| 101 | def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F), | |
| 102 | (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>; | |
| 103 | } | |
| 104 | ||
| 105 | // Instantiation of instructions. | |
| 1a4d82fc JJ |
106 | def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>, |
| 107 | ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc | 108 | |
| 1a4d82fc JJ |
109 | let isCodeGenOnly = 1 in { |
| 110 | def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>, | |
| 111 | ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 112 | def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>, | |
| 113 | ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 114 | def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>, | |
| 115 | ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc LB |
116 | } |
| 117 | ||
| 1a4d82fc JJ |
118 | def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>, |
| 119 | ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc | 120 | |
| 1a4d82fc JJ |
121 | let isCodeGenOnly = 1 in { |
| 122 | def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, | |
| 123 | ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 124 | def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, | |
| 125 | ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 126 | def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, | |
| 127 | ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc LB |
128 | } |
| 129 | ||
| 1a4d82fc JJ |
130 | def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, |
| 131 | CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 132 | ||
| 133 | let isCodeGenOnly = 1 in | |
| 134 | def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, | |
| 135 | CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 136 | AdditionalRequires<[HasMips64]>; | |
| 137 | ||
| 138 | def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, | |
| 139 | CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 140 | ||
| 141 | let isCodeGenOnly = 1 in | |
| 142 | def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, | |
| 143 | CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 144 | AdditionalRequires<[IsGP64bit]>; | |
| 145 | ||
| 146 | def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, | |
| 147 | II_MOVZ_D>, CMov_I_F_FM<18, 17>, | |
| 148 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; | |
| 149 | def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, | |
| 150 | II_MOVN_D>, CMov_I_F_FM<19, 17>, | |
| 151 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; | |
| 152 | ||
| 153 | let DecoderNamespace = "Mips64" in { | |
| 154 | def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, | |
| 155 | CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 156 | def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, | |
| 157 | CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 158 | let isCodeGenOnly = 1 in { | |
| 159 | def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, | |
| 160 | CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 161 | def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>, | |
| 162 | CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 223e47cc LB |
163 | } |
| 164 | } | |
| 165 | ||
| 1a4d82fc JJ |
166 | def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, |
| 167 | CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc | 168 | |
| 1a4d82fc JJ |
169 | let isCodeGenOnly = 1 in |
| 170 | def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, | |
| 171 | CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 172 | AdditionalRequires<[IsGP64bit]>; | |
| 223e47cc | 173 | |
| 1a4d82fc JJ |
174 | def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, |
| 175 | CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc | 176 | |
| 1a4d82fc JJ |
177 | let isCodeGenOnly = 1 in |
| 178 | def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, | |
| 179 | CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 180 | AdditionalRequires<[IsGP64bit]>; | |
| 181 | ||
| 182 | def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, | |
| 183 | CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 184 | def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, | |
| 185 | CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 186 | ||
| 187 | def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, | |
| 188 | MipsCMovFP_T>, CMov_F_F_FM<17, 1>, | |
| 189 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; | |
| 190 | def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, | |
| 191 | MipsCMovFP_F>, CMov_F_F_FM<17, 0>, | |
| 192 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; | |
| 193 | ||
| 194 | let DecoderNamespace = "Mips64" in { | |
| 195 | def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, | |
| 196 | CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 197 | def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, | |
| 198 | CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 223e47cc LB |
199 | } |
| 200 | ||
| 201 | // Instantiation of conditional move patterns. | |
| 1a4d82fc JJ |
202 | defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>, |
| 203 | INSN_MIPS4_32_NOT_32R6_64R6; | |
| 204 | defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 205 | defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 223e47cc | 206 | |
| 1a4d82fc JJ |
207 | defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>, |
| 208 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 209 | defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>, | |
| 210 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 211 | defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>, | |
| 212 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 213 | defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>, | |
| 214 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 215 | defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>, | |
| 216 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 217 | defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>, | |
| 218 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 219 | defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>, | |
| 220 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 221 | defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>, | |
| 222 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 223 | defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>, | |
| 224 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 223e47cc | 225 | |
| 1a4d82fc | 226 | defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; |
| 223e47cc | 227 | |
| 1a4d82fc JJ |
228 | defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, |
| 229 | GPR_64; | |
| 230 | defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 231 | GPR_64; | |
| 232 | defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 233 | GPR_64; | |
| 234 | ||
| 235 | defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>, | |
| 236 | INSN_MIPS4_32_NOT_32R6_64R6; | |
| 237 | defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 238 | defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; | |
| 239 | ||
| 240 | defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>, | |
| 241 | INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; | |
| 242 | defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 243 | GPR_64; | |
| 244 | defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 245 | GPR_64; | |
| 246 | ||
| 247 | defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>, | |
| 248 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; | |
| 249 | defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 250 | FGR_32; | |
| 251 | defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 252 | FGR_32; | |
| 253 | ||
| 254 | defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>, | |
| 255 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 256 | defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>, | |
| 257 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 258 | defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 259 | FGR_64; | |
| 260 | defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>, | |
| 261 | INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; | |
| 262 | defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 263 | FGR_64; | |
| 264 | defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, | |
| 265 | FGR_64; | |
| 85aaf69f SL |
266 | |
| 267 | // For targets that don't have conditional-move instructions | |
| 268 | // we have to match SELECT nodes with pseudo instructions. | |
| 269 | let usesCustomInserter = 1 in { | |
| 270 | class Select_Pseudo<RegisterOperand RC> : | |
| 271 | PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), | |
| 272 | [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>, | |
| 273 | ISA_MIPS1_NOT_4_32; | |
| 274 | ||
| 275 | class SelectFP_Pseudo_T<RegisterOperand RC> : | |
| 276 | PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), | |
| 277 | [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>, | |
| 278 | ISA_MIPS1_NOT_4_32; | |
| 279 | ||
| 280 | class SelectFP_Pseudo_F<RegisterOperand RC> : | |
| 281 | PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), | |
| 282 | [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>, | |
| 283 | ISA_MIPS1_NOT_4_32; | |
| 284 | } | |
| 285 | ||
| 286 | def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>; | |
| 287 | def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>; | |
| 288 | def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>; | |
| 289 | def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32; | |
| 290 | def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64; | |
| 291 | ||
| 292 | def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>; | |
| 293 | def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>; | |
| 294 | def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>; | |
| 295 | def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32; | |
| 296 | def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64; | |
| 297 | ||
| 298 | def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>; | |
| 299 | def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>; | |
| 300 | def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>; | |
| 301 | def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32; | |
| 302 | def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64; |