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1 | //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file describes Mips DSP ASE instructions. | |
11 | // | |
12 | //===----------------------------------------------------------------------===// | |
13 | ||
14 | // ImmLeaf | |
15 | def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; | |
16 | def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; | |
17 | def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; | |
18 | def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; | |
19 | def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; | |
20 | def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; | |
21 | ||
22 | // Mips-specific dsp nodes | |
1a4d82fc JJ |
23 | def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, |
24 | SDTCisVT<2, untyped>]>; | |
25 | def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, | |
26 | SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>; | |
27 | def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, | |
28 | SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; | |
29 | def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, | |
30 | SDTCisVT<2, i32>]>; | |
223e47cc LB |
31 | |
32 | class MipsDSPBase<string Opc, SDTypeProfile Prof> : | |
1a4d82fc | 33 | SDNode<!strconcat("MipsISD::", Opc), Prof>; |
223e47cc LB |
34 | |
35 | class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : | |
1a4d82fc | 36 | SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>; |
223e47cc LB |
37 | |
38 | def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; | |
39 | def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; | |
40 | def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; | |
41 | def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; | |
42 | def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; | |
43 | def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; | |
44 | ||
45 | def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; | |
1a4d82fc | 46 | def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>; |
223e47cc LB |
47 | |
48 | def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; | |
49 | def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; | |
50 | def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; | |
51 | def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; | |
52 | def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; | |
53 | ||
54 | def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; | |
55 | def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; | |
56 | def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; | |
57 | def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; | |
58 | def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; | |
59 | def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; | |
60 | def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; | |
61 | def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; | |
62 | ||
63 | def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; | |
64 | def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; | |
65 | def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; | |
66 | def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; | |
67 | def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; | |
68 | def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; | |
69 | def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; | |
70 | def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; | |
71 | def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; | |
72 | ||
73 | def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; | |
74 | def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; | |
75 | def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; | |
76 | def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; | |
77 | def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; | |
78 | def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; | |
1a4d82fc JJ |
79 | def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>; |
80 | def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>; | |
81 | def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>; | |
82 | def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>; | |
83 | def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>; | |
223e47cc LB |
84 | |
85 | // Flags. | |
1a4d82fc JJ |
86 | class Uses<list<Register> Regs> { |
87 | list<Register> Uses = Regs; | |
223e47cc LB |
88 | } |
89 | ||
1a4d82fc JJ |
90 | class Defs<list<Register> Regs> { |
91 | list<Register> Defs = Regs; | |
223e47cc LB |
92 | } |
93 | ||
94 | // Instruction encoding. | |
95 | class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; | |
96 | class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; | |
97 | class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; | |
98 | class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; | |
99 | class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; | |
100 | class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; | |
101 | class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; | |
102 | class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; | |
103 | class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; | |
104 | class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; | |
105 | class ADDSC_ENC : ADDU_QB_FMT<0b10000>; | |
106 | class ADDWC_ENC : ADDU_QB_FMT<0b10001>; | |
107 | class MODSUB_ENC : ADDU_QB_FMT<0b10010>; | |
108 | class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; | |
109 | class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; | |
110 | class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; | |
111 | class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; | |
112 | class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; | |
113 | class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; | |
114 | class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; | |
115 | class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; | |
116 | class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; | |
117 | class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; | |
118 | class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; | |
119 | class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; | |
120 | class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; | |
121 | class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; | |
122 | class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; | |
123 | class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; | |
124 | class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; | |
125 | class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; | |
126 | class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; | |
127 | class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; | |
128 | class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; | |
129 | class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; | |
130 | class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; | |
131 | class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; | |
132 | class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; | |
133 | class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; | |
134 | class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; | |
135 | class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; | |
136 | class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; | |
137 | class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; | |
138 | class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; | |
139 | class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; | |
140 | class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; | |
141 | class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; | |
142 | class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; | |
143 | class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; | |
144 | class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; | |
145 | class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; | |
146 | class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; | |
147 | class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; | |
148 | class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; | |
149 | class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; | |
150 | class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; | |
1a4d82fc JJ |
151 | class MFHI_ENC : MFHI_FMT<0b010000>; |
152 | class MFLO_ENC : MFHI_FMT<0b010010>; | |
153 | class MTHI_ENC : MTHI_FMT<0b010001>; | |
154 | class MTLO_ENC : MTHI_FMT<0b010011>; | |
223e47cc LB |
155 | class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; |
156 | class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; | |
157 | class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; | |
158 | class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; | |
159 | class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; | |
160 | class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; | |
161 | class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; | |
162 | class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; | |
163 | class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; | |
164 | class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; | |
165 | class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; | |
166 | class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; | |
167 | class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; | |
168 | class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; | |
169 | class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; | |
170 | class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; | |
171 | class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; | |
172 | class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; | |
173 | class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; | |
174 | class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; | |
175 | class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; | |
176 | class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; | |
177 | class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; | |
178 | class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; | |
179 | class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; | |
180 | class REPL_QB_ENC : REPL_FMT<0b00010>; | |
181 | class REPL_PH_ENC : REPL_FMT<0b01010>; | |
182 | class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; | |
183 | class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; | |
184 | class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; | |
185 | class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; | |
186 | class LWX_ENC : LX_FMT<0b00000>; | |
187 | class LHX_ENC : LX_FMT<0b00100>; | |
188 | class LBUX_ENC : LX_FMT<0b00110>; | |
189 | class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; | |
190 | class INSV_ENC : INSV_FMT<0b001100>; | |
191 | ||
192 | class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; | |
193 | class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; | |
194 | class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; | |
195 | class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; | |
196 | class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; | |
197 | class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; | |
198 | class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; | |
199 | class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; | |
200 | class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; | |
201 | class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; | |
202 | class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; | |
203 | class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; | |
204 | class SHILO_ENC : SHILO_R1_FMT<0b11010>; | |
205 | class SHILOV_ENC : SHILO_R2_FMT<0b11011>; | |
206 | class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; | |
207 | ||
208 | class RDDSP_ENC : RDDSP_FMT<0b10010>; | |
209 | class WRDSP_ENC : WRDSP_FMT<0b10011>; | |
210 | class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; | |
211 | class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; | |
212 | class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; | |
213 | class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; | |
214 | class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; | |
215 | class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; | |
216 | class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; | |
217 | class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; | |
218 | class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; | |
219 | class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; | |
220 | class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; | |
221 | class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; | |
222 | class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; | |
223 | class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; | |
224 | class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; | |
225 | class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; | |
226 | class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; | |
227 | class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; | |
228 | class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; | |
229 | class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; | |
230 | class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; | |
231 | class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; | |
232 | class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; | |
233 | class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; | |
234 | class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; | |
235 | class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; | |
236 | class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; | |
237 | class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; | |
238 | class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; | |
239 | class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; | |
240 | class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; | |
241 | class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; | |
242 | class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; | |
243 | class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; | |
244 | class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; | |
245 | class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; | |
246 | class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; | |
247 | class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; | |
248 | class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; | |
249 | class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; | |
250 | class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; | |
251 | class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; | |
252 | class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; | |
253 | class APPEND_ENC : APPEND_FMT<0b00000>; | |
254 | class BALIGN_ENC : APPEND_FMT<0b10000>; | |
255 | class PREPEND_ENC : APPEND_FMT<0b00001>; | |
256 | ||
257 | // Instruction desc. | |
258 | class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
259 | InstrItinClass itin, RegisterOperand ROD, |
260 | RegisterOperand ROS, RegisterOperand ROT = ROS> { | |
261 | dag OutOperandList = (outs ROD:$rd); | |
262 | dag InOperandList = (ins ROS:$rs, ROT:$rt); | |
223e47cc | 263 | string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); |
1a4d82fc | 264 | list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; |
223e47cc | 265 | InstrItinClass Itinerary = itin; |
223e47cc LB |
266 | } |
267 | ||
268 | class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
269 | InstrItinClass itin, RegisterOperand ROD, |
270 | RegisterOperand ROS = ROD> { | |
271 | dag OutOperandList = (outs ROD:$rd); | |
272 | dag InOperandList = (ins ROS:$rs); | |
223e47cc | 273 | string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); |
1a4d82fc | 274 | list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))]; |
223e47cc | 275 | InstrItinClass Itinerary = itin; |
223e47cc LB |
276 | } |
277 | ||
278 | class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
279 | InstrItinClass itin, RegisterOperand ROS, |
280 | RegisterOperand ROT = ROS> { | |
223e47cc | 281 | dag OutOperandList = (outs); |
1a4d82fc | 282 | dag InOperandList = (ins ROS:$rs, ROT:$rt); |
223e47cc | 283 | string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); |
1a4d82fc | 284 | list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)]; |
223e47cc | 285 | InstrItinClass Itinerary = itin; |
223e47cc LB |
286 | } |
287 | ||
288 | class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
289 | InstrItinClass itin, RegisterOperand ROD, |
290 | RegisterOperand ROS, RegisterOperand ROT = ROS> { | |
291 | dag OutOperandList = (outs ROD:$rd); | |
292 | dag InOperandList = (ins ROS:$rs, ROT:$rt); | |
223e47cc | 293 | string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); |
1a4d82fc | 294 | list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; |
223e47cc | 295 | InstrItinClass Itinerary = itin; |
223e47cc LB |
296 | } |
297 | ||
298 | class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
299 | InstrItinClass itin, RegisterOperand ROT, |
300 | RegisterOperand ROS = ROT> { | |
301 | dag OutOperandList = (outs ROT:$rt); | |
302 | dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src); | |
223e47cc | 303 | string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); |
1a4d82fc | 304 | list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))]; |
223e47cc | 305 | InstrItinClass Itinerary = itin; |
223e47cc LB |
306 | string Constraints = "$src = $rt"; |
307 | } | |
308 | ||
309 | class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
310 | InstrItinClass itin, RegisterOperand ROD, |
311 | RegisterOperand ROT = ROD> { | |
312 | dag OutOperandList = (outs ROD:$rd); | |
313 | dag InOperandList = (ins ROT:$rt); | |
223e47cc | 314 | string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); |
1a4d82fc | 315 | list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))]; |
223e47cc | 316 | InstrItinClass Itinerary = itin; |
223e47cc LB |
317 | } |
318 | ||
319 | class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
320 | ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> { |
321 | dag OutOperandList = (outs RO:$rd); | |
223e47cc LB |
322 | dag InOperandList = (ins uimm16:$imm); |
323 | string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); | |
1a4d82fc | 324 | list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))]; |
223e47cc | 325 | InstrItinClass Itinerary = itin; |
223e47cc LB |
326 | } |
327 | ||
328 | class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
329 | InstrItinClass itin, RegisterOperand RO> { |
330 | dag OutOperandList = (outs RO:$rd); | |
331 | dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa); | |
223e47cc | 332 | string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); |
1a4d82fc | 333 | list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))]; |
223e47cc | 334 | InstrItinClass Itinerary = itin; |
223e47cc LB |
335 | } |
336 | ||
337 | class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
338 | SDPatternOperator ImmPat, InstrItinClass itin, | |
1a4d82fc JJ |
339 | RegisterOperand RO> { |
340 | dag OutOperandList = (outs RO:$rd); | |
341 | dag InOperandList = (ins RO:$rt, uimm16:$rs_sa); | |
223e47cc | 342 | string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); |
1a4d82fc | 343 | list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))]; |
223e47cc | 344 | InstrItinClass Itinerary = itin; |
1a4d82fc | 345 | bit hasSideEffects = 1; |
223e47cc LB |
346 | } |
347 | ||
348 | class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
349 | InstrItinClass itin> { | |
1a4d82fc JJ |
350 | dag OutOperandList = (outs GPR32Opnd:$rd); |
351 | dag InOperandList = (ins PtrRC:$base, PtrRC:$index); | |
223e47cc | 352 | string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); |
1a4d82fc | 353 | list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))]; |
223e47cc | 354 | InstrItinClass Itinerary = itin; |
223e47cc LB |
355 | bit mayLoad = 1; |
356 | } | |
357 | ||
358 | class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
1a4d82fc JJ |
359 | InstrItinClass itin, RegisterOperand ROD, |
360 | RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> { | |
361 | dag OutOperandList = (outs ROD:$rd); | |
362 | dag InOperandList = (ins ROS:$rs, ROT:$rt); | |
223e47cc | 363 | string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); |
1a4d82fc | 364 | list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; |
223e47cc | 365 | InstrItinClass Itinerary = itin; |
223e47cc LB |
366 | } |
367 | ||
368 | class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
369 | SDPatternOperator ImmOp, InstrItinClass itin> { | |
1a4d82fc JJ |
370 | dag OutOperandList = (outs GPR32Opnd:$rt); |
371 | dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src); | |
223e47cc | 372 | string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); |
1a4d82fc JJ |
373 | list<dag> Pattern = [(set GPR32Opnd:$rt, |
374 | (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))]; | |
223e47cc | 375 | InstrItinClass Itinerary = itin; |
223e47cc LB |
376 | string Constraints = "$src = $rt"; |
377 | } | |
378 | ||
379 | class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
380 | InstrItinClass itin> { | |
1a4d82fc JJ |
381 | dag OutOperandList = (outs GPR32Opnd:$rt); |
382 | dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs); | |
223e47cc LB |
383 | string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); |
384 | InstrItinClass Itinerary = itin; | |
223e47cc LB |
385 | } |
386 | ||
387 | class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
388 | InstrItinClass itin> { | |
1a4d82fc JJ |
389 | dag OutOperandList = (outs GPR32Opnd:$rt); |
390 | dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs); | |
223e47cc LB |
391 | string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); |
392 | InstrItinClass Itinerary = itin; | |
223e47cc LB |
393 | } |
394 | ||
1a4d82fc JJ |
395 | class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { |
396 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
397 | dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin); | |
223e47cc | 398 | string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); |
1a4d82fc JJ |
399 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, |
400 | (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))]; | |
401 | string Constraints = "$acin = $ac"; | |
223e47cc LB |
402 | } |
403 | ||
1a4d82fc JJ |
404 | class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { |
405 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
406 | dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin); | |
223e47cc | 407 | string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); |
1a4d82fc JJ |
408 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, |
409 | (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))]; | |
410 | string Constraints = "$acin = $ac"; | |
223e47cc LB |
411 | } |
412 | ||
1a4d82fc JJ |
413 | class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { |
414 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
415 | dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin); | |
223e47cc | 416 | string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); |
1a4d82fc JJ |
417 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, |
418 | (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))]; | |
419 | string Constraints = "$acin = $ac"; | |
223e47cc LB |
420 | } |
421 | ||
422 | class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
423 | InstrItinClass itin> { | |
1a4d82fc | 424 | dag OutOperandList = (outs GPR32Opnd:$rd); |
223e47cc LB |
425 | dag InOperandList = (ins uimm16:$mask); |
426 | string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); | |
1a4d82fc | 427 | list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))]; |
223e47cc | 428 | InstrItinClass Itinerary = itin; |
223e47cc LB |
429 | } |
430 | ||
431 | class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
432 | InstrItinClass itin> { | |
433 | dag OutOperandList = (outs); | |
1a4d82fc | 434 | dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask); |
223e47cc | 435 | string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); |
1a4d82fc | 436 | list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)]; |
223e47cc | 437 | InstrItinClass Itinerary = itin; |
223e47cc LB |
438 | } |
439 | ||
1a4d82fc JJ |
440 | class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { |
441 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
442 | dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin); | |
443 | string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); | |
444 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, | |
445 | (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; | |
446 | string Constraints = "$acin = $ac"; | |
447 | } | |
448 | ||
449 | class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
450 | InstrItinClass itin> { | |
451 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
452 | dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt); | |
453 | string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); | |
454 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))]; | |
223e47cc | 455 | InstrItinClass Itinerary = itin; |
1a4d82fc | 456 | bit isCommutable = 1; |
223e47cc LB |
457 | } |
458 | ||
1a4d82fc JJ |
459 | class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
460 | InstrItinClass itin> { | |
461 | dag OutOperandList = (outs ACC64DSPOpnd:$ac); | |
462 | dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin); | |
223e47cc | 463 | string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); |
1a4d82fc JJ |
464 | list<dag> Pattern = [(set ACC64DSPOpnd:$ac, |
465 | (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; | |
466 | InstrItinClass Itinerary = itin; | |
467 | string Constraints = "$acin = $ac"; | |
223e47cc LB |
468 | } |
469 | ||
1a4d82fc JJ |
470 | class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode, |
471 | InstrItinClass itin> { | |
472 | dag OutOperandList = (outs GPR32Opnd:$rd); | |
473 | dag InOperandList = (ins RO:$ac); | |
474 | string AsmString = !strconcat(instr_asm, "\t$rd, $ac"); | |
475 | list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))]; | |
223e47cc LB |
476 | InstrItinClass Itinerary = itin; |
477 | } | |
478 | ||
1a4d82fc JJ |
479 | class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> { |
480 | dag OutOperandList = (outs RO:$ac); | |
481 | dag InOperandList = (ins GPR32Opnd:$rs); | |
482 | string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); | |
483 | InstrItinClass Itinerary = itin; | |
223e47cc LB |
484 | } |
485 | ||
486 | class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : | |
1a4d82fc | 487 | MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> { |
223e47cc LB |
488 | bit usesCustomInserter = 1; |
489 | } | |
490 | ||
491 | class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { | |
492 | dag OutOperandList = (outs); | |
493 | dag InOperandList = (ins brtarget:$offset); | |
494 | string AsmString = !strconcat(instr_asm, "\t$offset"); | |
495 | InstrItinClass Itinerary = itin; | |
223e47cc LB |
496 | bit isBranch = 1; |
497 | bit isTerminator = 1; | |
498 | bit hasDelaySlot = 1; | |
499 | } | |
500 | ||
501 | class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, | |
502 | InstrItinClass itin> { | |
1a4d82fc JJ |
503 | dag OutOperandList = (outs GPR32Opnd:$rt); |
504 | dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs); | |
223e47cc | 505 | string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); |
1a4d82fc | 506 | list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))]; |
223e47cc | 507 | InstrItinClass Itinerary = itin; |
223e47cc LB |
508 | string Constraints = "$src = $rt"; |
509 | } | |
510 | ||
511 | //===----------------------------------------------------------------------===// | |
512 | // MIPS DSP Rev 1 | |
513 | //===----------------------------------------------------------------------===// | |
514 | ||
515 | // Addition/subtraction | |
1a4d82fc JJ |
516 | class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary, |
517 | DSPROpnd, DSPROpnd>, IsCommutable, | |
518 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
519 | |
520 | class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, | |
1a4d82fc JJ |
521 | NoItinerary, DSPROpnd, DSPROpnd>, |
522 | IsCommutable, Defs<[DSPOutFlag20]>; | |
223e47cc | 523 | |
1a4d82fc JJ |
524 | class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary, |
525 | DSPROpnd, DSPROpnd>, | |
526 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
527 | |
528 | class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, | |
1a4d82fc JJ |
529 | NoItinerary, DSPROpnd, DSPROpnd>, |
530 | Defs<[DSPOutFlag20]>; | |
223e47cc | 531 | |
1a4d82fc JJ |
532 | class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary, |
533 | DSPROpnd, DSPROpnd>, IsCommutable, | |
534 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
535 | |
536 | class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, | |
1a4d82fc JJ |
537 | NoItinerary, DSPROpnd, DSPROpnd>, |
538 | IsCommutable, Defs<[DSPOutFlag20]>; | |
223e47cc | 539 | |
1a4d82fc JJ |
540 | class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary, |
541 | DSPROpnd, DSPROpnd>, | |
542 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
543 | |
544 | class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, | |
1a4d82fc JJ |
545 | NoItinerary, DSPROpnd, DSPROpnd>, |
546 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
547 | |
548 | class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, | |
1a4d82fc JJ |
549 | NoItinerary, GPR32Opnd, GPR32Opnd>, |
550 | IsCommutable, Defs<[DSPOutFlag20]>; | |
223e47cc LB |
551 | |
552 | class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, | |
1a4d82fc JJ |
553 | NoItinerary, GPR32Opnd, GPR32Opnd>, |
554 | Defs<[DSPOutFlag20]>; | |
223e47cc | 555 | |
1a4d82fc JJ |
556 | class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary, |
557 | GPR32Opnd, GPR32Opnd>, IsCommutable, | |
558 | Defs<[DSPCarry]>; | |
223e47cc | 559 | |
1a4d82fc JJ |
560 | class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary, |
561 | GPR32Opnd, GPR32Opnd>, | |
562 | IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>; | |
223e47cc LB |
563 | |
564 | class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, | |
1a4d82fc | 565 | GPR32Opnd, GPR32Opnd>; |
223e47cc LB |
566 | |
567 | class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, | |
1a4d82fc | 568 | NoItinerary, GPR32Opnd, DSPROpnd>; |
223e47cc LB |
569 | |
570 | // Absolute value | |
571 | class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, | |
1a4d82fc JJ |
572 | NoItinerary, DSPROpnd>, |
573 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
574 | |
575 | class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, | |
1a4d82fc JJ |
576 | NoItinerary, GPR32Opnd>, |
577 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
578 | |
579 | // Precision reduce/expand | |
580 | class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", | |
581 | int_mips_precrq_qb_ph, | |
1a4d82fc | 582 | NoItinerary, DSPROpnd, DSPROpnd>; |
223e47cc LB |
583 | |
584 | class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", | |
585 | int_mips_precrq_ph_w, | |
1a4d82fc | 586 | NoItinerary, DSPROpnd, GPR32Opnd>; |
223e47cc LB |
587 | |
588 | class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", | |
589 | int_mips_precrq_rs_ph_w, | |
1a4d82fc JJ |
590 | NoItinerary, DSPROpnd, |
591 | GPR32Opnd>, | |
592 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
593 | |
594 | class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", | |
595 | int_mips_precrqu_s_qb_ph, | |
1a4d82fc JJ |
596 | NoItinerary, DSPROpnd, |
597 | DSPROpnd>, | |
598 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
599 | |
600 | class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", | |
601 | int_mips_preceq_w_phl, | |
1a4d82fc | 602 | NoItinerary, GPR32Opnd, DSPROpnd>; |
223e47cc LB |
603 | |
604 | class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", | |
605 | int_mips_preceq_w_phr, | |
1a4d82fc | 606 | NoItinerary, GPR32Opnd, DSPROpnd>; |
223e47cc LB |
607 | |
608 | class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", | |
609 | int_mips_precequ_ph_qbl, | |
1a4d82fc | 610 | NoItinerary, DSPROpnd>; |
223e47cc LB |
611 | |
612 | class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", | |
613 | int_mips_precequ_ph_qbr, | |
1a4d82fc | 614 | NoItinerary, DSPROpnd>; |
223e47cc LB |
615 | |
616 | class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", | |
617 | int_mips_precequ_ph_qbla, | |
1a4d82fc | 618 | NoItinerary, DSPROpnd>; |
223e47cc LB |
619 | |
620 | class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", | |
621 | int_mips_precequ_ph_qbra, | |
1a4d82fc | 622 | NoItinerary, DSPROpnd>; |
223e47cc LB |
623 | |
624 | class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", | |
625 | int_mips_preceu_ph_qbl, | |
1a4d82fc | 626 | NoItinerary, DSPROpnd>; |
223e47cc LB |
627 | |
628 | class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", | |
629 | int_mips_preceu_ph_qbr, | |
1a4d82fc | 630 | NoItinerary, DSPROpnd>; |
223e47cc LB |
631 | |
632 | class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", | |
633 | int_mips_preceu_ph_qbla, | |
1a4d82fc | 634 | NoItinerary, DSPROpnd>; |
223e47cc LB |
635 | |
636 | class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", | |
637 | int_mips_preceu_ph_qbra, | |
1a4d82fc | 638 | NoItinerary, DSPROpnd>; |
223e47cc LB |
639 | |
640 | // Shift | |
1a4d82fc JJ |
641 | class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3, |
642 | NoItinerary, DSPROpnd>, | |
643 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
644 | |
645 | class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, | |
1a4d82fc JJ |
646 | NoItinerary, DSPROpnd>, |
647 | Defs<[DSPOutFlag22]>; | |
223e47cc | 648 | |
1a4d82fc JJ |
649 | class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3, |
650 | NoItinerary, DSPROpnd>; | |
223e47cc LB |
651 | |
652 | class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, | |
1a4d82fc | 653 | NoItinerary, DSPROpnd>; |
223e47cc | 654 | |
1a4d82fc JJ |
655 | class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4, |
656 | NoItinerary, DSPROpnd>, | |
657 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
658 | |
659 | class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, | |
1a4d82fc JJ |
660 | NoItinerary, DSPROpnd>, |
661 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
662 | |
663 | class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, | |
1a4d82fc JJ |
664 | immZExt4, NoItinerary, DSPROpnd>, |
665 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
666 | |
667 | class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, | |
1a4d82fc JJ |
668 | NoItinerary, DSPROpnd>, |
669 | Defs<[DSPOutFlag22]>; | |
223e47cc | 670 | |
1a4d82fc JJ |
671 | class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4, |
672 | NoItinerary, DSPROpnd>; | |
223e47cc LB |
673 | |
674 | class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, | |
1a4d82fc | 675 | NoItinerary, DSPROpnd>; |
223e47cc LB |
676 | |
677 | class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, | |
1a4d82fc | 678 | immZExt4, NoItinerary, DSPROpnd>; |
223e47cc LB |
679 | |
680 | class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, | |
1a4d82fc | 681 | NoItinerary, DSPROpnd>; |
223e47cc LB |
682 | |
683 | class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, | |
1a4d82fc JJ |
684 | immZExt5, NoItinerary, GPR32Opnd>, |
685 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
686 | |
687 | class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, | |
1a4d82fc JJ |
688 | NoItinerary, GPR32Opnd>, |
689 | Defs<[DSPOutFlag22]>; | |
223e47cc LB |
690 | |
691 | class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, | |
1a4d82fc | 692 | immZExt5, NoItinerary, GPR32Opnd>; |
223e47cc LB |
693 | |
694 | class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, | |
1a4d82fc | 695 | NoItinerary, GPR32Opnd>; |
223e47cc LB |
696 | |
697 | // Multiplication | |
698 | class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", | |
699 | int_mips_muleu_s_ph_qbl, | |
1a4d82fc JJ |
700 | NoItinerary, DSPROpnd, DSPROpnd>, |
701 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
702 | |
703 | class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", | |
704 | int_mips_muleu_s_ph_qbr, | |
1a4d82fc JJ |
705 | NoItinerary, DSPROpnd, DSPROpnd>, |
706 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
707 | |
708 | class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", | |
709 | int_mips_muleq_s_w_phl, | |
1a4d82fc JJ |
710 | NoItinerary, GPR32Opnd, DSPROpnd>, |
711 | IsCommutable, Defs<[DSPOutFlag21]>; | |
223e47cc LB |
712 | |
713 | class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", | |
714 | int_mips_muleq_s_w_phr, | |
1a4d82fc JJ |
715 | NoItinerary, GPR32Opnd, DSPROpnd>, |
716 | IsCommutable, Defs<[DSPOutFlag21]>; | |
223e47cc LB |
717 | |
718 | class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, | |
1a4d82fc JJ |
719 | NoItinerary, DSPROpnd, DSPROpnd>, |
720 | IsCommutable, Defs<[DSPOutFlag21]>; | |
223e47cc | 721 | |
1a4d82fc JJ |
722 | class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph", |
723 | MipsMULSAQ_S_W_PH>, | |
724 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 725 | |
1a4d82fc JJ |
726 | class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>, |
727 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 728 | |
1a4d82fc JJ |
729 | class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>, |
730 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 731 | |
1a4d82fc JJ |
732 | class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>, |
733 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 734 | |
1a4d82fc JJ |
735 | class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>, |
736 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 737 | |
1a4d82fc JJ |
738 | // Move from/to hi/lo. |
739 | class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>; | |
740 | class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>; | |
741 | class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>; | |
742 | class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>; | |
223e47cc | 743 | |
1a4d82fc JJ |
744 | // Dot product with accumulate/subtract |
745 | class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; | |
223e47cc | 746 | |
1a4d82fc | 747 | class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>; |
223e47cc | 748 | |
1a4d82fc | 749 | class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>; |
223e47cc | 750 | |
1a4d82fc | 751 | class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>; |
223e47cc | 752 | |
1a4d82fc JJ |
753 | class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>, |
754 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 755 | |
1a4d82fc JJ |
756 | class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>, |
757 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 758 | |
1a4d82fc JJ |
759 | class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>, |
760 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 761 | |
1a4d82fc JJ |
762 | class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>, |
763 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 764 | |
1a4d82fc JJ |
765 | class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>; |
766 | class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>; | |
767 | class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>; | |
768 | class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>; | |
769 | class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>; | |
770 | class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>; | |
223e47cc LB |
771 | |
772 | // Comparison | |
773 | class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", | |
774 | int_mips_cmpu_eq_qb, NoItinerary, | |
1a4d82fc JJ |
775 | DSPROpnd>, |
776 | IsCommutable, Defs<[DSPCCond]>; | |
223e47cc LB |
777 | |
778 | class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", | |
779 | int_mips_cmpu_lt_qb, NoItinerary, | |
1a4d82fc | 780 | DSPROpnd>, Defs<[DSPCCond]>; |
223e47cc LB |
781 | |
782 | class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", | |
783 | int_mips_cmpu_le_qb, NoItinerary, | |
1a4d82fc | 784 | DSPROpnd>, Defs<[DSPCCond]>; |
223e47cc LB |
785 | |
786 | class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", | |
787 | int_mips_cmpgu_eq_qb, | |
1a4d82fc | 788 | NoItinerary, GPR32Opnd, DSPROpnd>, |
223e47cc LB |
789 | IsCommutable; |
790 | ||
791 | class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", | |
792 | int_mips_cmpgu_lt_qb, | |
1a4d82fc | 793 | NoItinerary, GPR32Opnd, DSPROpnd>; |
223e47cc LB |
794 | |
795 | class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", | |
796 | int_mips_cmpgu_le_qb, | |
1a4d82fc | 797 | NoItinerary, GPR32Opnd, DSPROpnd>; |
223e47cc LB |
798 | |
799 | class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, | |
1a4d82fc JJ |
800 | NoItinerary, DSPROpnd>, |
801 | IsCommutable, Defs<[DSPCCond]>; | |
223e47cc LB |
802 | |
803 | class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, | |
1a4d82fc JJ |
804 | NoItinerary, DSPROpnd>, |
805 | Defs<[DSPCCond]>; | |
223e47cc LB |
806 | |
807 | class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, | |
1a4d82fc JJ |
808 | NoItinerary, DSPROpnd>, |
809 | Defs<[DSPCCond]>; | |
223e47cc LB |
810 | |
811 | // Misc | |
812 | class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, | |
1a4d82fc | 813 | NoItinerary, GPR32Opnd>; |
223e47cc LB |
814 | |
815 | class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, | |
1a4d82fc | 816 | NoItinerary, DSPROpnd, DSPROpnd>; |
223e47cc LB |
817 | |
818 | class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, | |
1a4d82fc | 819 | NoItinerary, DSPROpnd>; |
223e47cc LB |
820 | |
821 | class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, | |
1a4d82fc | 822 | NoItinerary, DSPROpnd>; |
223e47cc LB |
823 | |
824 | class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, | |
1a4d82fc | 825 | NoItinerary, DSPROpnd, GPR32Opnd>; |
223e47cc LB |
826 | |
827 | class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, | |
1a4d82fc | 828 | NoItinerary, DSPROpnd, GPR32Opnd>; |
223e47cc LB |
829 | |
830 | class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, | |
1a4d82fc JJ |
831 | NoItinerary, DSPROpnd, DSPROpnd>, |
832 | Uses<[DSPCCond]>; | |
223e47cc LB |
833 | |
834 | class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, | |
1a4d82fc JJ |
835 | NoItinerary, DSPROpnd, DSPROpnd>, |
836 | Uses<[DSPCCond]>; | |
223e47cc | 837 | |
1a4d82fc | 838 | class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>; |
223e47cc | 839 | |
1a4d82fc | 840 | class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>; |
223e47cc | 841 | |
1a4d82fc | 842 | class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>; |
223e47cc LB |
843 | |
844 | class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; | |
845 | ||
846 | // Extr | |
1a4d82fc JJ |
847 | class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>, |
848 | Uses<[DSPPos]>, Defs<[DSPEFI]>; | |
223e47cc | 849 | |
1a4d82fc JJ |
850 | class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>, |
851 | Uses<[DSPPos]>, Defs<[DSPEFI]>; | |
223e47cc | 852 | |
1a4d82fc JJ |
853 | class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>, |
854 | Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; | |
223e47cc LB |
855 | |
856 | class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, | |
1a4d82fc JJ |
857 | NoItinerary>, |
858 | Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; | |
223e47cc | 859 | |
1a4d82fc JJ |
860 | class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>, |
861 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
862 | |
863 | class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, | |
1a4d82fc | 864 | NoItinerary>, Defs<[DSPOutFlag23]>; |
223e47cc LB |
865 | |
866 | class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, | |
1a4d82fc JJ |
867 | NoItinerary>, |
868 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
869 | |
870 | class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, | |
1a4d82fc JJ |
871 | NoItinerary>, |
872 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
873 | |
874 | class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, | |
1a4d82fc JJ |
875 | NoItinerary>, |
876 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
877 | |
878 | class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, | |
1a4d82fc JJ |
879 | NoItinerary>, |
880 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
881 | |
882 | class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, | |
1a4d82fc JJ |
883 | NoItinerary>, |
884 | Defs<[DSPOutFlag23]>; | |
223e47cc LB |
885 | |
886 | class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, | |
1a4d82fc JJ |
887 | NoItinerary>, |
888 | Defs<[DSPOutFlag23]>; | |
223e47cc | 889 | |
1a4d82fc | 890 | class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>; |
223e47cc | 891 | |
1a4d82fc | 892 | class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>; |
223e47cc | 893 | |
1a4d82fc | 894 | class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>; |
223e47cc LB |
895 | |
896 | class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; | |
897 | ||
898 | class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; | |
899 | ||
1a4d82fc JJ |
900 | class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>, |
901 | Uses<[DSPPos, DSPSCount]>; | |
223e47cc LB |
902 | |
903 | //===----------------------------------------------------------------------===// | |
904 | // MIPS DSP Rev 2 | |
905 | // Addition/subtraction | |
906 | class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, | |
1a4d82fc JJ |
907 | DSPROpnd, DSPROpnd>, IsCommutable, |
908 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
909 | |
910 | class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, | |
1a4d82fc JJ |
911 | NoItinerary, DSPROpnd, DSPROpnd>, |
912 | IsCommutable, Defs<[DSPOutFlag20]>; | |
223e47cc LB |
913 | |
914 | class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, | |
1a4d82fc JJ |
915 | DSPROpnd, DSPROpnd>, |
916 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
917 | |
918 | class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, | |
1a4d82fc JJ |
919 | NoItinerary, DSPROpnd, DSPROpnd>, |
920 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
921 | |
922 | class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, | |
1a4d82fc | 923 | NoItinerary, DSPROpnd>, IsCommutable; |
223e47cc LB |
924 | |
925 | class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, | |
1a4d82fc | 926 | NoItinerary, DSPROpnd>, IsCommutable; |
223e47cc LB |
927 | |
928 | class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, | |
1a4d82fc | 929 | NoItinerary, DSPROpnd>; |
223e47cc LB |
930 | |
931 | class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, | |
1a4d82fc | 932 | NoItinerary, DSPROpnd>; |
223e47cc LB |
933 | |
934 | class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, | |
1a4d82fc | 935 | NoItinerary, DSPROpnd>, IsCommutable; |
223e47cc LB |
936 | |
937 | class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, | |
1a4d82fc | 938 | NoItinerary, DSPROpnd>, IsCommutable; |
223e47cc LB |
939 | |
940 | class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, | |
1a4d82fc | 941 | NoItinerary, DSPROpnd>; |
223e47cc LB |
942 | |
943 | class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, | |
1a4d82fc | 944 | NoItinerary, DSPROpnd>; |
223e47cc LB |
945 | |
946 | class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, | |
1a4d82fc | 947 | NoItinerary, GPR32Opnd>, IsCommutable; |
223e47cc LB |
948 | |
949 | class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, | |
1a4d82fc | 950 | NoItinerary, GPR32Opnd>, IsCommutable; |
223e47cc LB |
951 | |
952 | class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, | |
1a4d82fc | 953 | NoItinerary, GPR32Opnd>; |
223e47cc LB |
954 | |
955 | class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, | |
1a4d82fc | 956 | NoItinerary, GPR32Opnd>; |
223e47cc LB |
957 | |
958 | // Comparison | |
959 | class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", | |
960 | int_mips_cmpgdu_eq_qb, | |
1a4d82fc JJ |
961 | NoItinerary, GPR32Opnd, DSPROpnd>, |
962 | IsCommutable, Defs<[DSPCCond]>; | |
223e47cc LB |
963 | |
964 | class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", | |
965 | int_mips_cmpgdu_lt_qb, | |
1a4d82fc JJ |
966 | NoItinerary, GPR32Opnd, DSPROpnd>, |
967 | Defs<[DSPCCond]>; | |
223e47cc LB |
968 | |
969 | class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", | |
970 | int_mips_cmpgdu_le_qb, | |
1a4d82fc JJ |
971 | NoItinerary, GPR32Opnd, DSPROpnd>, |
972 | Defs<[DSPCCond]>; | |
223e47cc LB |
973 | |
974 | // Absolute | |
975 | class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, | |
1a4d82fc JJ |
976 | NoItinerary, DSPROpnd>, |
977 | Defs<[DSPOutFlag20]>; | |
223e47cc LB |
978 | |
979 | // Multiplication | |
1a4d82fc JJ |
980 | class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary, |
981 | DSPROpnd>, IsCommutable, | |
982 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
983 | |
984 | class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, | |
1a4d82fc JJ |
985 | NoItinerary, DSPROpnd>, IsCommutable, |
986 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
987 | |
988 | class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, | |
1a4d82fc JJ |
989 | NoItinerary, GPR32Opnd>, IsCommutable, |
990 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
991 | |
992 | class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, | |
1a4d82fc JJ |
993 | NoItinerary, GPR32Opnd>, IsCommutable, |
994 | Defs<[DSPOutFlag21]>; | |
223e47cc LB |
995 | |
996 | class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, | |
1a4d82fc JJ |
997 | NoItinerary, DSPROpnd, DSPROpnd>, |
998 | IsCommutable, Defs<[DSPOutFlag21]>; | |
223e47cc LB |
999 | |
1000 | // Dot product with accumulate/subtract | |
1a4d82fc | 1001 | class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>; |
223e47cc | 1002 | |
1a4d82fc | 1003 | class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>; |
223e47cc | 1004 | |
1a4d82fc JJ |
1005 | class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>, |
1006 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 1007 | |
1a4d82fc JJ |
1008 | class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph", |
1009 | MipsDPAQX_SA_W_PH>, | |
1010 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 1011 | |
1a4d82fc | 1012 | class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>; |
223e47cc | 1013 | |
1a4d82fc | 1014 | class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>; |
223e47cc | 1015 | |
1a4d82fc JJ |
1016 | class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>, |
1017 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 1018 | |
1a4d82fc JJ |
1019 | class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph", |
1020 | MipsDPSQX_SA_W_PH>, | |
1021 | Defs<[DSPOutFlag16_19]>; | |
223e47cc | 1022 | |
1a4d82fc | 1023 | class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>; |
223e47cc LB |
1024 | |
1025 | // Precision reduce/expand | |
1026 | class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", | |
1027 | int_mips_precr_qb_ph, | |
1a4d82fc | 1028 | NoItinerary, DSPROpnd, DSPROpnd>; |
223e47cc LB |
1029 | |
1030 | class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", | |
1031 | int_mips_precr_sra_ph_w, | |
1a4d82fc JJ |
1032 | NoItinerary, DSPROpnd, |
1033 | GPR32Opnd>; | |
223e47cc LB |
1034 | |
1035 | class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", | |
1036 | int_mips_precr_sra_r_ph_w, | |
1a4d82fc JJ |
1037 | NoItinerary, DSPROpnd, |
1038 | GPR32Opnd>; | |
223e47cc LB |
1039 | |
1040 | // Shift | |
1a4d82fc JJ |
1041 | class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3, |
1042 | NoItinerary, DSPROpnd>; | |
223e47cc LB |
1043 | |
1044 | class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, | |
1a4d82fc | 1045 | NoItinerary, DSPROpnd>; |
223e47cc LB |
1046 | |
1047 | class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, | |
1a4d82fc | 1048 | immZExt3, NoItinerary, DSPROpnd>; |
223e47cc LB |
1049 | |
1050 | class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, | |
1a4d82fc | 1051 | NoItinerary, DSPROpnd>; |
223e47cc | 1052 | |
1a4d82fc JJ |
1053 | class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4, |
1054 | NoItinerary, DSPROpnd>; | |
223e47cc LB |
1055 | |
1056 | class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, | |
1a4d82fc | 1057 | NoItinerary, DSPROpnd>; |
223e47cc LB |
1058 | |
1059 | // Misc | |
1060 | class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, | |
1a4d82fc | 1061 | NoItinerary>; |
223e47cc LB |
1062 | |
1063 | class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, | |
1a4d82fc | 1064 | NoItinerary>; |
223e47cc LB |
1065 | |
1066 | class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, | |
1a4d82fc | 1067 | NoItinerary>; |
223e47cc LB |
1068 | |
1069 | // Pseudos. | |
1a4d82fc JJ |
1070 | def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, |
1071 | NoItinerary>, Uses<[DSPPos]>; | |
223e47cc LB |
1072 | |
1073 | // Instruction defs. | |
1074 | // MIPS DSP Rev 1 | |
1075 | def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; | |
1076 | def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; | |
1077 | def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; | |
1078 | def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; | |
1079 | def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; | |
1080 | def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; | |
1081 | def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; | |
1082 | def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; | |
1083 | def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; | |
1084 | def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; | |
1085 | def ADDSC : ADDSC_ENC, ADDSC_DESC; | |
1086 | def ADDWC : ADDWC_ENC, ADDWC_DESC; | |
1087 | def MODSUB : MODSUB_ENC, MODSUB_DESC; | |
1088 | def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; | |
1089 | def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; | |
1090 | def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC; | |
1091 | def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; | |
1092 | def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; | |
1093 | def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; | |
1094 | def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; | |
1095 | def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; | |
1096 | def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; | |
1097 | def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; | |
1098 | def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; | |
1099 | def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; | |
1100 | def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; | |
1101 | def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; | |
1102 | def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; | |
1103 | def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; | |
1104 | def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; | |
1105 | def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC; | |
1106 | def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC; | |
1107 | def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC; | |
1108 | def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC; | |
1109 | def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC; | |
1110 | def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC; | |
1111 | def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC; | |
1112 | def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; | |
1113 | def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC; | |
1114 | def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC; | |
1115 | def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC; | |
1116 | def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; | |
1117 | def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC; | |
1118 | def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC; | |
1119 | def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; | |
1120 | def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; | |
1121 | def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; | |
1122 | def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; | |
1123 | def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; | |
1124 | def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; | |
1125 | def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; | |
1126 | def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; | |
1127 | def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; | |
1128 | def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; | |
1129 | def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; | |
1130 | def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; | |
1a4d82fc JJ |
1131 | def MFHI_DSP : MFHI_ENC, MFHI_DESC; |
1132 | def MFLO_DSP : MFLO_ENC, MFLO_DESC; | |
1133 | def MTHI_DSP : MTHI_ENC, MTHI_DESC; | |
1134 | def MTLO_DSP : MTLO_ENC, MTLO_DESC; | |
223e47cc LB |
1135 | def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; |
1136 | def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; | |
1137 | def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; | |
1138 | def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; | |
1139 | def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; | |
1140 | def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; | |
1141 | def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; | |
1142 | def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; | |
1143 | def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; | |
1144 | def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; | |
1145 | def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; | |
1146 | def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; | |
1147 | def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; | |
1148 | def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; | |
1149 | def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; | |
1150 | def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; | |
1151 | def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; | |
1152 | def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; | |
1153 | def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; | |
1154 | def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; | |
1155 | def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; | |
1156 | def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; | |
1157 | def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; | |
1158 | def BITREV : BITREV_ENC, BITREV_DESC; | |
1159 | def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; | |
1160 | def REPL_QB : REPL_QB_ENC, REPL_QB_DESC; | |
1161 | def REPL_PH : REPL_PH_ENC, REPL_PH_DESC; | |
1162 | def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; | |
1163 | def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; | |
1164 | def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; | |
1165 | def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; | |
1166 | def LWX : LWX_ENC, LWX_DESC; | |
1167 | def LHX : LHX_ENC, LHX_DESC; | |
1168 | def LBUX : LBUX_ENC, LBUX_DESC; | |
1169 | def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; | |
1170 | def INSV : INSV_ENC, INSV_DESC; | |
1171 | def EXTP : EXTP_ENC, EXTP_DESC; | |
1172 | def EXTPV : EXTPV_ENC, EXTPV_DESC; | |
1173 | def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; | |
1174 | def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; | |
1175 | def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; | |
1176 | def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; | |
1177 | def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; | |
1178 | def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; | |
1179 | def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; | |
1180 | def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; | |
1181 | def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; | |
1182 | def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; | |
1183 | def SHILO : SHILO_ENC, SHILO_DESC; | |
1184 | def SHILOV : SHILOV_ENC, SHILOV_DESC; | |
1185 | def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; | |
1186 | def RDDSP : RDDSP_ENC, RDDSP_DESC; | |
1187 | def WRDSP : WRDSP_ENC, WRDSP_DESC; | |
1188 | ||
1189 | // MIPS DSP Rev 2 | |
1190 | let Predicates = [HasDSPR2] in { | |
1191 | ||
1192 | def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; | |
1193 | def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; | |
1194 | def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; | |
1195 | def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; | |
1196 | def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; | |
1197 | def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; | |
1198 | def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; | |
1199 | def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; | |
1200 | def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC; | |
1201 | def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; | |
1202 | def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; | |
1203 | def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; | |
1204 | def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC; | |
1205 | def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; | |
1206 | def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; | |
1207 | def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; | |
1208 | def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC; | |
1209 | def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC; | |
1210 | def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; | |
1211 | def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; | |
1212 | def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; | |
1213 | def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; | |
1214 | def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; | |
1215 | def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; | |
1216 | def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; | |
1217 | def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; | |
1218 | def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; | |
1219 | def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; | |
1220 | def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; | |
1221 | def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; | |
1222 | def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; | |
1223 | def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; | |
1224 | def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; | |
1225 | def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; | |
1226 | def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; | |
1227 | def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; | |
1228 | def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; | |
1229 | def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC; | |
1230 | def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC; | |
1231 | def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC; | |
1232 | def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; | |
1233 | def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC; | |
1234 | def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC; | |
1235 | def APPEND : APPEND_ENC, APPEND_DESC; | |
1236 | def BALIGN : BALIGN_ENC, BALIGN_DESC; | |
1237 | def PREPEND : PREPEND_ENC, PREPEND_DESC; | |
1238 | ||
1239 | } | |
1240 | ||
1241 | // Pseudos. | |
1a4d82fc JJ |
1242 | let isPseudo = 1, isCodeGenOnly = 1 in { |
1243 | // Pseudo instructions for loading and storing accumulator registers. | |
1244 | def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>; | |
1245 | def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>; | |
1246 | ||
1247 | // Pseudos for loading and storing ccond field of DSP control register. | |
1248 | def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>; | |
1249 | def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>; | |
1250 | } | |
223e47cc | 1251 | |
1a4d82fc JJ |
1252 | // Pseudo CMP and PICK instructions. |
1253 | class PseudoCMP<Instruction RealInst> : | |
1254 | PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>, | |
1255 | PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects; | |
223e47cc | 1256 | |
1a4d82fc JJ |
1257 | class PseudoPICK<Instruction RealInst> : |
1258 | PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>, | |
1259 | PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>, | |
1260 | NeverHasSideEffects; | |
223e47cc | 1261 | |
1a4d82fc JJ |
1262 | def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>; |
1263 | def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>; | |
1264 | def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>; | |
1265 | def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>; | |
1266 | def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>; | |
1267 | def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>; | |
1268 | ||
1269 | def PseudoPICK_PH : PseudoPICK<PICK_PH>; | |
1270 | def PseudoPICK_QB : PseudoPICK<PICK_QB>; | |
1271 | ||
1272 | def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>; | |
223e47cc LB |
1273 | |
1274 | // Patterns. | |
1275 | class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : | |
1276 | Pat<pattern, result>, Requires<[pred]>; | |
1277 | ||
1278 | class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, | |
1279 | RegisterClass SrcRC> : | |
1280 | DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), | |
1281 | (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; | |
1282 | ||
1a4d82fc JJ |
1283 | def : BitconvertPat<i32, v2i16, GPR32, DSPR>; |
1284 | def : BitconvertPat<i32, v4i8, GPR32, DSPR>; | |
1285 | def : BitconvertPat<v2i16, i32, DSPR, GPR32>; | |
1286 | def : BitconvertPat<v4i8, i32, DSPR, GPR32>; | |
223e47cc LB |
1287 | |
1288 | def : DSPPat<(v2i16 (load addr:$a)), | |
1a4d82fc | 1289 | (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>; |
223e47cc | 1290 | def : DSPPat<(v4i8 (load addr:$a)), |
1a4d82fc JJ |
1291 | (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>; |
1292 | def : DSPPat<(store (v2i16 DSPR:$val), addr:$a), | |
1293 | (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>; | |
1294 | def : DSPPat<(store (v4i8 DSPR:$val), addr:$a), | |
1295 | (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>; | |
1296 | ||
1297 | // Binary operations. | |
1298 | class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, | |
1299 | Predicate Pred = HasDSP> : | |
1300 | DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>; | |
1301 | ||
1302 | def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>; | |
1303 | def : DSPBinPat<ADDQ_PH, v2i16, add>; | |
1304 | def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>; | |
1305 | def : DSPBinPat<SUBQ_PH, v2i16, sub>; | |
1306 | def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>; | |
1307 | def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>; | |
1308 | def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>; | |
1309 | def : DSPBinPat<ADDU_QB, v4i8, add>; | |
1310 | def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>; | |
1311 | def : DSPBinPat<SUBU_QB, v4i8, sub>; | |
1312 | def : DSPBinPat<ADDSC, i32, int_mips_addsc>; | |
1313 | def : DSPBinPat<ADDSC, i32, addc>; | |
1314 | def : DSPBinPat<ADDWC, i32, int_mips_addwc>; | |
1315 | def : DSPBinPat<ADDWC, i32, adde>; | |
1316 | ||
1317 | // Shift immediate patterns. | |
1318 | class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, | |
1319 | SDPatternOperator Imm, Predicate Pred = HasDSP> : | |
1320 | DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>; | |
1321 | ||
1322 | def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>; | |
1323 | def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>; | |
1324 | def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>; | |
1325 | def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>; | |
1326 | def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>; | |
1327 | def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>; | |
1328 | def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>; | |
1329 | def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>; | |
1330 | def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>; | |
1331 | def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>; | |
1332 | def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>; | |
1333 | def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>; | |
1334 | ||
1335 | // SETCC/SELECT_CC patterns. | |
1336 | class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, | |
1337 | CondCode CC> : | |
1338 | DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), | |
1339 | (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), | |
1340 | (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)), | |
1341 | (ValTy ZERO)))>; | |
1342 | ||
1343 | class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, | |
1344 | CondCode CC> : | |
1345 | DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), | |
1346 | (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), | |
1347 | (ValTy ZERO), | |
1348 | (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>; | |
1349 | ||
1350 | class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, | |
1351 | CondCode CC> : | |
1352 | DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), | |
1353 | (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>; | |
1354 | ||
1355 | class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, | |
1356 | CondCode CC> : | |
1357 | DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), | |
1358 | (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>; | |
1359 | ||
1360 | def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; | |
1361 | def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; | |
1362 | def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; | |
1363 | def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; | |
1364 | def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; | |
1365 | def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; | |
1366 | def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; | |
1367 | def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; | |
1368 | def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; | |
1369 | def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; | |
1370 | def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; | |
1371 | def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; | |
1372 | ||
1373 | def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; | |
1374 | def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; | |
1375 | def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; | |
1376 | def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; | |
1377 | def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; | |
1378 | def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; | |
1379 | def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; | |
1380 | def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; | |
1381 | def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; | |
1382 | def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; | |
1383 | def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; | |
1384 | def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; | |
223e47cc LB |
1385 | |
1386 | // Extr patterns. | |
1387 | class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : | |
1a4d82fc JJ |
1388 | DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)), |
1389 | (Instr ACC64DSP:$ac, GPR32:$rs)>; | |
223e47cc LB |
1390 | |
1391 | class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : | |
1a4d82fc JJ |
1392 | DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)), |
1393 | (Instr ACC64DSP:$ac, immZExt5:$shift)>; | |
223e47cc LB |
1394 | |
1395 | def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; | |
1396 | def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; | |
1397 | def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; | |
1398 | def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; | |
1399 | def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; | |
1400 | def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; | |
1401 | def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; | |
1402 | def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; | |
1403 | def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; | |
1404 | def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; | |
1405 | def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; | |
1406 | def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; | |
1a4d82fc JJ |
1407 | |
1408 | // Indexed load patterns. | |
1409 | class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> : | |
1410 | DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))), | |
1411 | (Instr i32:$base, i32:$index)>; | |
1412 | ||
1413 | let AddedComplexity = 20 in { | |
1414 | def : IndexedLoadPat<zextloadi8, LBUX>; | |
1415 | def : IndexedLoadPat<sextloadi16, LHX>; | |
1416 | def : IndexedLoadPat<load, LWX>; | |
1417 | } |