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Imported Upstream version 1.0.0+dfsg1
[rustc.git] / src / llvm / lib / Target / Mips / MipsInstrFPU.td
CommitLineData
223e47cc
LB		 1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Mips FPU instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Floating Point Instructions
16// ------------------------
17// * 64bit fp:
18// - 32 64-bit registers (default mode)
19// - 16 even 32-bit registers (32-bit compatible mode) for
20// single and double access.
21// * 32bit fp:
22// - 16 even 32-bit registers - single and double (aliased)
23// - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
26// Floating Point Compare and Branch
1a4d82fc
JJ		 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
28 SDTCisVT<1, i32>,
29 SDTCisVT<2, OtherVT>]>;
223e47cc
LB		 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 SDTCisVT<2, i32>]>;
1a4d82fc
JJ		 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
33 SDTCisSameAs<1, 3>]>;
34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
223e47cc
LB		 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 SDTCisVT<1, i32>,
37 SDTCisSameAs<1, 2>]>;
38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
39 SDTCisVT<1, f64>,
40 SDTCisVT<2, i32>]>;
41
42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
1a4d82fc 47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
223e47cc
LB		 48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
51
52// Operand for printing out a condition code.
53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
55
56//===----------------------------------------------------------------------===//
57// Feature predicates.
58//===----------------------------------------------------------------------===//
59
1a4d82fc 60def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
223e47cc 61 AssemblerPredicate<"FeatureFP64Bit">;
1a4d82fc 62def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
223e47cc 63 AssemblerPredicate<"!FeatureFP64Bit">;
1a4d82fc 64def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
223e47cc 65 AssemblerPredicate<"FeatureSingleFloat">;
1a4d82fc 66def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
223e47cc
LB		 67 AssemblerPredicate<"!FeatureSingleFloat">;
68
1a4d82fc
JJ		 69//===----------------------------------------------------------------------===//
70// Mips FGR size adjectives.
71// They are mutually exclusive.
72//===----------------------------------------------------------------------===//
73
74class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
75class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
76
77//===----------------------------------------------------------------------===//
78
223e47cc
LB		 79// FP immediate patterns.
80def fpimm0 : PatLeaf<(fpimm), [{
81 return N->isExactlyValue(+0.0);
82}]>;
83
84def fpimm0neg : PatLeaf<(fpimm), [{
85 return N->isExactlyValue(-0.0);
86}]>;
87
88//===----------------------------------------------------------------------===//
89// Instruction Class Templates
90//
91// A set of multiclasses is used to address the register usage.
92//
93// S32 - single precision in 16 32bit even fp registers
94// single precision in 32 32bit fp registers in SingleOnly mode
95// S64 - single precision in 32 64bit fp registers (In64BitMode)
96// D32 - double precision in 16 32bit even fp registers
97// D64 - double precision in 32 64bit fp registers (In64BitMode)
98//
99// Only S32 and D32 are supported right now.
100//===----------------------------------------------------------------------===//
101
1a4d82fc 102class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
970d7e83
LB		 103 SDPatternOperator OpNode= null_frag> :
104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
105 !strconcat(opstr, "\t$fd, $fs, $ft"),
1a4d82fc 106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
970d7e83
LB		 107 let isCommutable = IsComm;
108}
109
110multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
111 SDPatternOperator OpNode = null_frag> {
1a4d82fc
JJ		 112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
113 AdditionalRequires<[NotFP64bit]>;
114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
115 IsComm, OpNode>,
116 AdditionalRequires<[IsFP64bit]> {
970d7e83 117 string DecoderNamespace = "Mips64";
223e47cc
LB		 118 }
119}
120
1a4d82fc 121class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
970d7e83
LB		 122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
1a4d82fc 124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
970d7e83 125 NeverHasSideEffects;
223e47cc 126
970d7e83
LB		 127multiclass ABSS_M<string opstr, InstrItinClass Itin,
128 SDPatternOperator OpNode= null_frag> {
1a4d82fc
JJ		 129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
130 AdditionalRequires<[NotFP64bit]>;
131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
132 AdditionalRequires<[IsFP64bit]> {
970d7e83 133 string DecoderNamespace = "Mips64";
223e47cc
LB		 134 }
135}
136
970d7e83 137multiclass ROUND_M<string opstr, InstrItinClass Itin> {
1a4d82fc
JJ		 138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
139 AdditionalRequires<[NotFP64bit]>;
140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
141 AdditionalRequires<[IsFP64bit]> {
223e47cc
LB		 142 let DecoderNamespace = "Mips64";
143 }
144}
223e47cc 145
1a4d82fc 146class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
970d7e83
LB		 147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
1a4d82fc 149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
970d7e83 150
1a4d82fc 151class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
970d7e83
LB		 152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
1a4d82fc 154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
970d7e83 155
1a4d82fc
JJ		 156class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
157 InstrItinClass Itin> :
158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> {
160 // $fs_in is part of a white lie to work around a widespread bug in the FPU
161 // implementation. See expandBuildPairF64 for details.
162 let Constraints = "$fs = $fs_in";
163}
970d7e83 164
1a4d82fc
JJ		 165class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
166 SDPatternOperator OpNode= null_frag> :
167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
970d7e83 169 let DecoderMethod = "DecodeFMem";
1a4d82fc 170 let mayLoad = 1;
970d7e83
LB		 171}
172
1a4d82fc
JJ		 173class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
174 SDPatternOperator OpNode= null_frag> :
175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
970d7e83 177 let DecoderMethod = "DecodeFMem";
1a4d82fc
JJ		 178 let mayStore = 1;
179}
180
1a4d82fc 181class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
970d7e83
LB		 182 SDPatternOperator OpNode = null_frag> :
183 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
184 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
1a4d82fc
JJ		 185 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
186 FrmFR, opstr>;
970d7e83 187
1a4d82fc 188class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
970d7e83
LB		 189 SDPatternOperator OpNode = null_frag> :
190 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
191 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
192 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
1a4d82fc 193 Itin, FrmFR, opstr>;
970d7e83 194
1a4d82fc 195class LWXC1_FT<string opstr, RegisterOperand DRC,
970d7e83 196 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
1a4d82fc 197 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
970d7e83 198 !strconcat(opstr, "\t$fd, ${index}(${base})"),
1a4d82fc
JJ		 199 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
200 FrmFI, opstr> {
970d7e83
LB		 201 let AddedComplexity = 20;
202}
203
1a4d82fc 204class SWXC1_FT<string opstr, RegisterOperand DRC,
970d7e83 205 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
1a4d82fc 206 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
970d7e83 207 !strconcat(opstr, "\t$fs, ${index}(${base})"),
1a4d82fc
JJ		 208 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
209 FrmFI, opstr> {
970d7e83
LB		 210 let AddedComplexity = 20;
211}
212
1a4d82fc 213class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
85aaf69f 214 SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
1a4d82fc
JJ		 215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
216 !strconcat(opstr, "\t$fcc, $offset"),
217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
218 FrmFI, opstr> {
970d7e83
LB		 219 let isBranch = 1;
220 let isTerminator = 1;
85aaf69f 221 let hasDelaySlot = DelaySlot;
970d7e83 222 let Defs = [AT];
970d7e83
LB		 223}
224
225class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
226 SDPatternOperator OpNode = null_frag> :
227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
1a4d82fc
JJ		 229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
230 !strconcat("c.$cond.", typestr)> {
231 let Defs = [FCC0];
232 let isCodeGenOnly = 1;
233}
234
235class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
236 InstrItinClass itin> :
237 InstSE<(outs), (ins RC:$fs, RC:$ft),
238 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
239 FrmFR>;
240
241multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
242 InstrItinClass itin> {
243 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
244 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
245 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
246 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
247 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
248 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
249 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
250 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
251 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
252 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
253 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
254 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
255 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
256 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
257 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
258 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
259}
260
261defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
262defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
263 AdditionalRequires<[NotFP64bit]>;
264let DecoderNamespace = "Mips64" in
265defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
266 AdditionalRequires<[IsFP64bit]>;
223e47cc
LB		 267
268//===----------------------------------------------------------------------===//
269// Floating Point Instructions
270//===----------------------------------------------------------------------===//
1a4d82fc
JJ		 271def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
272 ABSS_FM<0xc, 16>, ISA_MIPS2;
273def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
274 ABSS_FM<0xd, 16>, ISA_MIPS2;
275def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
276 ABSS_FM<0xe, 16>, ISA_MIPS2;
277def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
278 ABSS_FM<0xf, 16>, ISA_MIPS2;
279def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
280 ABSS_FM<0x24, 16>;
281
282defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
283defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
284defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
285defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
286defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
287
288let DecoderNamespace = "Mips64" in {
289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
290 ABSS_FM<0x8, 16>, FGR_64;
291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
292 ABSS_FM<0x8, 17>, FGR_64;
293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
294 ABSS_FM<0x9, 16>, FGR_64;
295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
296 ABSS_FM<0x9, 17>, FGR_64;
297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
298 ABSS_FM<0xa, 16>, FGR_64;
299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
300 ABSS_FM<0xa, 17>, FGR_64;
301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
302 ABSS_FM<0xb, 16>, FGR_64;
303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
304 ABSS_FM<0xb, 17>, FGR_64;
305}
306
307def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
308 ABSS_FM<0x20, 20>;
309def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
310 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
311def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
312 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
313
314def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
315 ABSS_FM<0x20, 17>, FGR_32;
316def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
317 ABSS_FM<0x21, 20>, FGR_32;
318def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
319 ABSS_FM<0x21, 16>, FGR_32;
320
321let DecoderNamespace = "Mips64" in {
322 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
323 ABSS_FM<0x20, 17>, FGR_64;
324 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
325 ABSS_FM<0x20, 21>, FGR_64;
326 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
327 ABSS_FM<0x21, 20>, FGR_64;
328 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
329 ABSS_FM<0x21, 16>, FGR_64;
330 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
331 ABSS_FM<0x21, 21>, FGR_64;
332}
333
334let isPseudo = 1, isCodeGenOnly = 1 in {
335 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
336 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
337 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
338 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
339 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
340}
341
342def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
343 ABSS_FM<0x5, 16>;
344def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
345 ABSS_FM<0x7, 16>;
346defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
347defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
348
349def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
350 ABSS_FM<0x4, 16>, ISA_MIPS2;
351defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
223e47cc
LB		 352
353// The odd-numbered registers are only referenced when doing loads,
354// stores, and moves between floating-point and integer registers.
355// When defining instructions, we reference all 32-bit registers,
356// regardless of register aliasing.
357
223e47cc 358/// Move Control Registers From/To CPU Registers
1a4d82fc
JJ		 359def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
360def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
361def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
362 bitconvert>, MFC1_FM<0>;
363def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
364 bitconvert>, MFC1_FM<4>;
365def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
366 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
367def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
368 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
223e47cc
LB		 369 let DecoderNamespace = "Mips64";
370}
1a4d82fc
JJ		 371def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
372 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
373def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
374 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
375 let DecoderNamespace = "Mips64";
223e47cc 376}
1a4d82fc
JJ		 377def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
378 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
379def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
380 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
223e47cc 381
1a4d82fc
JJ		 382def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
383 ABSS_FM<0x6, 16>;
384def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
385 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>;
386def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
387 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> {
388 let DecoderNamespace = "Mips64";
223e47cc
LB		 389}
390
1a4d82fc
JJ		 391/// Floating Point Memory Instructions
392def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
393def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
394
395let DecoderNamespace = "Mips64" in {
396 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
397 FGR_64;
398 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
399 FGR_64;
400}
401
402def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
403 ISA_MIPS2, FGR_32;
404def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
405 ISA_MIPS2, FGR_32;
406
223e47cc 407// Indexed loads and stores.
1a4d82fc
JJ		 408// Base register + offset register addressing mode (indicated by "x" in the
409// instruction mnemonic) is disallowed under NaCl.
410let AdditionalPredicates = [IsNotNaCl] in {
411 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
412 INSN_MIPS4_32R2_NOT_32R6_64R6;
413 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
414 INSN_MIPS4_32R2_NOT_32R6_64R6;
223e47cc
LB		 415}
416
1a4d82fc
JJ		 417let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
418 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
419 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
420 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
421 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
223e47cc
LB		 422}
423
1a4d82fc
JJ		 424let DecoderNamespace="Mips64" in {
425 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
426 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
427 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
428 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
223e47cc
LB		 429}
430
431// Load/store doubleword indexed unaligned.
1a4d82fc
JJ		 432let AdditionalPredicates = [IsNotNaCl] in {
433 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
434 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
435 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
436 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
223e47cc
LB		 437}
438
1a4d82fc
JJ		 439let DecoderNamespace="Mips64" in {
440 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
441 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
442 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
443 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
223e47cc
LB		 444}
445
446/// Floating-point Aritmetic
1a4d82fc
JJ		 447def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
448 ADDS_FM<0x00, 16>;
449defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
450def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
451 ADDS_FM<0x03, 16>;
452defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
453def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
454 ADDS_FM<0x02, 16>;
455defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
456def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
457 ADDS_FM<0x01, 16>;
458defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
459
460def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
461 MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
462def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
463 MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
464
465let AdditionalPredicates = [NoNaNsFPMath] in {
466 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
467 MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
468 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
469 MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
470}
471
472def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
473 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
474def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
475 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
476
477let AdditionalPredicates = [NoNaNsFPMath] in {
478 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
479 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
480 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
481 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
482}
483
484let isCodeGenOnly=1 in {
485 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
486 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
487 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
488 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
489}
490
491let AdditionalPredicates = [NoNaNsFPMath],
223e47cc 492 isCodeGenOnly=1 in {
1a4d82fc
JJ		 493 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
494 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
495 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
496 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
223e47cc
LB		 497}
498
499//===----------------------------------------------------------------------===//
500// Floating Point Branch Codes
501//===----------------------------------------------------------------------===//
502// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
503// They must be kept in synch.
504def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
505def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
506
1a4d82fc
JJ		 507def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
508 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
85aaf69f
SL		 509def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
510 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
1a4d82fc
JJ		 511def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
512 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
85aaf69f
SL		 513def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
514 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
1a4d82fc 515
223e47cc
LB		 516//===----------------------------------------------------------------------===//
517// Floating Point Flag Conditions
518//===----------------------------------------------------------------------===//
519// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
520// They must be kept in synch.
521def MIPS_FCOND_F : PatLeaf<(i32 0)>;
522def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
523def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
524def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
525def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
526def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
527def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
528def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
529def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
530def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
531def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
532def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
533def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
534def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
535def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
536def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
537
223e47cc 538/// Floating Point Compare
1a4d82fc
JJ		 539def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
540 ISA_MIPS1_NOT_32R6_64R6;
541def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
542 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>;
970d7e83 543let DecoderNamespace = "Mips64" in
1a4d82fc
JJ		 544def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
545 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>;
223e47cc
LB		 546
547//===----------------------------------------------------------------------===//
548// Floating Point Pseudo-Instructions
549//===----------------------------------------------------------------------===//
223e47cc
LB		 550
551// This pseudo instr gets expanded into 2 mtc1 instrs after register
552// allocation.
1a4d82fc
JJ		 553class BuildPairF64Base<RegisterOperand RO> :
554 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
555 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
556
557def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
558 AdditionalRequires<[NotFP64bit]>;
559def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
560 AdditionalRequires<[IsFP64bit]>;
223e47cc
LB		 561
562// This pseudo instr gets expanded into 2 mfc1 instrs after register
563// allocation.
564// if n is 0, lower part of src is extracted.
565// if n is 1, higher part of src is extracted.
1a4d82fc
JJ		 566class ExtractElementF64Base<RegisterOperand RO> :
567 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
568 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
569
570def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
571 AdditionalRequires<[NotFP64bit]>;
572def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
573 AdditionalRequires<[IsFP64bit]>;
574
575//===----------------------------------------------------------------------===//
576// InstAliases.
577//===----------------------------------------------------------------------===//
578def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
579 ISA_MIPS1_NOT_32R6_64R6;
85aaf69f
SL		 580def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
581 ISA_MIPS2_NOT_32R6_64R6;
1a4d82fc
JJ		 582def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
583 ISA_MIPS1_NOT_32R6_64R6;
85aaf69f
SL		 584def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
585 ISA_MIPS2_NOT_32R6_64R6;
223e47cc
LB		 586
587//===----------------------------------------------------------------------===//
588// Floating Point Patterns
589//===----------------------------------------------------------------------===//
590def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
591def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
592
1a4d82fc
JJ		 593def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
594 (PseudoCVT_S_W GPR32Opnd:$src)>;
595def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
596 (TRUNC_W_S FGR32Opnd:$src)>;
597
598def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
599 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
600def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
601 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
602def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
603 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
604def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
605 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
606
607def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
608def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
609
610def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
611 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
612def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
613 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
614def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
615 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
616
617def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
618 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
619def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
620 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
621def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
622 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
623
624def : MipsPat<(f32 (fround FGR64Opnd:$src)),
625 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
626def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
627 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
628
629// Patterns for loads/stores with a reg+imm operand.
970d7e83 630let AddedComplexity = 40 in {
1a4d82fc
JJ		 631 def : LoadRegImmPat<LWC1, f32, load>;
632 def : StoreRegImmPat<SWC1, f32>;
970d7e83 633
1a4d82fc
JJ		 634 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
635 def : StoreRegImmPat<SDC164, f64>, FGR_64;
970d7e83 636
1a4d82fc
JJ		 637 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
638 def : StoreRegImmPat<SDC1, f64>, FGR_32;
970d7e83 639}
backport for Debian buster