]> git.proxmox.com Git - rustc.git/blame - src/llvm/lib/Target/Mips/MipsRegisterInfo.td
projects / rustc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Imported Upstream version 1.0.0+dfsg1
[rustc.git] / src / llvm / lib / Target / Mips / MipsRegisterInfo.td
CommitLineData
223e47cc
LB		 1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Declarations that describe the MIPS register file
12//===----------------------------------------------------------------------===//
13let Namespace = "Mips" in {
1a4d82fc
JJ		 14def sub_32 : SubRegIndex<32>;
15def sub_64 : SubRegIndex<64>;
16def sub_lo : SubRegIndex<32>;
17def sub_hi : SubRegIndex<32, 32>;
18def sub_dsp16_19 : SubRegIndex<4, 16>;
19def sub_dsp20 : SubRegIndex<1, 20>;
20def sub_dsp21 : SubRegIndex<1, 21>;
21def sub_dsp22 : SubRegIndex<1, 22>;
22def sub_dsp23 : SubRegIndex<1, 23>;
223e47cc
LB		 23}
24
970d7e83
LB		 25class Unallocatable {
26 bit isAllocatable = 0;
27}
28
223e47cc 29// We have banks of 32 registers each.
970d7e83
LB		 30class MipsReg<bits<16> Enc, string n> : Register<n> {
31 let HWEncoding = Enc;
223e47cc
LB		 32 let Namespace = "Mips";
33}
34
970d7e83 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
223e47cc 36 : RegisterWithSubRegs<n, subregs> {
970d7e83 37 let HWEncoding = Enc;
223e47cc
LB		 38 let Namespace = "Mips";
39}
40
41// Mips CPU Registers
970d7e83 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
223e47cc
LB		 43
44// Mips 64-bit CPU Registers
970d7e83
LB		 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
46 : MipsRegWithSubRegs<Enc, n, subregs> {
223e47cc
LB		 47 let SubRegIndices = [sub_32];
48}
49
50// Mips 32-bit FPU Registers
970d7e83 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
223e47cc
LB		 52
53// Mips 64-bit (aliased) FPU Registers
970d7e83
LB		 54class AFPR<bits<16> Enc, string n, list<Register> subregs>
55 : MipsRegWithSubRegs<Enc, n, subregs> {
1a4d82fc 56 let SubRegIndices = [sub_lo, sub_hi];
223e47cc
LB		 57 let CoveredBySubRegs = 1;
58}
59
970d7e83
LB		 60class AFPR64<bits<16> Enc, string n, list<Register> subregs>
61 : MipsRegWithSubRegs<Enc, n, subregs> {
1a4d82fc
JJ		 62 let SubRegIndices = [sub_lo, sub_hi];
63 let CoveredBySubRegs = 1;
64}
65
66// Mips 128-bit (aliased) MSA Registers
67class AFPR128<bits<16> Enc, string n, list<Register> subregs>
68 : MipsRegWithSubRegs<Enc, n, subregs> {
69 let SubRegIndices = [sub_64];
70}
71
72// Accumulator Registers
73class ACCReg<bits<16> Enc, string n, list<Register> subregs>
74 : MipsRegWithSubRegs<Enc, n, subregs> {
75 let SubRegIndices = [sub_lo, sub_hi];
76 let CoveredBySubRegs = 1;
223e47cc
LB		 77}
78
79// Mips Hardware Registers
970d7e83 80class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
223e47cc
LB		 81
82//===----------------------------------------------------------------------===//
83// Registers
84//===----------------------------------------------------------------------===//
85
86let Namespace = "Mips" in {
87 // General Purpose Registers
88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
970d7e83 89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
223e47cc
LB		 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
120
121 // General Purpose 64-bit Registers
122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
970d7e83 123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
223e47cc
LB		 124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
154
155 /// Mips Single point precision FPU Registers
1a4d82fc
JJ		 156 foreach I = 0-31 in
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
158
159 // Higher half of 64-bit FP registers.
160 foreach I = 0-31 in
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
223e47cc
LB		 162
163 /// Mips Double point precision FPU Registers (aliased
164 /// with the single precision to hold 64 bit values)
1a4d82fc
JJ		 165 foreach I = 0-15 in
166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
223e47cc
LB		 169
170 /// Mips Double point precision FPU Registers in MFP64 mode.
1a4d82fc
JJ		 171 foreach I = 0-31 in
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
173 DwarfRegNum<[!add(I, 32)]>;
174
175 /// Mips MSA registers
176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
177 foreach I = 0-31 in
178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
179 DwarfRegNum<[!add(I, 32)]>;
223e47cc
LB		 180
181 // Hi/Lo registers
1a4d82fc
JJ		 182 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
183 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
184 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
185 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
186 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
187 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
188 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
189 def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>;
223e47cc
LB		 190
191 let SubRegIndices = [sub_32] in {
1a4d82fc
JJ		 192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;
193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;
223e47cc
LB		 194 }
195
1a4d82fc
JJ		 196 // FP control registers.
197 foreach I = 0-31 in
198 def FCR#I : MipsReg<#I, ""#I>;
223e47cc 199
1a4d82fc
JJ		 200 // FP condition code registers.
201 foreach I = 0-7 in
202 def FCC#I : MipsReg<#I, "fcc"#I>;
203
204 // COP2 registers.
205 foreach I = 0-31 in
206 def COP2#I : MipsReg<#I, ""#I>;
207
208 // COP3 registers.
209 foreach I = 0-31 in
210 def COP3#I : MipsReg<#I, ""#I>;
223e47cc
LB		 211
212 // PC register
213 def PC : Register<"pc">;
214
85aaf69f
SL		 215 // Hardware registers
216 def HWR0 : MipsReg<0, "hwr_cpunum">;
217 def HWR1 : MipsReg<1, "hwr_synci_step">;
218 def HWR2 : MipsReg<2, "hwr_cc">;
219 def HWR3 : MipsReg<3, "hwr_ccres">;
220
221 foreach I = 4-31 in
1a4d82fc 222 def HWR#I : MipsReg<#I, ""#I>;
223e47cc
LB		 223
224 // Accum registers
1a4d82fc
JJ		 225 foreach I = 0-3 in
226 def AC#I : ACCReg<#I, "ac"#I,
227 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
228
229 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
230
231 // DSP-ASE control register fields.
232 def DSPPos : Register<"">;
233 def DSPSCount : Register<"">;
234 def DSPCarry : Register<"">;
235 def DSPEFI : Register<"">;
236 def DSPOutFlag16_19 : Register<"">;
237 def DSPOutFlag20 : Register<"">;
238 def DSPOutFlag21 : Register<"">;
239 def DSPOutFlag22 : Register<"">;
240 def DSPOutFlag23 : Register<"">;
241 def DSPCCond : Register<"">;
242
243 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
244 sub_dsp23] in
245 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
246 DSPOutFlag21, DSPOutFlag22,
247 DSPOutFlag23]>;
248
249 // MSA-ASE control registers.
250 def MSAIR : MipsReg<0, "0">;
251 def MSACSR : MipsReg<1, "1">;
252 def MSAAccess : MipsReg<2, "2">;
253 def MSASave : MipsReg<3, "3">;
254 def MSAModify : MipsReg<4, "4">;
255 def MSARequest : MipsReg<5, "5">;
256 def MSAMap : MipsReg<6, "6">;
257 def MSAUnmap : MipsReg<7, "7">;
258
259 // Octeon multiplier and product registers
260 def MPL0 : MipsReg<0, "mpl0">;
261 def MPL1 : MipsReg<1, "mpl1">;
262 def MPL2 : MipsReg<2, "mpl2">;
263 def P0 : MipsReg<0, "p0">;
264 def P1 : MipsReg<1, "p1">;
265 def P2 : MipsReg<2, "p2">;
223e47cc 266
223e47cc
LB		 267}
268
269//===----------------------------------------------------------------------===//
270// Register Classes
271//===----------------------------------------------------------------------===//
272
1a4d82fc 273class GPR32Class<list<ValueType> regTypes> :
223e47cc
LB		 274 RegisterClass<"Mips", regTypes, 32, (add
275 // Reserved
276 ZERO, AT,
277 // Return Values and Arguments
278 V0, V1, A0, A1, A2, A3,
279 // Not preserved across procedure calls
280 T0, T1, T2, T3, T4, T5, T6, T7,
281 // Callee save
282 S0, S1, S2, S3, S4, S5, S6, S7,
283 // Not preserved across procedure calls
284 T8, T9,
285 // Reserved
286 K0, K1, GP, SP, FP, RA)>;
287
1a4d82fc
JJ		 288def GPR32 : GPR32Class<[i32]>;
289def DSPR : GPR32Class<[v4i8, v2i16]>;
223e47cc 290
85aaf69f
SL		 291def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
292 // Callee save
293 S0, S1,
294 // Return Values and Arguments
295 V0, V1, A0, A1, A2, A3)>;
296
297def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
298 // Reserved
299 ZERO,
300 // Callee save
301 S1,
302 // Return Values and Arguments
303 V0, V1, A0, A1, A2, A3)>;
304
1a4d82fc 305def GPR64 : RegisterClass<"Mips", [i64], 64, (add
223e47cc
LB		 306// Reserved
307 ZERO_64, AT_64,
308 // Return Values and Arguments
309 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
310 // Not preserved across procedure calls
311 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
312 // Callee save
313 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
314 // Not preserved across procedure calls
315 T8_64, T9_64,
316 // Reserved
317 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
318
319def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
320 // Return Values and Arguments
321 V0, V1, A0, A1, A2, A3,
322 // Callee save
323 S0, S1)>;
324
1a4d82fc
JJ		 325def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
326 // Return Values and Arguments
327 V0, V1, A0, A1, A2, A3,
328 // Callee save
329 S0, S1,
330 SP)>;
331
970d7e83 332def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
223e47cc 333
970d7e83 334def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
223e47cc
LB		 335
336// 64bit fp:
337// * FGR64 - 32 64-bit registers
338// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
339//
340// 32bit fp:
341// * FGR32 - 16 32-bit even registers
342// * FGR32 - 32 32-bit registers (single float only mode)
343def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
344
1a4d82fc
JJ		 345def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
346 Unallocatable;
347
223e47cc
LB		 348def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
349 // Return Values and Arguments
350 D0, D1,
351 // Not preserved across procedure calls
352 D2, D3, D4, D5,
353 // Return Values and Arguments
354 D6, D7,
355 // Not preserved across procedure calls
356 D8, D9,
357 // Callee save
358 D10, D11, D12, D13, D14, D15)>;
359
360def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
361
1a4d82fc
JJ		 362// Used to reserve odd registers when given -mattr=+nooddspreg
363// FIXME: Remove double precision registers from this set.
364def OddSP : RegisterClass<"Mips", [f32], 32,
365 (add (decimate (sequence "F%u", 1, 31), 2),
366 (decimate (sequence "F_HI%u", 1, 31), 2),
367 (decimate (sequence "D%u", 1, 15), 2),
368 (decimate (sequence "D%u_64", 1, 31), 2))>,
369 Unallocatable;
370
371// FP control registers.
372def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
373 Unallocatable;
374
375// FP condition code registers.
376def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
377 Unallocatable;
378
379// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
380// This class allows us to represent this in codegen patterns.
381def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
382
383def MSA128B: RegisterClass<"Mips", [v16i8], 128,
384 (sequence "W%u", 0, 31)>;
385def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
386 (sequence "W%u", 0, 31)>;
387def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
388 (sequence "W%u", 0, 31)>;
389def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
390 (sequence "W%u", 0, 31)>;
391
392def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
393 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
223e47cc
LB		 394
395// Hi/Lo Registers
1a4d82fc
JJ		 396def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
397def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
398def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
399def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
400def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
401def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
223e47cc
LB		 402
403// Hardware registers
1a4d82fc
JJ		 404def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
405 Unallocatable;
223e47cc
LB		 406
407// Accumulator Registers
1a4d82fc
JJ		 408def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
409 let Size = 64;
410}
970d7e83 411
1a4d82fc
JJ		 412def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
413 let Size = 128;
970d7e83
LB		 414}
415
1a4d82fc
JJ		 416def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
417 let Size = 64;
970d7e83
LB		 418}
419
1a4d82fc
JJ		 420def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
421
422// Coprocessor 2 registers.
423def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
424 Unallocatable;
425
426// Coprocessor 3 registers.
427def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
428 Unallocatable;
429
430// Octeon multiplier and product registers
431def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
432 Unallocatable;
433def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
434 Unallocatable;
435
436// Register Operands.
437
438class MipsAsmRegOperand : AsmOperandClass {
439 let ParserMethod = "parseAnyRegister";
440}
441
442def GPR64AsmOperand : MipsAsmRegOperand {
443 let Name = "GPR64AsmReg";
444 let PredicateMethod = "isGPRAsmReg";
445}
446
447def GPR32AsmOperand : MipsAsmRegOperand {
448 let Name = "GPR32AsmReg";
449 let PredicateMethod = "isGPRAsmReg";
450}
451
85aaf69f
SL		 452def GPRMM16AsmOperand : MipsAsmRegOperand {
453 let Name = "GPRMM16AsmReg";
454 let PredicateMethod = "isMM16AsmReg";
455}
456
457def GPRMM16AsmOperandZero : MipsAsmRegOperand {
458 let Name = "GPRMM16AsmRegZero";
459 let PredicateMethod = "isMM16AsmRegZero";
460}
461
1a4d82fc
JJ		 462def ACC64DSPAsmOperand : MipsAsmRegOperand {
463 let Name = "ACC64DSPAsmReg";
464 let PredicateMethod = "isACCAsmReg";
970d7e83
LB		 465}
466
1a4d82fc
JJ		 467def HI32DSPAsmOperand : MipsAsmRegOperand {
468 let Name = "HI32DSPAsmReg";
469 let PredicateMethod = "isACCAsmReg";
970d7e83
LB		 470}
471
1a4d82fc
JJ		 472def LO32DSPAsmOperand : MipsAsmRegOperand {
473 let Name = "LO32DSPAsmReg";
474 let PredicateMethod = "isACCAsmReg";
970d7e83
LB		 475}
476
1a4d82fc
JJ		 477def CCRAsmOperand : MipsAsmRegOperand {
478 let Name = "CCRAsmReg";
479}
480
481def AFGR64AsmOperand : MipsAsmRegOperand {
482 let Name = "AFGR64AsmReg";
483 let PredicateMethod = "isFGRAsmReg";
484}
485
486def FGR64AsmOperand : MipsAsmRegOperand {
487 let Name = "FGR64AsmReg";
488 let PredicateMethod = "isFGRAsmReg";
489}
490
491def FGR32AsmOperand : MipsAsmRegOperand {
492 let Name = "FGR32AsmReg";
493 let PredicateMethod = "isFGRAsmReg";
494}
495
496def FGRH32AsmOperand : MipsAsmRegOperand {
497 let Name = "FGRH32AsmReg";
498 let PredicateMethod = "isFGRAsmReg";
499}
500
501def FCCRegsAsmOperand : MipsAsmRegOperand {
502 let Name = "FCCAsmReg";
503}
504
505def MSA128AsmOperand : MipsAsmRegOperand {
506 let Name = "MSA128AsmReg";
507}
508
509def MSACtrlAsmOperand : MipsAsmRegOperand {
510 let Name = "MSACtrlAsmReg";
511}
512
513def GPR32Opnd : RegisterOperand<GPR32> {
514 let ParserMatchClass = GPR32AsmOperand;
515}
516
85aaf69f
SL		 517def GPRMM16Opnd : RegisterOperand<GPRMM16> {
518 let ParserMatchClass = GPRMM16AsmOperand;
519}
520
521def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
522 let ParserMatchClass = GPRMM16AsmOperandZero;
523}
524
1a4d82fc
JJ		 525def GPR64Opnd : RegisterOperand<GPR64> {
526 let ParserMatchClass = GPR64AsmOperand;
527}
528
529def DSPROpnd : RegisterOperand<DSPR> {
530 let ParserMatchClass = GPR32AsmOperand;
531}
532
533def CCROpnd : RegisterOperand<CCR> {
970d7e83
LB		 534 let ParserMatchClass = CCRAsmOperand;
535}
536
1a4d82fc
JJ		 537def HWRegsAsmOperand : MipsAsmRegOperand {
538 let Name = "HWRegsAsmReg";
970d7e83
LB		 539}
540
1a4d82fc
JJ		 541def COP2AsmOperand : MipsAsmRegOperand {
542 let Name = "COP2AsmReg";
970d7e83
LB		 543}
544
1a4d82fc
JJ		 545def COP3AsmOperand : MipsAsmRegOperand {
546 let Name = "COP3AsmReg";
547}
548
549def HWRegsOpnd : RegisterOperand<HWRegs> {
970d7e83
LB		 550 let ParserMatchClass = HWRegsAsmOperand;
551}
552
1a4d82fc
JJ		 553def AFGR64Opnd : RegisterOperand<AFGR64> {
554 let ParserMatchClass = AFGR64AsmOperand;
555}
556
557def FGR64Opnd : RegisterOperand<FGR64> {
558 let ParserMatchClass = FGR64AsmOperand;
559}
560
561def FGR32Opnd : RegisterOperand<FGR32> {
562 let ParserMatchClass = FGR32AsmOperand;
563}
564
565def FGRCCOpnd : RegisterOperand<FGRCC> {
566 // The assembler doesn't use register classes so we can re-use
567 // FGR32AsmOperand.
568 let ParserMatchClass = FGR32AsmOperand;
569}
570
571def FGRH32Opnd : RegisterOperand<FGRH32> {
572 let ParserMatchClass = FGRH32AsmOperand;
573}
574
575def FCCRegsOpnd : RegisterOperand<FCC> {
576 let ParserMatchClass = FCCRegsAsmOperand;
577}
578
579def LO32DSPOpnd : RegisterOperand<LO32DSP> {
580 let ParserMatchClass = LO32DSPAsmOperand;
581}
582
583def HI32DSPOpnd : RegisterOperand<HI32DSP> {
584 let ParserMatchClass = HI32DSPAsmOperand;
585}
586
587def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
588 let ParserMatchClass = ACC64DSPAsmOperand;
589}
590
591def COP2Opnd : RegisterOperand<COP2> {
592 let ParserMatchClass = COP2AsmOperand;
593}
594
595def COP3Opnd : RegisterOperand<COP3> {
596 let ParserMatchClass = COP3AsmOperand;
970d7e83 597}
1a4d82fc
JJ		 598
599def MSA128BOpnd : RegisterOperand<MSA128B> {
600 let ParserMatchClass = MSA128AsmOperand;
601}
602
603def MSA128HOpnd : RegisterOperand<MSA128H> {
604 let ParserMatchClass = MSA128AsmOperand;
605}
606
607def MSA128WOpnd : RegisterOperand<MSA128W> {
608 let ParserMatchClass = MSA128AsmOperand;
609}
610
611def MSA128DOpnd : RegisterOperand<MSA128D> {
612 let ParserMatchClass = MSA128AsmOperand;
613}
614
615def MSA128CROpnd : RegisterOperand<MSACtrl> {
616 let ParserMatchClass = MSACtrlAsmOperand;
617}
backport for Debian buster