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1a4d82fc JJ |
1 | //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | ||
10 | #include "MCTargetDesc/PPCMCTargetDesc.h" | |
11 | #include "MCTargetDesc/PPCMCExpr.h" | |
12 | #include "PPCTargetStreamer.h" | |
13 | #include "llvm/ADT/STLExtras.h" | |
14 | #include "llvm/ADT/SmallString.h" | |
15 | #include "llvm/ADT/SmallVector.h" | |
16 | #include "llvm/ADT/StringSwitch.h" | |
17 | #include "llvm/ADT/Twine.h" | |
18 | #include "llvm/MC/MCContext.h" | |
19 | #include "llvm/MC/MCExpr.h" | |
20 | #include "llvm/MC/MCInst.h" | |
21 | #include "llvm/MC/MCInstrInfo.h" | |
22 | #include "llvm/MC/MCParser/MCAsmLexer.h" | |
23 | #include "llvm/MC/MCParser/MCAsmParser.h" | |
24 | #include "llvm/MC/MCParser/MCParsedAsmOperand.h" | |
25 | #include "llvm/MC/MCRegisterInfo.h" | |
26 | #include "llvm/MC/MCStreamer.h" | |
27 | #include "llvm/MC/MCSubtargetInfo.h" | |
28 | #include "llvm/MC/MCTargetAsmParser.h" | |
29 | #include "llvm/Support/SourceMgr.h" | |
30 | #include "llvm/Support/TargetRegistry.h" | |
31 | #include "llvm/Support/raw_ostream.h" | |
32 | ||
33 | using namespace llvm; | |
34 | ||
85aaf69f | 35 | static const MCPhysReg RRegs[32] = { |
1a4d82fc JJ |
36 | PPC::R0, PPC::R1, PPC::R2, PPC::R3, |
37 | PPC::R4, PPC::R5, PPC::R6, PPC::R7, | |
38 | PPC::R8, PPC::R9, PPC::R10, PPC::R11, | |
39 | PPC::R12, PPC::R13, PPC::R14, PPC::R15, | |
40 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, | |
41 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, | |
42 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, | |
43 | PPC::R28, PPC::R29, PPC::R30, PPC::R31 | |
44 | }; | |
85aaf69f | 45 | static const MCPhysReg RRegsNoR0[32] = { |
1a4d82fc JJ |
46 | PPC::ZERO, |
47 | PPC::R1, PPC::R2, PPC::R3, | |
48 | PPC::R4, PPC::R5, PPC::R6, PPC::R7, | |
49 | PPC::R8, PPC::R9, PPC::R10, PPC::R11, | |
50 | PPC::R12, PPC::R13, PPC::R14, PPC::R15, | |
51 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, | |
52 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, | |
53 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, | |
54 | PPC::R28, PPC::R29, PPC::R30, PPC::R31 | |
55 | }; | |
85aaf69f | 56 | static const MCPhysReg XRegs[32] = { |
1a4d82fc JJ |
57 | PPC::X0, PPC::X1, PPC::X2, PPC::X3, |
58 | PPC::X4, PPC::X5, PPC::X6, PPC::X7, | |
59 | PPC::X8, PPC::X9, PPC::X10, PPC::X11, | |
60 | PPC::X12, PPC::X13, PPC::X14, PPC::X15, | |
61 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, | |
62 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, | |
63 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, | |
64 | PPC::X28, PPC::X29, PPC::X30, PPC::X31 | |
65 | }; | |
85aaf69f | 66 | static const MCPhysReg XRegsNoX0[32] = { |
1a4d82fc JJ |
67 | PPC::ZERO8, |
68 | PPC::X1, PPC::X2, PPC::X3, | |
69 | PPC::X4, PPC::X5, PPC::X6, PPC::X7, | |
70 | PPC::X8, PPC::X9, PPC::X10, PPC::X11, | |
71 | PPC::X12, PPC::X13, PPC::X14, PPC::X15, | |
72 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, | |
73 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, | |
74 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, | |
75 | PPC::X28, PPC::X29, PPC::X30, PPC::X31 | |
76 | }; | |
85aaf69f | 77 | static const MCPhysReg FRegs[32] = { |
1a4d82fc JJ |
78 | PPC::F0, PPC::F1, PPC::F2, PPC::F3, |
79 | PPC::F4, PPC::F5, PPC::F6, PPC::F7, | |
80 | PPC::F8, PPC::F9, PPC::F10, PPC::F11, | |
81 | PPC::F12, PPC::F13, PPC::F14, PPC::F15, | |
82 | PPC::F16, PPC::F17, PPC::F18, PPC::F19, | |
83 | PPC::F20, PPC::F21, PPC::F22, PPC::F23, | |
84 | PPC::F24, PPC::F25, PPC::F26, PPC::F27, | |
85 | PPC::F28, PPC::F29, PPC::F30, PPC::F31 | |
86 | }; | |
85aaf69f | 87 | static const MCPhysReg VRegs[32] = { |
1a4d82fc JJ |
88 | PPC::V0, PPC::V1, PPC::V2, PPC::V3, |
89 | PPC::V4, PPC::V5, PPC::V6, PPC::V7, | |
90 | PPC::V8, PPC::V9, PPC::V10, PPC::V11, | |
91 | PPC::V12, PPC::V13, PPC::V14, PPC::V15, | |
92 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, | |
93 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, | |
94 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, | |
95 | PPC::V28, PPC::V29, PPC::V30, PPC::V31 | |
96 | }; | |
85aaf69f | 97 | static const MCPhysReg VSRegs[64] = { |
1a4d82fc JJ |
98 | PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, |
99 | PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, | |
100 | PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, | |
101 | PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, | |
102 | PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, | |
103 | PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, | |
104 | PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, | |
105 | PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, | |
106 | ||
107 | PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, | |
108 | PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, | |
109 | PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, | |
110 | PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, | |
111 | PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, | |
112 | PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, | |
113 | PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, | |
114 | PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 | |
115 | }; | |
85aaf69f | 116 | static const MCPhysReg VSFRegs[64] = { |
1a4d82fc JJ |
117 | PPC::F0, PPC::F1, PPC::F2, PPC::F3, |
118 | PPC::F4, PPC::F5, PPC::F6, PPC::F7, | |
119 | PPC::F8, PPC::F9, PPC::F10, PPC::F11, | |
120 | PPC::F12, PPC::F13, PPC::F14, PPC::F15, | |
121 | PPC::F16, PPC::F17, PPC::F18, PPC::F19, | |
122 | PPC::F20, PPC::F21, PPC::F22, PPC::F23, | |
123 | PPC::F24, PPC::F25, PPC::F26, PPC::F27, | |
124 | PPC::F28, PPC::F29, PPC::F30, PPC::F31, | |
125 | ||
126 | PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, | |
127 | PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, | |
128 | PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, | |
129 | PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, | |
130 | PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, | |
131 | PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, | |
132 | PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, | |
133 | PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 | |
134 | }; | |
85aaf69f | 135 | static const MCPhysReg CRBITRegs[32] = { |
1a4d82fc JJ |
136 | PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, |
137 | PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, | |
138 | PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, | |
139 | PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, | |
140 | PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, | |
141 | PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, | |
142 | PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, | |
143 | PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN | |
144 | }; | |
85aaf69f | 145 | static const MCPhysReg CRRegs[8] = { |
1a4d82fc JJ |
146 | PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, |
147 | PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 | |
148 | }; | |
149 | ||
150 | // Evaluate an expression containing condition register | |
151 | // or condition register field symbols. Returns positive | |
152 | // value on success, or -1 on error. | |
153 | static int64_t | |
154 | EvaluateCRExpr(const MCExpr *E) { | |
155 | switch (E->getKind()) { | |
156 | case MCExpr::Target: | |
157 | return -1; | |
158 | ||
159 | case MCExpr::Constant: { | |
160 | int64_t Res = cast<MCConstantExpr>(E)->getValue(); | |
161 | return Res < 0 ? -1 : Res; | |
162 | } | |
163 | ||
164 | case MCExpr::SymbolRef: { | |
165 | const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); | |
166 | StringRef Name = SRE->getSymbol().getName(); | |
167 | ||
168 | if (Name == "lt") return 0; | |
169 | if (Name == "gt") return 1; | |
170 | if (Name == "eq") return 2; | |
171 | if (Name == "so") return 3; | |
172 | if (Name == "un") return 3; | |
173 | ||
174 | if (Name == "cr0") return 0; | |
175 | if (Name == "cr1") return 1; | |
176 | if (Name == "cr2") return 2; | |
177 | if (Name == "cr3") return 3; | |
178 | if (Name == "cr4") return 4; | |
179 | if (Name == "cr5") return 5; | |
180 | if (Name == "cr6") return 6; | |
181 | if (Name == "cr7") return 7; | |
182 | ||
183 | return -1; | |
184 | } | |
185 | ||
186 | case MCExpr::Unary: | |
187 | return -1; | |
188 | ||
189 | case MCExpr::Binary: { | |
190 | const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); | |
191 | int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); | |
192 | int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); | |
193 | int64_t Res; | |
194 | ||
195 | if (LHSVal < 0 || RHSVal < 0) | |
196 | return -1; | |
197 | ||
198 | switch (BE->getOpcode()) { | |
199 | default: return -1; | |
200 | case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; | |
201 | case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; | |
202 | } | |
203 | ||
204 | return Res < 0 ? -1 : Res; | |
205 | } | |
206 | } | |
207 | ||
208 | llvm_unreachable("Invalid expression kind!"); | |
209 | } | |
210 | ||
85aaf69f SL |
211 | namespace { |
212 | ||
1a4d82fc JJ |
213 | struct PPCOperand; |
214 | ||
215 | class PPCAsmParser : public MCTargetAsmParser { | |
216 | MCSubtargetInfo &STI; | |
1a4d82fc JJ |
217 | const MCInstrInfo &MII; |
218 | bool IsPPC64; | |
219 | bool IsDarwin; | |
220 | ||
85aaf69f SL |
221 | void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } |
222 | bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); } | |
1a4d82fc JJ |
223 | |
224 | bool isPPC64() const { return IsPPC64; } | |
225 | bool isDarwin() const { return IsDarwin; } | |
226 | ||
227 | bool MatchRegisterName(const AsmToken &Tok, | |
228 | unsigned &RegNo, int64_t &IntVal); | |
229 | ||
230 | bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; | |
231 | ||
232 | const MCExpr *ExtractModifierFromExpr(const MCExpr *E, | |
233 | PPCMCExpr::VariantKind &Variant); | |
234 | const MCExpr *FixupVariantKind(const MCExpr *E); | |
235 | bool ParseExpression(const MCExpr *&EVal); | |
236 | bool ParseDarwinExpression(const MCExpr *&EVal); | |
237 | ||
238 | bool ParseOperand(OperandVector &Operands); | |
239 | ||
240 | bool ParseDirectiveWord(unsigned Size, SMLoc L); | |
241 | bool ParseDirectiveTC(unsigned Size, SMLoc L); | |
242 | bool ParseDirectiveMachine(SMLoc L); | |
243 | bool ParseDarwinDirectiveMachine(SMLoc L); | |
244 | bool ParseDirectiveAbiVersion(SMLoc L); | |
245 | bool ParseDirectiveLocalEntry(SMLoc L); | |
246 | ||
247 | bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |
248 | OperandVector &Operands, MCStreamer &Out, | |
249 | uint64_t &ErrorInfo, | |
250 | bool MatchingInlineAsm) override; | |
251 | ||
252 | void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); | |
253 | ||
254 | /// @name Auto-generated Match Functions | |
255 | /// { | |
256 | ||
257 | #define GET_ASSEMBLER_HEADER | |
258 | #include "PPCGenAsmMatcher.inc" | |
259 | ||
260 | /// } | |
261 | ||
262 | ||
263 | public: | |
264 | PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, | |
85aaf69f SL |
265 | const MCInstrInfo &_MII, const MCTargetOptions &Options) |
266 | : MCTargetAsmParser(), STI(_STI), MII(_MII) { | |
1a4d82fc JJ |
267 | // Check for 64-bit vs. 32-bit pointer mode. |
268 | Triple TheTriple(STI.getTargetTriple()); | |
269 | IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || | |
270 | TheTriple.getArch() == Triple::ppc64le); | |
271 | IsDarwin = TheTriple.isMacOSX(); | |
272 | // Initialize the set of available features. | |
273 | setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); | |
274 | } | |
275 | ||
276 | bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, | |
277 | SMLoc NameLoc, OperandVector &Operands) override; | |
278 | ||
279 | bool ParseDirective(AsmToken DirectiveID) override; | |
280 | ||
281 | unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, | |
282 | unsigned Kind) override; | |
283 | ||
284 | const MCExpr *applyModifierToExpr(const MCExpr *E, | |
285 | MCSymbolRefExpr::VariantKind, | |
286 | MCContext &Ctx) override; | |
287 | }; | |
288 | ||
289 | /// PPCOperand - Instances of this class represent a parsed PowerPC machine | |
290 | /// instruction. | |
291 | struct PPCOperand : public MCParsedAsmOperand { | |
292 | enum KindTy { | |
293 | Token, | |
294 | Immediate, | |
295 | ContextImmediate, | |
296 | Expression, | |
297 | TLSRegister | |
298 | } Kind; | |
299 | ||
300 | SMLoc StartLoc, EndLoc; | |
301 | bool IsPPC64; | |
302 | ||
303 | struct TokOp { | |
304 | const char *Data; | |
305 | unsigned Length; | |
306 | }; | |
307 | ||
308 | struct ImmOp { | |
309 | int64_t Val; | |
310 | }; | |
311 | ||
312 | struct ExprOp { | |
313 | const MCExpr *Val; | |
314 | int64_t CRVal; // Cached result of EvaluateCRExpr(Val) | |
315 | }; | |
316 | ||
317 | struct TLSRegOp { | |
318 | const MCSymbolRefExpr *Sym; | |
319 | }; | |
320 | ||
321 | union { | |
322 | struct TokOp Tok; | |
323 | struct ImmOp Imm; | |
324 | struct ExprOp Expr; | |
325 | struct TLSRegOp TLSReg; | |
326 | }; | |
327 | ||
328 | PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} | |
329 | public: | |
330 | PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { | |
331 | Kind = o.Kind; | |
332 | StartLoc = o.StartLoc; | |
333 | EndLoc = o.EndLoc; | |
334 | IsPPC64 = o.IsPPC64; | |
335 | switch (Kind) { | |
336 | case Token: | |
337 | Tok = o.Tok; | |
338 | break; | |
339 | case Immediate: | |
340 | case ContextImmediate: | |
341 | Imm = o.Imm; | |
342 | break; | |
343 | case Expression: | |
344 | Expr = o.Expr; | |
345 | break; | |
346 | case TLSRegister: | |
347 | TLSReg = o.TLSReg; | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | /// getStartLoc - Get the location of the first token of this operand. | |
353 | SMLoc getStartLoc() const override { return StartLoc; } | |
354 | ||
355 | /// getEndLoc - Get the location of the last token of this operand. | |
356 | SMLoc getEndLoc() const override { return EndLoc; } | |
357 | ||
358 | /// isPPC64 - True if this operand is for an instruction in 64-bit mode. | |
359 | bool isPPC64() const { return IsPPC64; } | |
360 | ||
361 | int64_t getImm() const { | |
362 | assert(Kind == Immediate && "Invalid access!"); | |
363 | return Imm.Val; | |
364 | } | |
365 | int64_t getImmS16Context() const { | |
366 | assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!"); | |
367 | if (Kind == Immediate) | |
368 | return Imm.Val; | |
369 | return static_cast<int16_t>(Imm.Val); | |
370 | } | |
371 | int64_t getImmU16Context() const { | |
372 | assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!"); | |
373 | return Imm.Val; | |
374 | } | |
375 | ||
376 | const MCExpr *getExpr() const { | |
377 | assert(Kind == Expression && "Invalid access!"); | |
378 | return Expr.Val; | |
379 | } | |
380 | ||
381 | int64_t getExprCRVal() const { | |
382 | assert(Kind == Expression && "Invalid access!"); | |
383 | return Expr.CRVal; | |
384 | } | |
385 | ||
386 | const MCExpr *getTLSReg() const { | |
387 | assert(Kind == TLSRegister && "Invalid access!"); | |
388 | return TLSReg.Sym; | |
389 | } | |
390 | ||
391 | unsigned getReg() const override { | |
392 | assert(isRegNumber() && "Invalid access!"); | |
393 | return (unsigned) Imm.Val; | |
394 | } | |
395 | ||
396 | unsigned getVSReg() const { | |
397 | assert(isVSRegNumber() && "Invalid access!"); | |
398 | return (unsigned) Imm.Val; | |
399 | } | |
400 | ||
401 | unsigned getCCReg() const { | |
402 | assert(isCCRegNumber() && "Invalid access!"); | |
403 | return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); | |
404 | } | |
405 | ||
406 | unsigned getCRBit() const { | |
407 | assert(isCRBitNumber() && "Invalid access!"); | |
408 | return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); | |
409 | } | |
410 | ||
411 | unsigned getCRBitMask() const { | |
412 | assert(isCRBitMask() && "Invalid access!"); | |
413 | return 7 - countTrailingZeros<uint64_t>(Imm.Val); | |
414 | } | |
415 | ||
416 | bool isToken() const override { return Kind == Token; } | |
417 | bool isImm() const override { return Kind == Immediate || Kind == Expression; } | |
418 | bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } | |
419 | bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } | |
420 | bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } | |
421 | bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } | |
422 | bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } | |
423 | bool isU6ImmX2() const { return Kind == Immediate && | |
424 | isUInt<6>(getImm()) && | |
425 | (getImm() & 1) == 0; } | |
426 | bool isU7ImmX4() const { return Kind == Immediate && | |
427 | isUInt<7>(getImm()) && | |
428 | (getImm() & 3) == 0; } | |
429 | bool isU8ImmX8() const { return Kind == Immediate && | |
430 | isUInt<8>(getImm()) && | |
431 | (getImm() & 7) == 0; } | |
432 | bool isU16Imm() const { | |
433 | switch (Kind) { | |
434 | case Expression: | |
435 | return true; | |
436 | case Immediate: | |
437 | case ContextImmediate: | |
438 | return isUInt<16>(getImmU16Context()); | |
439 | default: | |
440 | return false; | |
441 | } | |
442 | } | |
443 | bool isS16Imm() const { | |
444 | switch (Kind) { | |
445 | case Expression: | |
446 | return true; | |
447 | case Immediate: | |
448 | case ContextImmediate: | |
449 | return isInt<16>(getImmS16Context()); | |
450 | default: | |
451 | return false; | |
452 | } | |
453 | } | |
454 | bool isS16ImmX4() const { return Kind == Expression || | |
455 | (Kind == Immediate && isInt<16>(getImm()) && | |
456 | (getImm() & 3) == 0); } | |
457 | bool isS17Imm() const { | |
458 | switch (Kind) { | |
459 | case Expression: | |
460 | return true; | |
461 | case Immediate: | |
462 | case ContextImmediate: | |
463 | return isInt<17>(getImmS16Context()); | |
464 | default: | |
465 | return false; | |
466 | } | |
467 | } | |
468 | bool isTLSReg() const { return Kind == TLSRegister; } | |
469 | bool isDirectBr() const { | |
470 | if (Kind == Expression) | |
471 | return true; | |
472 | if (Kind != Immediate) | |
473 | return false; | |
474 | // Operand must be 64-bit aligned, signed 27-bit immediate. | |
475 | if ((getImm() & 3) != 0) | |
476 | return false; | |
477 | if (isInt<26>(getImm())) | |
478 | return true; | |
479 | if (!IsPPC64) { | |
480 | // In 32-bit mode, large 32-bit quantities wrap around. | |
481 | if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) | |
482 | return true; | |
483 | } | |
484 | return false; | |
485 | } | |
486 | bool isCondBr() const { return Kind == Expression || | |
487 | (Kind == Immediate && isInt<16>(getImm()) && | |
488 | (getImm() & 3) == 0); } | |
489 | bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } | |
490 | bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); } | |
491 | bool isCCRegNumber() const { return (Kind == Expression | |
492 | && isUInt<3>(getExprCRVal())) || | |
493 | (Kind == Immediate | |
494 | && isUInt<3>(getImm())); } | |
495 | bool isCRBitNumber() const { return (Kind == Expression | |
496 | && isUInt<5>(getExprCRVal())) || | |
497 | (Kind == Immediate | |
498 | && isUInt<5>(getImm())); } | |
499 | bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && | |
500 | isPowerOf2_32(getImm()); } | |
501 | bool isMem() const override { return false; } | |
502 | bool isReg() const override { return false; } | |
503 | ||
504 | void addRegOperands(MCInst &Inst, unsigned N) const { | |
505 | llvm_unreachable("addRegOperands"); | |
506 | } | |
507 | ||
508 | void addRegGPRCOperands(MCInst &Inst, unsigned N) const { | |
509 | assert(N == 1 && "Invalid number of operands!"); | |
510 | Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); | |
511 | } | |
512 | ||
513 | void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { | |
514 | assert(N == 1 && "Invalid number of operands!"); | |
515 | Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); | |
516 | } | |
517 | ||
518 | void addRegG8RCOperands(MCInst &Inst, unsigned N) const { | |
519 | assert(N == 1 && "Invalid number of operands!"); | |
520 | Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); | |
521 | } | |
522 | ||
523 | void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { | |
524 | assert(N == 1 && "Invalid number of operands!"); | |
525 | Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); | |
526 | } | |
527 | ||
528 | void addRegGxRCOperands(MCInst &Inst, unsigned N) const { | |
529 | if (isPPC64()) | |
530 | addRegG8RCOperands(Inst, N); | |
531 | else | |
532 | addRegGPRCOperands(Inst, N); | |
533 | } | |
534 | ||
535 | void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { | |
536 | if (isPPC64()) | |
537 | addRegG8RCNoX0Operands(Inst, N); | |
538 | else | |
539 | addRegGPRCNoR0Operands(Inst, N); | |
540 | } | |
541 | ||
542 | void addRegF4RCOperands(MCInst &Inst, unsigned N) const { | |
543 | assert(N == 1 && "Invalid number of operands!"); | |
544 | Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); | |
545 | } | |
546 | ||
547 | void addRegF8RCOperands(MCInst &Inst, unsigned N) const { | |
548 | assert(N == 1 && "Invalid number of operands!"); | |
549 | Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); | |
550 | } | |
551 | ||
552 | void addRegVRRCOperands(MCInst &Inst, unsigned N) const { | |
553 | assert(N == 1 && "Invalid number of operands!"); | |
554 | Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); | |
555 | } | |
556 | ||
557 | void addRegVSRCOperands(MCInst &Inst, unsigned N) const { | |
558 | assert(N == 1 && "Invalid number of operands!"); | |
559 | Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()])); | |
560 | } | |
561 | ||
562 | void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { | |
563 | assert(N == 1 && "Invalid number of operands!"); | |
564 | Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()])); | |
565 | } | |
566 | ||
567 | void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { | |
568 | assert(N == 1 && "Invalid number of operands!"); | |
569 | Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()])); | |
570 | } | |
571 | ||
572 | void addRegCRRCOperands(MCInst &Inst, unsigned N) const { | |
573 | assert(N == 1 && "Invalid number of operands!"); | |
574 | Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); | |
575 | } | |
576 | ||
577 | void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { | |
578 | assert(N == 1 && "Invalid number of operands!"); | |
579 | Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); | |
580 | } | |
581 | ||
582 | void addImmOperands(MCInst &Inst, unsigned N) const { | |
583 | assert(N == 1 && "Invalid number of operands!"); | |
584 | if (Kind == Immediate) | |
585 | Inst.addOperand(MCOperand::CreateImm(getImm())); | |
586 | else | |
587 | Inst.addOperand(MCOperand::CreateExpr(getExpr())); | |
588 | } | |
589 | ||
590 | void addS16ImmOperands(MCInst &Inst, unsigned N) const { | |
591 | assert(N == 1 && "Invalid number of operands!"); | |
592 | switch (Kind) { | |
593 | case Immediate: | |
594 | Inst.addOperand(MCOperand::CreateImm(getImm())); | |
595 | break; | |
596 | case ContextImmediate: | |
597 | Inst.addOperand(MCOperand::CreateImm(getImmS16Context())); | |
598 | break; | |
599 | default: | |
600 | Inst.addOperand(MCOperand::CreateExpr(getExpr())); | |
601 | break; | |
602 | } | |
603 | } | |
604 | ||
605 | void addU16ImmOperands(MCInst &Inst, unsigned N) const { | |
606 | assert(N == 1 && "Invalid number of operands!"); | |
607 | switch (Kind) { | |
608 | case Immediate: | |
609 | Inst.addOperand(MCOperand::CreateImm(getImm())); | |
610 | break; | |
611 | case ContextImmediate: | |
612 | Inst.addOperand(MCOperand::CreateImm(getImmU16Context())); | |
613 | break; | |
614 | default: | |
615 | Inst.addOperand(MCOperand::CreateExpr(getExpr())); | |
616 | break; | |
617 | } | |
618 | } | |
619 | ||
620 | void addBranchTargetOperands(MCInst &Inst, unsigned N) const { | |
621 | assert(N == 1 && "Invalid number of operands!"); | |
622 | if (Kind == Immediate) | |
623 | Inst.addOperand(MCOperand::CreateImm(getImm() / 4)); | |
624 | else | |
625 | Inst.addOperand(MCOperand::CreateExpr(getExpr())); | |
626 | } | |
627 | ||
628 | void addTLSRegOperands(MCInst &Inst, unsigned N) const { | |
629 | assert(N == 1 && "Invalid number of operands!"); | |
630 | Inst.addOperand(MCOperand::CreateExpr(getTLSReg())); | |
631 | } | |
632 | ||
633 | StringRef getToken() const { | |
634 | assert(Kind == Token && "Invalid access!"); | |
635 | return StringRef(Tok.Data, Tok.Length); | |
636 | } | |
637 | ||
638 | void print(raw_ostream &OS) const override; | |
639 | ||
640 | static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, | |
641 | bool IsPPC64) { | |
642 | auto Op = make_unique<PPCOperand>(Token); | |
643 | Op->Tok.Data = Str.data(); | |
644 | Op->Tok.Length = Str.size(); | |
645 | Op->StartLoc = S; | |
646 | Op->EndLoc = S; | |
647 | Op->IsPPC64 = IsPPC64; | |
648 | return Op; | |
649 | } | |
650 | ||
651 | static std::unique_ptr<PPCOperand> | |
652 | CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { | |
653 | // Allocate extra memory for the string and copy it. | |
654 | // FIXME: This is incorrect, Operands are owned by unique_ptr with a default | |
655 | // deleter which will destroy them by simply using "delete", not correctly | |
656 | // calling operator delete on this extra memory after calling the dtor | |
657 | // explicitly. | |
658 | void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); | |
659 | std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); | |
660 | Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); | |
661 | Op->Tok.Length = Str.size(); | |
662 | std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); | |
663 | Op->StartLoc = S; | |
664 | Op->EndLoc = S; | |
665 | Op->IsPPC64 = IsPPC64; | |
666 | return Op; | |
667 | } | |
668 | ||
669 | static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, | |
670 | bool IsPPC64) { | |
671 | auto Op = make_unique<PPCOperand>(Immediate); | |
672 | Op->Imm.Val = Val; | |
673 | Op->StartLoc = S; | |
674 | Op->EndLoc = E; | |
675 | Op->IsPPC64 = IsPPC64; | |
676 | return Op; | |
677 | } | |
678 | ||
679 | static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, | |
680 | SMLoc E, bool IsPPC64) { | |
681 | auto Op = make_unique<PPCOperand>(Expression); | |
682 | Op->Expr.Val = Val; | |
683 | Op->Expr.CRVal = EvaluateCRExpr(Val); | |
684 | Op->StartLoc = S; | |
685 | Op->EndLoc = E; | |
686 | Op->IsPPC64 = IsPPC64; | |
687 | return Op; | |
688 | } | |
689 | ||
690 | static std::unique_ptr<PPCOperand> | |
691 | CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { | |
692 | auto Op = make_unique<PPCOperand>(TLSRegister); | |
693 | Op->TLSReg.Sym = Sym; | |
694 | Op->StartLoc = S; | |
695 | Op->EndLoc = E; | |
696 | Op->IsPPC64 = IsPPC64; | |
697 | return Op; | |
698 | } | |
699 | ||
700 | static std::unique_ptr<PPCOperand> | |
701 | CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { | |
702 | auto Op = make_unique<PPCOperand>(ContextImmediate); | |
703 | Op->Imm.Val = Val; | |
704 | Op->StartLoc = S; | |
705 | Op->EndLoc = E; | |
706 | Op->IsPPC64 = IsPPC64; | |
707 | return Op; | |
708 | } | |
709 | ||
710 | static std::unique_ptr<PPCOperand> | |
711 | CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { | |
712 | if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) | |
713 | return CreateImm(CE->getValue(), S, E, IsPPC64); | |
714 | ||
715 | if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) | |
716 | if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) | |
717 | return CreateTLSReg(SRE, S, E, IsPPC64); | |
718 | ||
719 | if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { | |
720 | int64_t Res; | |
721 | if (TE->EvaluateAsConstant(Res)) | |
722 | return CreateContextImm(Res, S, E, IsPPC64); | |
723 | } | |
724 | ||
725 | return CreateExpr(Val, S, E, IsPPC64); | |
726 | } | |
727 | }; | |
728 | ||
729 | } // end anonymous namespace. | |
730 | ||
731 | void PPCOperand::print(raw_ostream &OS) const { | |
732 | switch (Kind) { | |
733 | case Token: | |
734 | OS << "'" << getToken() << "'"; | |
735 | break; | |
736 | case Immediate: | |
737 | case ContextImmediate: | |
738 | OS << getImm(); | |
739 | break; | |
740 | case Expression: | |
741 | getExpr()->print(OS); | |
742 | break; | |
743 | case TLSRegister: | |
744 | getTLSReg()->print(OS); | |
745 | break; | |
746 | } | |
747 | } | |
748 | ||
749 | static void | |
750 | addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { | |
751 | if (Op.isImm()) { | |
752 | Inst.addOperand(MCOperand::CreateImm(-Op.getImm())); | |
753 | return; | |
754 | } | |
755 | const MCExpr *Expr = Op.getExpr(); | |
756 | if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { | |
757 | if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { | |
758 | Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr())); | |
759 | return; | |
760 | } | |
761 | } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { | |
762 | if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { | |
763 | const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(), | |
764 | BinExpr->getLHS(), Ctx); | |
765 | Inst.addOperand(MCOperand::CreateExpr(NE)); | |
766 | return; | |
767 | } | |
768 | } | |
769 | Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx))); | |
770 | } | |
771 | ||
772 | void PPCAsmParser::ProcessInstruction(MCInst &Inst, | |
773 | const OperandVector &Operands) { | |
774 | int Opcode = Inst.getOpcode(); | |
775 | switch (Opcode) { | |
776 | case PPC::LAx: { | |
777 | MCInst TmpInst; | |
778 | TmpInst.setOpcode(PPC::LA); | |
779 | TmpInst.addOperand(Inst.getOperand(0)); | |
780 | TmpInst.addOperand(Inst.getOperand(2)); | |
781 | TmpInst.addOperand(Inst.getOperand(1)); | |
782 | Inst = TmpInst; | |
783 | break; | |
784 | } | |
785 | case PPC::SUBI: { | |
786 | MCInst TmpInst; | |
787 | TmpInst.setOpcode(PPC::ADDI); | |
788 | TmpInst.addOperand(Inst.getOperand(0)); | |
789 | TmpInst.addOperand(Inst.getOperand(1)); | |
790 | addNegOperand(TmpInst, Inst.getOperand(2), getContext()); | |
791 | Inst = TmpInst; | |
792 | break; | |
793 | } | |
794 | case PPC::SUBIS: { | |
795 | MCInst TmpInst; | |
796 | TmpInst.setOpcode(PPC::ADDIS); | |
797 | TmpInst.addOperand(Inst.getOperand(0)); | |
798 | TmpInst.addOperand(Inst.getOperand(1)); | |
799 | addNegOperand(TmpInst, Inst.getOperand(2), getContext()); | |
800 | Inst = TmpInst; | |
801 | break; | |
802 | } | |
803 | case PPC::SUBIC: { | |
804 | MCInst TmpInst; | |
805 | TmpInst.setOpcode(PPC::ADDIC); | |
806 | TmpInst.addOperand(Inst.getOperand(0)); | |
807 | TmpInst.addOperand(Inst.getOperand(1)); | |
808 | addNegOperand(TmpInst, Inst.getOperand(2), getContext()); | |
809 | Inst = TmpInst; | |
810 | break; | |
811 | } | |
812 | case PPC::SUBICo: { | |
813 | MCInst TmpInst; | |
814 | TmpInst.setOpcode(PPC::ADDICo); | |
815 | TmpInst.addOperand(Inst.getOperand(0)); | |
816 | TmpInst.addOperand(Inst.getOperand(1)); | |
817 | addNegOperand(TmpInst, Inst.getOperand(2), getContext()); | |
818 | Inst = TmpInst; | |
819 | break; | |
820 | } | |
821 | case PPC::EXTLWI: | |
822 | case PPC::EXTLWIo: { | |
823 | MCInst TmpInst; | |
824 | int64_t N = Inst.getOperand(2).getImm(); | |
825 | int64_t B = Inst.getOperand(3).getImm(); | |
826 | TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); | |
827 | TmpInst.addOperand(Inst.getOperand(0)); | |
828 | TmpInst.addOperand(Inst.getOperand(1)); | |
829 | TmpInst.addOperand(MCOperand::CreateImm(B)); | |
830 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
831 | TmpInst.addOperand(MCOperand::CreateImm(N - 1)); | |
832 | Inst = TmpInst; | |
833 | break; | |
834 | } | |
835 | case PPC::EXTRWI: | |
836 | case PPC::EXTRWIo: { | |
837 | MCInst TmpInst; | |
838 | int64_t N = Inst.getOperand(2).getImm(); | |
839 | int64_t B = Inst.getOperand(3).getImm(); | |
840 | TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); | |
841 | TmpInst.addOperand(Inst.getOperand(0)); | |
842 | TmpInst.addOperand(Inst.getOperand(1)); | |
843 | TmpInst.addOperand(MCOperand::CreateImm(B + N)); | |
844 | TmpInst.addOperand(MCOperand::CreateImm(32 - N)); | |
845 | TmpInst.addOperand(MCOperand::CreateImm(31)); | |
846 | Inst = TmpInst; | |
847 | break; | |
848 | } | |
849 | case PPC::INSLWI: | |
850 | case PPC::INSLWIo: { | |
851 | MCInst TmpInst; | |
852 | int64_t N = Inst.getOperand(2).getImm(); | |
853 | int64_t B = Inst.getOperand(3).getImm(); | |
854 | TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); | |
855 | TmpInst.addOperand(Inst.getOperand(0)); | |
856 | TmpInst.addOperand(Inst.getOperand(0)); | |
857 | TmpInst.addOperand(Inst.getOperand(1)); | |
858 | TmpInst.addOperand(MCOperand::CreateImm(32 - B)); | |
859 | TmpInst.addOperand(MCOperand::CreateImm(B)); | |
860 | TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); | |
861 | Inst = TmpInst; | |
862 | break; | |
863 | } | |
864 | case PPC::INSRWI: | |
865 | case PPC::INSRWIo: { | |
866 | MCInst TmpInst; | |
867 | int64_t N = Inst.getOperand(2).getImm(); | |
868 | int64_t B = Inst.getOperand(3).getImm(); | |
869 | TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); | |
870 | TmpInst.addOperand(Inst.getOperand(0)); | |
871 | TmpInst.addOperand(Inst.getOperand(0)); | |
872 | TmpInst.addOperand(Inst.getOperand(1)); | |
873 | TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N))); | |
874 | TmpInst.addOperand(MCOperand::CreateImm(B)); | |
875 | TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); | |
876 | Inst = TmpInst; | |
877 | break; | |
878 | } | |
879 | case PPC::ROTRWI: | |
880 | case PPC::ROTRWIo: { | |
881 | MCInst TmpInst; | |
882 | int64_t N = Inst.getOperand(2).getImm(); | |
883 | TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); | |
884 | TmpInst.addOperand(Inst.getOperand(0)); | |
885 | TmpInst.addOperand(Inst.getOperand(1)); | |
886 | TmpInst.addOperand(MCOperand::CreateImm(32 - N)); | |
887 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
888 | TmpInst.addOperand(MCOperand::CreateImm(31)); | |
889 | Inst = TmpInst; | |
890 | break; | |
891 | } | |
892 | case PPC::SLWI: | |
893 | case PPC::SLWIo: { | |
894 | MCInst TmpInst; | |
895 | int64_t N = Inst.getOperand(2).getImm(); | |
896 | TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); | |
897 | TmpInst.addOperand(Inst.getOperand(0)); | |
898 | TmpInst.addOperand(Inst.getOperand(1)); | |
899 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
900 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
901 | TmpInst.addOperand(MCOperand::CreateImm(31 - N)); | |
902 | Inst = TmpInst; | |
903 | break; | |
904 | } | |
905 | case PPC::SRWI: | |
906 | case PPC::SRWIo: { | |
907 | MCInst TmpInst; | |
908 | int64_t N = Inst.getOperand(2).getImm(); | |
909 | TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); | |
910 | TmpInst.addOperand(Inst.getOperand(0)); | |
911 | TmpInst.addOperand(Inst.getOperand(1)); | |
912 | TmpInst.addOperand(MCOperand::CreateImm(32 - N)); | |
913 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
914 | TmpInst.addOperand(MCOperand::CreateImm(31)); | |
915 | Inst = TmpInst; | |
916 | break; | |
917 | } | |
918 | case PPC::CLRRWI: | |
919 | case PPC::CLRRWIo: { | |
920 | MCInst TmpInst; | |
921 | int64_t N = Inst.getOperand(2).getImm(); | |
922 | TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); | |
923 | TmpInst.addOperand(Inst.getOperand(0)); | |
924 | TmpInst.addOperand(Inst.getOperand(1)); | |
925 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
926 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
927 | TmpInst.addOperand(MCOperand::CreateImm(31 - N)); | |
928 | Inst = TmpInst; | |
929 | break; | |
930 | } | |
931 | case PPC::CLRLSLWI: | |
932 | case PPC::CLRLSLWIo: { | |
933 | MCInst TmpInst; | |
934 | int64_t B = Inst.getOperand(2).getImm(); | |
935 | int64_t N = Inst.getOperand(3).getImm(); | |
936 | TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); | |
937 | TmpInst.addOperand(Inst.getOperand(0)); | |
938 | TmpInst.addOperand(Inst.getOperand(1)); | |
939 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
940 | TmpInst.addOperand(MCOperand::CreateImm(B - N)); | |
941 | TmpInst.addOperand(MCOperand::CreateImm(31 - N)); | |
942 | Inst = TmpInst; | |
943 | break; | |
944 | } | |
945 | case PPC::EXTLDI: | |
946 | case PPC::EXTLDIo: { | |
947 | MCInst TmpInst; | |
948 | int64_t N = Inst.getOperand(2).getImm(); | |
949 | int64_t B = Inst.getOperand(3).getImm(); | |
950 | TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); | |
951 | TmpInst.addOperand(Inst.getOperand(0)); | |
952 | TmpInst.addOperand(Inst.getOperand(1)); | |
953 | TmpInst.addOperand(MCOperand::CreateImm(B)); | |
954 | TmpInst.addOperand(MCOperand::CreateImm(N - 1)); | |
955 | Inst = TmpInst; | |
956 | break; | |
957 | } | |
958 | case PPC::EXTRDI: | |
959 | case PPC::EXTRDIo: { | |
960 | MCInst TmpInst; | |
961 | int64_t N = Inst.getOperand(2).getImm(); | |
962 | int64_t B = Inst.getOperand(3).getImm(); | |
963 | TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); | |
964 | TmpInst.addOperand(Inst.getOperand(0)); | |
965 | TmpInst.addOperand(Inst.getOperand(1)); | |
966 | TmpInst.addOperand(MCOperand::CreateImm(B + N)); | |
967 | TmpInst.addOperand(MCOperand::CreateImm(64 - N)); | |
968 | Inst = TmpInst; | |
969 | break; | |
970 | } | |
971 | case PPC::INSRDI: | |
972 | case PPC::INSRDIo: { | |
973 | MCInst TmpInst; | |
974 | int64_t N = Inst.getOperand(2).getImm(); | |
975 | int64_t B = Inst.getOperand(3).getImm(); | |
976 | TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); | |
977 | TmpInst.addOperand(Inst.getOperand(0)); | |
978 | TmpInst.addOperand(Inst.getOperand(0)); | |
979 | TmpInst.addOperand(Inst.getOperand(1)); | |
980 | TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N))); | |
981 | TmpInst.addOperand(MCOperand::CreateImm(B)); | |
982 | Inst = TmpInst; | |
983 | break; | |
984 | } | |
985 | case PPC::ROTRDI: | |
986 | case PPC::ROTRDIo: { | |
987 | MCInst TmpInst; | |
988 | int64_t N = Inst.getOperand(2).getImm(); | |
989 | TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); | |
990 | TmpInst.addOperand(Inst.getOperand(0)); | |
991 | TmpInst.addOperand(Inst.getOperand(1)); | |
992 | TmpInst.addOperand(MCOperand::CreateImm(64 - N)); | |
993 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
994 | Inst = TmpInst; | |
995 | break; | |
996 | } | |
997 | case PPC::SLDI: | |
998 | case PPC::SLDIo: { | |
999 | MCInst TmpInst; | |
1000 | int64_t N = Inst.getOperand(2).getImm(); | |
1001 | TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); | |
1002 | TmpInst.addOperand(Inst.getOperand(0)); | |
1003 | TmpInst.addOperand(Inst.getOperand(1)); | |
1004 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
1005 | TmpInst.addOperand(MCOperand::CreateImm(63 - N)); | |
1006 | Inst = TmpInst; | |
1007 | break; | |
1008 | } | |
1009 | case PPC::SRDI: | |
1010 | case PPC::SRDIo: { | |
1011 | MCInst TmpInst; | |
1012 | int64_t N = Inst.getOperand(2).getImm(); | |
1013 | TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); | |
1014 | TmpInst.addOperand(Inst.getOperand(0)); | |
1015 | TmpInst.addOperand(Inst.getOperand(1)); | |
1016 | TmpInst.addOperand(MCOperand::CreateImm(64 - N)); | |
1017 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
1018 | Inst = TmpInst; | |
1019 | break; | |
1020 | } | |
1021 | case PPC::CLRRDI: | |
1022 | case PPC::CLRRDIo: { | |
1023 | MCInst TmpInst; | |
1024 | int64_t N = Inst.getOperand(2).getImm(); | |
1025 | TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); | |
1026 | TmpInst.addOperand(Inst.getOperand(0)); | |
1027 | TmpInst.addOperand(Inst.getOperand(1)); | |
1028 | TmpInst.addOperand(MCOperand::CreateImm(0)); | |
1029 | TmpInst.addOperand(MCOperand::CreateImm(63 - N)); | |
1030 | Inst = TmpInst; | |
1031 | break; | |
1032 | } | |
1033 | case PPC::CLRLSLDI: | |
1034 | case PPC::CLRLSLDIo: { | |
1035 | MCInst TmpInst; | |
1036 | int64_t B = Inst.getOperand(2).getImm(); | |
1037 | int64_t N = Inst.getOperand(3).getImm(); | |
1038 | TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); | |
1039 | TmpInst.addOperand(Inst.getOperand(0)); | |
1040 | TmpInst.addOperand(Inst.getOperand(1)); | |
1041 | TmpInst.addOperand(MCOperand::CreateImm(N)); | |
1042 | TmpInst.addOperand(MCOperand::CreateImm(B - N)); | |
1043 | Inst = TmpInst; | |
1044 | break; | |
1045 | } | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |
1050 | OperandVector &Operands, | |
1051 | MCStreamer &Out, uint64_t &ErrorInfo, | |
1052 | bool MatchingInlineAsm) { | |
1053 | MCInst Inst; | |
1054 | ||
1055 | switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { | |
1a4d82fc JJ |
1056 | case Match_Success: |
1057 | // Post-process instructions (typically extended mnemonics) | |
1058 | ProcessInstruction(Inst, Operands); | |
1059 | Inst.setLoc(IDLoc); | |
1060 | Out.EmitInstruction(Inst, STI); | |
1061 | return false; | |
1062 | case Match_MissingFeature: | |
1063 | return Error(IDLoc, "instruction use requires an option to be enabled"); | |
1064 | case Match_MnemonicFail: | |
85aaf69f | 1065 | return Error(IDLoc, "unrecognized instruction mnemonic"); |
1a4d82fc JJ |
1066 | case Match_InvalidOperand: { |
1067 | SMLoc ErrorLoc = IDLoc; | |
1068 | if (ErrorInfo != ~0ULL) { | |
1069 | if (ErrorInfo >= Operands.size()) | |
1070 | return Error(IDLoc, "too few operands for instruction"); | |
1071 | ||
1072 | ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); | |
1073 | if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; | |
1074 | } | |
1075 | ||
1076 | return Error(ErrorLoc, "invalid operand for instruction"); | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | llvm_unreachable("Implement any new match types added!"); | |
1081 | } | |
1082 | ||
1083 | bool PPCAsmParser:: | |
1084 | MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { | |
1085 | if (Tok.is(AsmToken::Identifier)) { | |
1086 | StringRef Name = Tok.getString(); | |
1087 | ||
1088 | if (Name.equals_lower("lr")) { | |
1089 | RegNo = isPPC64()? PPC::LR8 : PPC::LR; | |
1090 | IntVal = 8; | |
1091 | return false; | |
1092 | } else if (Name.equals_lower("ctr")) { | |
1093 | RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; | |
1094 | IntVal = 9; | |
1095 | return false; | |
1096 | } else if (Name.equals_lower("vrsave")) { | |
1097 | RegNo = PPC::VRSAVE; | |
1098 | IntVal = 256; | |
1099 | return false; | |
1100 | } else if (Name.startswith_lower("r") && | |
1101 | !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { | |
1102 | RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; | |
1103 | return false; | |
1104 | } else if (Name.startswith_lower("f") && | |
1105 | !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { | |
1106 | RegNo = FRegs[IntVal]; | |
1107 | return false; | |
1108 | } else if (Name.startswith_lower("v") && | |
1109 | !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { | |
1110 | RegNo = VRegs[IntVal]; | |
1111 | return false; | |
1112 | } else if (Name.startswith_lower("cr") && | |
1113 | !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { | |
1114 | RegNo = CRRegs[IntVal]; | |
1115 | return false; | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | return true; | |
1120 | } | |
1121 | ||
1122 | bool PPCAsmParser:: | |
1123 | ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { | |
85aaf69f | 1124 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1125 | const AsmToken &Tok = Parser.getTok(); |
1126 | StartLoc = Tok.getLoc(); | |
1127 | EndLoc = Tok.getEndLoc(); | |
1128 | RegNo = 0; | |
1129 | int64_t IntVal; | |
1130 | ||
1131 | if (!MatchRegisterName(Tok, RegNo, IntVal)) { | |
1132 | Parser.Lex(); // Eat identifier token. | |
1133 | return false; | |
1134 | } | |
1135 | ||
1136 | return Error(StartLoc, "invalid register name"); | |
1137 | } | |
1138 | ||
1139 | /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan | |
1140 | /// the expression and check for VK_PPC_LO/HI/HA | |
1141 | /// symbol variants. If all symbols with modifier use the same | |
1142 | /// variant, return the corresponding PPCMCExpr::VariantKind, | |
1143 | /// and a modified expression using the default symbol variant. | |
1144 | /// Otherwise, return NULL. | |
1145 | const MCExpr *PPCAsmParser:: | |
1146 | ExtractModifierFromExpr(const MCExpr *E, | |
1147 | PPCMCExpr::VariantKind &Variant) { | |
1148 | MCContext &Context = getParser().getContext(); | |
1149 | Variant = PPCMCExpr::VK_PPC_None; | |
1150 | ||
1151 | switch (E->getKind()) { | |
1152 | case MCExpr::Target: | |
1153 | case MCExpr::Constant: | |
1154 | return nullptr; | |
1155 | ||
1156 | case MCExpr::SymbolRef: { | |
1157 | const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); | |
1158 | ||
1159 | switch (SRE->getKind()) { | |
1160 | case MCSymbolRefExpr::VK_PPC_LO: | |
1161 | Variant = PPCMCExpr::VK_PPC_LO; | |
1162 | break; | |
1163 | case MCSymbolRefExpr::VK_PPC_HI: | |
1164 | Variant = PPCMCExpr::VK_PPC_HI; | |
1165 | break; | |
1166 | case MCSymbolRefExpr::VK_PPC_HA: | |
1167 | Variant = PPCMCExpr::VK_PPC_HA; | |
1168 | break; | |
1169 | case MCSymbolRefExpr::VK_PPC_HIGHER: | |
1170 | Variant = PPCMCExpr::VK_PPC_HIGHER; | |
1171 | break; | |
1172 | case MCSymbolRefExpr::VK_PPC_HIGHERA: | |
1173 | Variant = PPCMCExpr::VK_PPC_HIGHERA; | |
1174 | break; | |
1175 | case MCSymbolRefExpr::VK_PPC_HIGHEST: | |
1176 | Variant = PPCMCExpr::VK_PPC_HIGHEST; | |
1177 | break; | |
1178 | case MCSymbolRefExpr::VK_PPC_HIGHESTA: | |
1179 | Variant = PPCMCExpr::VK_PPC_HIGHESTA; | |
1180 | break; | |
1181 | default: | |
1182 | return nullptr; | |
1183 | } | |
1184 | ||
1185 | return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context); | |
1186 | } | |
1187 | ||
1188 | case MCExpr::Unary: { | |
1189 | const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); | |
1190 | const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); | |
1191 | if (!Sub) | |
1192 | return nullptr; | |
1193 | return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); | |
1194 | } | |
1195 | ||
1196 | case MCExpr::Binary: { | |
1197 | const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); | |
1198 | PPCMCExpr::VariantKind LHSVariant, RHSVariant; | |
1199 | const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); | |
1200 | const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); | |
1201 | ||
1202 | if (!LHS && !RHS) | |
1203 | return nullptr; | |
1204 | ||
1205 | if (!LHS) LHS = BE->getLHS(); | |
1206 | if (!RHS) RHS = BE->getRHS(); | |
1207 | ||
1208 | if (LHSVariant == PPCMCExpr::VK_PPC_None) | |
1209 | Variant = RHSVariant; | |
1210 | else if (RHSVariant == PPCMCExpr::VK_PPC_None) | |
1211 | Variant = LHSVariant; | |
1212 | else if (LHSVariant == RHSVariant) | |
1213 | Variant = LHSVariant; | |
1214 | else | |
1215 | return nullptr; | |
1216 | ||
1217 | return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); | |
1218 | } | |
1219 | } | |
1220 | ||
1221 | llvm_unreachable("Invalid expression kind!"); | |
1222 | } | |
1223 | ||
1224 | /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace | |
1225 | /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having | |
1226 | /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. | |
1227 | /// FIXME: This is a hack. | |
1228 | const MCExpr *PPCAsmParser:: | |
1229 | FixupVariantKind(const MCExpr *E) { | |
1230 | MCContext &Context = getParser().getContext(); | |
1231 | ||
1232 | switch (E->getKind()) { | |
1233 | case MCExpr::Target: | |
1234 | case MCExpr::Constant: | |
1235 | return E; | |
1236 | ||
1237 | case MCExpr::SymbolRef: { | |
1238 | const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); | |
1239 | MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; | |
1240 | ||
1241 | switch (SRE->getKind()) { | |
1242 | case MCSymbolRefExpr::VK_TLSGD: | |
1243 | Variant = MCSymbolRefExpr::VK_PPC_TLSGD; | |
1244 | break; | |
1245 | case MCSymbolRefExpr::VK_TLSLD: | |
1246 | Variant = MCSymbolRefExpr::VK_PPC_TLSLD; | |
1247 | break; | |
1248 | default: | |
1249 | return E; | |
1250 | } | |
1251 | return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context); | |
1252 | } | |
1253 | ||
1254 | case MCExpr::Unary: { | |
1255 | const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); | |
1256 | const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); | |
1257 | if (Sub == UE->getSubExpr()) | |
1258 | return E; | |
1259 | return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); | |
1260 | } | |
1261 | ||
1262 | case MCExpr::Binary: { | |
1263 | const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); | |
1264 | const MCExpr *LHS = FixupVariantKind(BE->getLHS()); | |
1265 | const MCExpr *RHS = FixupVariantKind(BE->getRHS()); | |
1266 | if (LHS == BE->getLHS() && RHS == BE->getRHS()) | |
1267 | return E; | |
1268 | return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | llvm_unreachable("Invalid expression kind!"); | |
1273 | } | |
1274 | ||
1275 | /// ParseExpression. This differs from the default "parseExpression" in that | |
1276 | /// it handles modifiers. | |
1277 | bool PPCAsmParser:: | |
1278 | ParseExpression(const MCExpr *&EVal) { | |
1279 | ||
1280 | if (isDarwin()) | |
1281 | return ParseDarwinExpression(EVal); | |
1282 | ||
1283 | // (ELF Platforms) | |
1284 | // Handle \code @l/@ha \endcode | |
1285 | if (getParser().parseExpression(EVal)) | |
1286 | return true; | |
1287 | ||
1288 | EVal = FixupVariantKind(EVal); | |
1289 | ||
1290 | PPCMCExpr::VariantKind Variant; | |
1291 | const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); | |
1292 | if (E) | |
1293 | EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext()); | |
1294 | ||
1295 | return false; | |
1296 | } | |
1297 | ||
1298 | /// ParseDarwinExpression. (MachO Platforms) | |
1299 | /// This differs from the default "parseExpression" in that it handles detection | |
1300 | /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, | |
1301 | /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO | |
1302 | /// syntax form so it is done here. TODO: Determine if there is merit in arranging | |
1303 | /// for this to be done at a higher level. | |
1304 | bool PPCAsmParser:: | |
1305 | ParseDarwinExpression(const MCExpr *&EVal) { | |
85aaf69f | 1306 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1307 | PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; |
1308 | switch (getLexer().getKind()) { | |
1309 | default: | |
1310 | break; | |
1311 | case AsmToken::Identifier: | |
1312 | // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus | |
1313 | // something starting with any other char should be part of the | |
1314 | // asm syntax. If handwritten asm includes an identifier like lo16, | |
1315 | // then all bets are off - but no-one would do that, right? | |
1316 | StringRef poss = Parser.getTok().getString(); | |
1317 | if (poss.equals_lower("lo16")) { | |
1318 | Variant = PPCMCExpr::VK_PPC_LO; | |
1319 | } else if (poss.equals_lower("hi16")) { | |
1320 | Variant = PPCMCExpr::VK_PPC_HI; | |
1321 | } else if (poss.equals_lower("ha16")) { | |
1322 | Variant = PPCMCExpr::VK_PPC_HA; | |
1323 | } | |
1324 | if (Variant != PPCMCExpr::VK_PPC_None) { | |
1325 | Parser.Lex(); // Eat the xx16 | |
1326 | if (getLexer().isNot(AsmToken::LParen)) | |
1327 | return Error(Parser.getTok().getLoc(), "expected '('"); | |
1328 | Parser.Lex(); // Eat the '(' | |
1329 | } | |
1330 | break; | |
1331 | } | |
1332 | ||
1333 | if (getParser().parseExpression(EVal)) | |
1334 | return true; | |
1335 | ||
1336 | if (Variant != PPCMCExpr::VK_PPC_None) { | |
1337 | if (getLexer().isNot(AsmToken::RParen)) | |
1338 | return Error(Parser.getTok().getLoc(), "expected ')'"); | |
1339 | Parser.Lex(); // Eat the ')' | |
1340 | EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext()); | |
1341 | } | |
1342 | return false; | |
1343 | } | |
1344 | ||
1345 | /// ParseOperand | |
1346 | /// This handles registers in the form 'NN', '%rNN' for ELF platforms and | |
1347 | /// rNN for MachO. | |
1348 | bool PPCAsmParser::ParseOperand(OperandVector &Operands) { | |
85aaf69f | 1349 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1350 | SMLoc S = Parser.getTok().getLoc(); |
1351 | SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); | |
1352 | const MCExpr *EVal; | |
1353 | ||
1354 | // Attempt to parse the next token as an immediate | |
1355 | switch (getLexer().getKind()) { | |
1356 | // Special handling for register names. These are interpreted | |
1357 | // as immediates corresponding to the register number. | |
1358 | case AsmToken::Percent: | |
1359 | Parser.Lex(); // Eat the '%'. | |
1360 | unsigned RegNo; | |
1361 | int64_t IntVal; | |
1362 | if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { | |
1363 | Parser.Lex(); // Eat the identifier token. | |
1364 | Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); | |
1365 | return false; | |
1366 | } | |
1367 | return Error(S, "invalid register name"); | |
1368 | ||
1369 | case AsmToken::Identifier: | |
1370 | // Note that non-register-name identifiers from the compiler will begin | |
1371 | // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include | |
1372 | // identifiers like r31foo - so we fall through in the event that parsing | |
1373 | // a register name fails. | |
1374 | if (isDarwin()) { | |
1375 | unsigned RegNo; | |
1376 | int64_t IntVal; | |
1377 | if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { | |
1378 | Parser.Lex(); // Eat the identifier token. | |
1379 | Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); | |
1380 | return false; | |
1381 | } | |
1382 | } | |
1383 | // Fall-through to process non-register-name identifiers as expression. | |
1384 | // All other expressions | |
1385 | case AsmToken::LParen: | |
1386 | case AsmToken::Plus: | |
1387 | case AsmToken::Minus: | |
1388 | case AsmToken::Integer: | |
1389 | case AsmToken::Dot: | |
1390 | case AsmToken::Dollar: | |
1391 | case AsmToken::Exclaim: | |
1392 | case AsmToken::Tilde: | |
1393 | if (!ParseExpression(EVal)) | |
1394 | break; | |
1395 | /* fall through */ | |
1396 | default: | |
1397 | return Error(S, "unknown operand"); | |
1398 | } | |
1399 | ||
1400 | // Push the parsed operand into the list of operands | |
1401 | Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); | |
1402 | ||
1403 | // Check whether this is a TLS call expression | |
1404 | bool TLSCall = false; | |
1405 | if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) | |
1406 | TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; | |
1407 | ||
1408 | if (TLSCall && getLexer().is(AsmToken::LParen)) { | |
1409 | const MCExpr *TLSSym; | |
1410 | ||
1411 | Parser.Lex(); // Eat the '('. | |
1412 | S = Parser.getTok().getLoc(); | |
1413 | if (ParseExpression(TLSSym)) | |
1414 | return Error(S, "invalid TLS call expression"); | |
1415 | if (getLexer().isNot(AsmToken::RParen)) | |
1416 | return Error(Parser.getTok().getLoc(), "missing ')'"); | |
1417 | E = Parser.getTok().getLoc(); | |
1418 | Parser.Lex(); // Eat the ')'. | |
1419 | ||
1420 | Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); | |
1421 | } | |
1422 | ||
1423 | // Otherwise, check for D-form memory operands | |
1424 | if (!TLSCall && getLexer().is(AsmToken::LParen)) { | |
1425 | Parser.Lex(); // Eat the '('. | |
1426 | S = Parser.getTok().getLoc(); | |
1427 | ||
1428 | int64_t IntVal; | |
1429 | switch (getLexer().getKind()) { | |
1430 | case AsmToken::Percent: | |
1431 | Parser.Lex(); // Eat the '%'. | |
1432 | unsigned RegNo; | |
1433 | if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) | |
1434 | return Error(S, "invalid register name"); | |
1435 | Parser.Lex(); // Eat the identifier token. | |
1436 | break; | |
1437 | ||
1438 | case AsmToken::Integer: | |
1439 | if (!isDarwin()) { | |
1440 | if (getParser().parseAbsoluteExpression(IntVal) || | |
1441 | IntVal < 0 || IntVal > 31) | |
1442 | return Error(S, "invalid register number"); | |
1443 | } else { | |
1444 | return Error(S, "unexpected integer value"); | |
1445 | } | |
1446 | break; | |
1447 | ||
1448 | case AsmToken::Identifier: | |
1449 | if (isDarwin()) { | |
1450 | unsigned RegNo; | |
1451 | if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { | |
1452 | Parser.Lex(); // Eat the identifier token. | |
1453 | break; | |
1454 | } | |
1455 | } | |
1456 | // Fall-through.. | |
1457 | ||
1458 | default: | |
1459 | return Error(S, "invalid memory operand"); | |
1460 | } | |
1461 | ||
1462 | if (getLexer().isNot(AsmToken::RParen)) | |
1463 | return Error(Parser.getTok().getLoc(), "missing ')'"); | |
1464 | E = Parser.getTok().getLoc(); | |
1465 | Parser.Lex(); // Eat the ')'. | |
1466 | ||
1467 | Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); | |
1468 | } | |
1469 | ||
1470 | return false; | |
1471 | } | |
1472 | ||
1473 | /// Parse an instruction mnemonic followed by its operands. | |
1474 | bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, | |
1475 | SMLoc NameLoc, OperandVector &Operands) { | |
1476 | // The first operand is the token for the instruction name. | |
1477 | // If the next character is a '+' or '-', we need to add it to the | |
1478 | // instruction name, to match what TableGen is doing. | |
1479 | std::string NewOpcode; | |
1480 | if (getLexer().is(AsmToken::Plus)) { | |
1481 | getLexer().Lex(); | |
1482 | NewOpcode = Name; | |
1483 | NewOpcode += '+'; | |
1484 | Name = NewOpcode; | |
1485 | } | |
1486 | if (getLexer().is(AsmToken::Minus)) { | |
1487 | getLexer().Lex(); | |
1488 | NewOpcode = Name; | |
1489 | NewOpcode += '-'; | |
1490 | Name = NewOpcode; | |
1491 | } | |
1492 | // If the instruction ends in a '.', we need to create a separate | |
1493 | // token for it, to match what TableGen is doing. | |
1494 | size_t Dot = Name.find('.'); | |
1495 | StringRef Mnemonic = Name.slice(0, Dot); | |
1496 | if (!NewOpcode.empty()) // Underlying memory for Name is volatile. | |
1497 | Operands.push_back( | |
1498 | PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); | |
1499 | else | |
1500 | Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); | |
1501 | if (Dot != StringRef::npos) { | |
1502 | SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); | |
1503 | StringRef DotStr = Name.slice(Dot, StringRef::npos); | |
1504 | if (!NewOpcode.empty()) // Underlying memory for Name is volatile. | |
1505 | Operands.push_back( | |
1506 | PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); | |
1507 | else | |
1508 | Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); | |
1509 | } | |
1510 | ||
1511 | // If there are no more operands then finish | |
1512 | if (getLexer().is(AsmToken::EndOfStatement)) | |
1513 | return false; | |
1514 | ||
1515 | // Parse the first operand | |
1516 | if (ParseOperand(Operands)) | |
1517 | return true; | |
1518 | ||
1519 | while (getLexer().isNot(AsmToken::EndOfStatement) && | |
1520 | getLexer().is(AsmToken::Comma)) { | |
1521 | // Consume the comma token | |
1522 | getLexer().Lex(); | |
1523 | ||
1524 | // Parse the next operand | |
1525 | if (ParseOperand(Operands)) | |
1526 | return true; | |
1527 | } | |
1528 | ||
1529 | return false; | |
1530 | } | |
1531 | ||
1532 | /// ParseDirective parses the PPC specific directives | |
1533 | bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { | |
1534 | StringRef IDVal = DirectiveID.getIdentifier(); | |
1535 | if (!isDarwin()) { | |
1536 | if (IDVal == ".word") | |
1537 | return ParseDirectiveWord(2, DirectiveID.getLoc()); | |
1538 | if (IDVal == ".llong") | |
1539 | return ParseDirectiveWord(8, DirectiveID.getLoc()); | |
1540 | if (IDVal == ".tc") | |
1541 | return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); | |
1542 | if (IDVal == ".machine") | |
1543 | return ParseDirectiveMachine(DirectiveID.getLoc()); | |
1544 | if (IDVal == ".abiversion") | |
1545 | return ParseDirectiveAbiVersion(DirectiveID.getLoc()); | |
1546 | if (IDVal == ".localentry") | |
1547 | return ParseDirectiveLocalEntry(DirectiveID.getLoc()); | |
1548 | } else { | |
1549 | if (IDVal == ".machine") | |
1550 | return ParseDarwinDirectiveMachine(DirectiveID.getLoc()); | |
1551 | } | |
1552 | return true; | |
1553 | } | |
1554 | ||
1555 | /// ParseDirectiveWord | |
1556 | /// ::= .word [ expression (, expression)* ] | |
1557 | bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { | |
85aaf69f | 1558 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1559 | if (getLexer().isNot(AsmToken::EndOfStatement)) { |
1560 | for (;;) { | |
1561 | const MCExpr *Value; | |
1562 | if (getParser().parseExpression(Value)) | |
1563 | return false; | |
1564 | ||
1565 | getParser().getStreamer().EmitValue(Value, Size); | |
1566 | ||
1567 | if (getLexer().is(AsmToken::EndOfStatement)) | |
1568 | break; | |
1569 | ||
1570 | if (getLexer().isNot(AsmToken::Comma)) | |
1571 | return Error(L, "unexpected token in directive"); | |
1572 | Parser.Lex(); | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | Parser.Lex(); | |
1577 | return false; | |
1578 | } | |
1579 | ||
1580 | /// ParseDirectiveTC | |
1581 | /// ::= .tc [ symbol (, expression)* ] | |
1582 | bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { | |
85aaf69f | 1583 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1584 | // Skip TC symbol, which is only used with XCOFF. |
1585 | while (getLexer().isNot(AsmToken::EndOfStatement) | |
1586 | && getLexer().isNot(AsmToken::Comma)) | |
1587 | Parser.Lex(); | |
1588 | if (getLexer().isNot(AsmToken::Comma)) { | |
1589 | Error(L, "unexpected token in directive"); | |
1590 | return false; | |
1591 | } | |
1592 | Parser.Lex(); | |
1593 | ||
1594 | // Align to word size. | |
1595 | getParser().getStreamer().EmitValueToAlignment(Size); | |
1596 | ||
1597 | // Emit expressions. | |
1598 | return ParseDirectiveWord(Size, L); | |
1599 | } | |
1600 | ||
1601 | /// ParseDirectiveMachine (ELF platforms) | |
1602 | /// ::= .machine [ cpu | "push" | "pop" ] | |
1603 | bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { | |
85aaf69f | 1604 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1605 | if (getLexer().isNot(AsmToken::Identifier) && |
1606 | getLexer().isNot(AsmToken::String)) { | |
1607 | Error(L, "unexpected token in directive"); | |
1608 | return false; | |
1609 | } | |
1610 | ||
1611 | StringRef CPU = Parser.getTok().getIdentifier(); | |
1612 | Parser.Lex(); | |
1613 | ||
1614 | // FIXME: Right now, the parser always allows any available | |
1615 | // instruction, so the .machine directive is not useful. | |
1616 | // Implement ".machine any" (by doing nothing) for the benefit | |
1617 | // of existing assembler code. Likewise, we can then implement | |
1618 | // ".machine push" and ".machine pop" as no-op. | |
1619 | if (CPU != "any" && CPU != "push" && CPU != "pop") { | |
1620 | Error(L, "unrecognized machine type"); | |
1621 | return false; | |
1622 | } | |
1623 | ||
1624 | if (getLexer().isNot(AsmToken::EndOfStatement)) { | |
1625 | Error(L, "unexpected token in directive"); | |
1626 | return false; | |
1627 | } | |
1628 | PPCTargetStreamer &TStreamer = | |
1629 | *static_cast<PPCTargetStreamer *>( | |
1630 | getParser().getStreamer().getTargetStreamer()); | |
1631 | TStreamer.emitMachine(CPU); | |
1632 | ||
1633 | return false; | |
1634 | } | |
1635 | ||
1636 | /// ParseDarwinDirectiveMachine (Mach-o platforms) | |
1637 | /// ::= .machine cpu-identifier | |
1638 | bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { | |
85aaf69f | 1639 | MCAsmParser &Parser = getParser(); |
1a4d82fc JJ |
1640 | if (getLexer().isNot(AsmToken::Identifier) && |
1641 | getLexer().isNot(AsmToken::String)) { | |
1642 | Error(L, "unexpected token in directive"); | |
1643 | return false; | |
1644 | } | |
1645 | ||
1646 | StringRef CPU = Parser.getTok().getIdentifier(); | |
1647 | Parser.Lex(); | |
1648 | ||
1649 | // FIXME: this is only the 'default' set of cpu variants. | |
1650 | // However we don't act on this information at present, this is simply | |
1651 | // allowing parsing to proceed with minimal sanity checking. | |
1652 | if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") { | |
1653 | Error(L, "unrecognized cpu type"); | |
1654 | return false; | |
1655 | } | |
1656 | ||
1657 | if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) { | |
1658 | Error(L, "wrong cpu type specified for 64bit"); | |
1659 | return false; | |
1660 | } | |
1661 | if (!isPPC64() && CPU == "ppc64") { | |
1662 | Error(L, "wrong cpu type specified for 32bit"); | |
1663 | return false; | |
1664 | } | |
1665 | ||
1666 | if (getLexer().isNot(AsmToken::EndOfStatement)) { | |
1667 | Error(L, "unexpected token in directive"); | |
1668 | return false; | |
1669 | } | |
1670 | ||
1671 | return false; | |
1672 | } | |
1673 | ||
1674 | /// ParseDirectiveAbiVersion | |
1675 | /// ::= .abiversion constant-expression | |
1676 | bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { | |
1677 | int64_t AbiVersion; | |
1678 | if (getParser().parseAbsoluteExpression(AbiVersion)){ | |
1679 | Error(L, "expected constant expression"); | |
1680 | return false; | |
1681 | } | |
1682 | if (getLexer().isNot(AsmToken::EndOfStatement)) { | |
1683 | Error(L, "unexpected token in directive"); | |
1684 | return false; | |
1685 | } | |
1686 | ||
1687 | PPCTargetStreamer &TStreamer = | |
1688 | *static_cast<PPCTargetStreamer *>( | |
1689 | getParser().getStreamer().getTargetStreamer()); | |
1690 | TStreamer.emitAbiVersion(AbiVersion); | |
1691 | ||
1692 | return false; | |
1693 | } | |
1694 | ||
1695 | /// ParseDirectiveLocalEntry | |
1696 | /// ::= .localentry symbol, expression | |
1697 | bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { | |
1698 | StringRef Name; | |
1699 | if (getParser().parseIdentifier(Name)) { | |
1700 | Error(L, "expected identifier in directive"); | |
1701 | return false; | |
1702 | } | |
1703 | MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); | |
1704 | ||
1705 | if (getLexer().isNot(AsmToken::Comma)) { | |
1706 | Error(L, "unexpected token in directive"); | |
1707 | return false; | |
1708 | } | |
1709 | Lex(); | |
1710 | ||
1711 | const MCExpr *Expr; | |
1712 | if (getParser().parseExpression(Expr)) { | |
1713 | Error(L, "expected expression"); | |
1714 | return false; | |
1715 | } | |
1716 | ||
1717 | if (getLexer().isNot(AsmToken::EndOfStatement)) { | |
1718 | Error(L, "unexpected token in directive"); | |
1719 | return false; | |
1720 | } | |
1721 | ||
1722 | PPCTargetStreamer &TStreamer = | |
1723 | *static_cast<PPCTargetStreamer *>( | |
1724 | getParser().getStreamer().getTargetStreamer()); | |
1725 | TStreamer.emitLocalEntry(Sym, Expr); | |
1726 | ||
1727 | return false; | |
1728 | } | |
1729 | ||
1730 | ||
1731 | ||
1732 | /// Force static initialization. | |
1733 | extern "C" void LLVMInitializePowerPCAsmParser() { | |
1734 | RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); | |
1735 | RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); | |
1736 | RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget); | |
1737 | } | |
1738 | ||
1739 | #define GET_REGISTER_MATCHER | |
1740 | #define GET_MATCHER_IMPLEMENTATION | |
1741 | #include "PPCGenAsmMatcher.inc" | |
1742 | ||
1743 | // Define this matcher function after the auto-generated include so we | |
1744 | // have the match class enum definitions. | |
1745 | unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, | |
1746 | unsigned Kind) { | |
1747 | // If the kind is a token for a literal immediate, check if our asm | |
1748 | // operand matches. This is for InstAliases which have a fixed-value | |
1749 | // immediate in the syntax. | |
1750 | int64_t ImmVal; | |
1751 | switch (Kind) { | |
1752 | case MCK_0: ImmVal = 0; break; | |
1753 | case MCK_1: ImmVal = 1; break; | |
1754 | case MCK_2: ImmVal = 2; break; | |
1755 | case MCK_3: ImmVal = 3; break; | |
1756 | case MCK_4: ImmVal = 4; break; | |
1757 | case MCK_5: ImmVal = 5; break; | |
1758 | case MCK_6: ImmVal = 6; break; | |
1759 | case MCK_7: ImmVal = 7; break; | |
1760 | default: return Match_InvalidOperand; | |
1761 | } | |
1762 | ||
1763 | PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); | |
1764 | if (Op.isImm() && Op.getImm() == ImmVal) | |
1765 | return Match_Success; | |
1766 | ||
1767 | return Match_InvalidOperand; | |
1768 | } | |
1769 | ||
1770 | const MCExpr * | |
1771 | PPCAsmParser::applyModifierToExpr(const MCExpr *E, | |
1772 | MCSymbolRefExpr::VariantKind Variant, | |
1773 | MCContext &Ctx) { | |
1774 | switch (Variant) { | |
1775 | case MCSymbolRefExpr::VK_PPC_LO: | |
1776 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx); | |
1777 | case MCSymbolRefExpr::VK_PPC_HI: | |
1778 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx); | |
1779 | case MCSymbolRefExpr::VK_PPC_HA: | |
1780 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx); | |
1781 | case MCSymbolRefExpr::VK_PPC_HIGHER: | |
1782 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx); | |
1783 | case MCSymbolRefExpr::VK_PPC_HIGHERA: | |
1784 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx); | |
1785 | case MCSymbolRefExpr::VK_PPC_HIGHEST: | |
1786 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx); | |
1787 | case MCSymbolRefExpr::VK_PPC_HIGHESTA: | |
1788 | return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx); | |
1789 | default: | |
1790 | return nullptr; | |
1791 | } | |
1792 | } |