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970d7e83 LB |
1 | //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | /// \file | |
11 | /// \brief R600 implementation of the TargetRegisterInfo class. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | #include "R600RegisterInfo.h" | |
16 | #include "AMDGPUTargetMachine.h" | |
17 | #include "R600Defines.h" | |
18 | #include "R600InstrInfo.h" | |
19 | #include "R600MachineFunctionInfo.h" | |
20 | ||
21 | using namespace llvm; | |
22 | ||
1a4d82fc JJ |
23 | R600RegisterInfo::R600RegisterInfo(const AMDGPUSubtarget &st) |
24 | : AMDGPURegisterInfo(st) | |
25 | { RCW.RegWeight = 0; RCW.WeightLimit = 0;} | |
970d7e83 LB |
26 | |
27 | BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { | |
28 | BitVector Reserved(getNumRegs()); | |
29 | ||
1a4d82fc JJ |
30 | const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(ST.getInstrInfo()); |
31 | ||
970d7e83 LB |
32 | Reserved.set(AMDGPU::ZERO); |
33 | Reserved.set(AMDGPU::HALF); | |
34 | Reserved.set(AMDGPU::ONE); | |
35 | Reserved.set(AMDGPU::ONE_INT); | |
36 | Reserved.set(AMDGPU::NEG_HALF); | |
37 | Reserved.set(AMDGPU::NEG_ONE); | |
38 | Reserved.set(AMDGPU::PV_X); | |
39 | Reserved.set(AMDGPU::ALU_LITERAL_X); | |
40 | Reserved.set(AMDGPU::ALU_CONST); | |
41 | Reserved.set(AMDGPU::PREDICATE_BIT); | |
42 | Reserved.set(AMDGPU::PRED_SEL_OFF); | |
43 | Reserved.set(AMDGPU::PRED_SEL_ZERO); | |
44 | Reserved.set(AMDGPU::PRED_SEL_ONE); | |
1a4d82fc | 45 | Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); |
970d7e83 LB |
46 | |
47 | for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), | |
48 | E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { | |
49 | Reserved.set(*I); | |
50 | } | |
51 | ||
1a4d82fc | 52 | TII->reserveIndirectRegisters(Reserved, MF); |
970d7e83 | 53 | |
970d7e83 LB |
54 | return Reserved; |
55 | } | |
56 | ||
970d7e83 LB |
57 | unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { |
58 | return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; | |
59 | } | |
60 | ||
1a4d82fc JJ |
61 | unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { |
62 | return GET_REG_INDEX(getEncodingValue(Reg)); | |
63 | } | |
64 | ||
970d7e83 LB |
65 | const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( |
66 | MVT VT) const { | |
67 | switch(VT.SimpleTy) { | |
68 | default: | |
69 | case MVT::i32: return &AMDGPU::R600_TReg32RegClass; | |
70 | } | |
71 | } | |
72 | ||
1a4d82fc JJ |
73 | const RegClassWeight &R600RegisterInfo::getRegClassWeight( |
74 | const TargetRegisterClass *RC) const { | |
75 | return RCW; | |
970d7e83 LB |
76 | } |
77 | ||
1a4d82fc JJ |
78 | bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { |
79 | assert(!TargetRegisterInfo::isVirtualRegister(Reg)); | |
80 | ||
81 | switch (Reg) { | |
82 | case AMDGPU::OQAP: | |
83 | case AMDGPU::OQBP: | |
84 | case AMDGPU::AR_X: | |
85 | return false; | |
86 | default: | |
87 | return true; | |
88 | } | |
89 | } |