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1 | //===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | /// \file | |
9 | //===----------------------------------------------------------------------===// | |
10 | ||
11 | ||
12 | #include "SIMachineFunctionInfo.h" | |
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13 | #include "AMDGPUSubtarget.h" |
14 | #include "SIInstrInfo.h" | |
15 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |
16 | #include "llvm/CodeGen/MachineFrameInfo.h" | |
17 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |
970d7e83 | 18 | #include "llvm/IR/Function.h" |
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19 | #include "llvm/IR/LLVMContext.h" |
20 | ||
21 | #define MAX_LANES 64 | |
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22 | |
23 | using namespace llvm; | |
24 | ||
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25 | |
26 | // Pin the vtable to this file. | |
27 | void SIMachineFunctionInfo::anchor() {} | |
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28 | |
29 | SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) | |
1a4d82fc JJ |
30 | : AMDGPUMachineFunction(MF), |
31 | TIDReg(AMDGPU::NoRegister), | |
85aaf69f | 32 | HasSpilledVGPRs(false), |
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33 | PSInputAddr(0), |
34 | NumUserSGPRs(0), | |
35 | LDSWaveSpillSize(0) { } | |
36 | ||
37 | SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( | |
38 | MachineFunction *MF, | |
39 | unsigned FrameIndex, | |
40 | unsigned SubIdx) { | |
41 | const MachineFrameInfo *FrameInfo = MF->getFrameInfo(); | |
42 | const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>( | |
43 | MF->getTarget().getSubtarget<AMDGPUSubtarget>().getRegisterInfo()); | |
44 | MachineRegisterInfo &MRI = MF->getRegInfo(); | |
45 | int64_t Offset = FrameInfo->getObjectOffset(FrameIndex); | |
46 | Offset += SubIdx * 4; | |
47 | ||
48 | unsigned LaneVGPRIdx = Offset / (64 * 4); | |
49 | unsigned Lane = (Offset / 4) % 64; | |
50 | ||
51 | struct SpilledReg Spill; | |
52 | ||
53 | if (!LaneVGPRs.count(LaneVGPRIdx)) { | |
85aaf69f | 54 | unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass); |
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55 | LaneVGPRs[LaneVGPRIdx] = LaneVGPR; |
56 | MRI.setPhysRegUsed(LaneVGPR); | |
57 | ||
58 | // Add this register as live-in to all blocks to avoid machine verifer | |
59 | // complaining about use of an undefined physical register. | |
60 | for (MachineFunction::iterator BI = MF->begin(), BE = MF->end(); | |
61 | BI != BE; ++BI) { | |
62 | BI->addLiveIn(LaneVGPR); | |
63 | } | |
970d7e83 | 64 | } |
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65 | |
66 | Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; | |
67 | Spill.Lane = Lane; | |
68 | return Spill; | |
69 | } | |
70 | ||
71 | unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize( | |
72 | const MachineFunction &MF) const { | |
73 | const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget<AMDGPUSubtarget>(); | |
74 | // FIXME: We should get this information from kernel attributes if it | |
75 | // is available. | |
76 | return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize(); | |
970d7e83 | 77 | } |