[rustc.git] / src / llvm / lib / Target / Sparc / SparcFrameLowering.cpp

//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Sparc implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//

#include "SparcFrameLowering.h"
#include "SparcInstrInfo.h"
#include "SparcMachineFunctionInfo.h"
#include "SparcSubtarget.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetOptions.h"

using namespace llvm;

static cl::opt<bool>
DisableLeafProc("disable-sparc-leaf-proc",
                cl::init(false),
                cl::desc("Disable Sparc leaf procedure optimization."),
                cl::Hidden);

SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
                          ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}

void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
                                          MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MBBI,
                                          int NumBytes,
                                          unsigned ADDrr,
                                          unsigned ADDri) const {

  DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
  const SparcInstrInfo &TII =
      *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());

  if (NumBytes >= -4096 && NumBytes < 4096) {
    BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
      .addReg(SP::O6).addImm(NumBytes);
    return;
  }

  // Emit this the hard way.  This clobbers G1 which we always know is
  // available here.
  if (NumBytes >= 0) {
    // Emit nonnegative numbers with sethi + or.
    // sethi %hi(NumBytes), %g1
    // or %g1, %lo(NumBytes), %g1
    // add %sp, %g1, %sp
    BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
      .addImm(HI22(NumBytes));
    BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
      .addReg(SP::G1).addImm(LO10(NumBytes));
    BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
      .addReg(SP::O6).addReg(SP::G1);
    return ;
  }

  // Emit negative numbers with sethi + xor.
  // sethi %hix(NumBytes), %g1
  // xor %g1, %lox(NumBytes), %g1
  // add %sp, %g1, %sp
  BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
    .addImm(HIX22(NumBytes));
  BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
    .addReg(SP::G1).addImm(LOX10(NumBytes));
  BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
    .addReg(SP::O6).addReg(SP::G1);
}

void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();

  MachineBasicBlock &MBB = MF.front();
  MachineFrameInfo *MFI = MF.getFrameInfo();
  const SparcInstrInfo &TII =
      *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
  MachineBasicBlock::iterator MBBI = MBB.begin();
  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

  // Get the number of bytes to allocate from the FrameInfo
  int NumBytes = (int) MFI->getStackSize();

  unsigned SAVEri = SP::SAVEri;
  unsigned SAVErr = SP::SAVErr;
  if (FuncInfo->isLeafProc()) {
    if (NumBytes == 0)
      return;
    SAVEri = SP::ADDri;
    SAVErr = SP::ADDrr;
  }
  NumBytes =
      -MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
          NumBytes);
  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);

  MachineModuleInfo &MMI = MF.getMMI();
  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
  unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);

  // Emit ".cfi_def_cfa_register 30".
  unsigned CFIIndex =
      MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
      .addCFIIndex(CFIIndex);

  // Emit ".cfi_window_save".
  CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
      .addCFIIndex(CFIIndex);

  unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
  unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
  // Emit ".cfi_register 15, 31".
  CFIIndex = MMI.addFrameInst(
      MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
      .addCFIIndex(CFIIndex);
}

void SparcFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator I) const {
  if (!hasReservedCallFrame(MF)) {
    MachineInstr &MI = *I;
    int Size = MI.getOperand(0).getImm();
    if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
      Size = -Size;

    if (Size)
      emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
  }
  MBB.erase(I);
}


void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
                                  MachineBasicBlock &MBB) const {
  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
  const SparcInstrInfo &TII =
      *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
  DebugLoc dl = MBBI->getDebugLoc();
  assert(MBBI->getOpcode() == SP::RETL &&
         "Can only put epilog before 'retl' instruction!");
  if (!FuncInfo->isLeafProc()) {
    BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
      .addReg(SP::G0);
    return;
  }
  MachineFrameInfo *MFI = MF.getFrameInfo();

  int NumBytes = (int) MFI->getStackSize();
  if (NumBytes == 0)
    return;

  NumBytes = MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
      NumBytes);
  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
}

bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
  // Reserve call frame if there are no variable sized objects on the stack.
  return !MF.getFrameInfo()->hasVarSizedObjects();
}

// hasFP - Return true if the specified function should have a dedicated frame
// pointer register.  This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
  const MachineFrameInfo *MFI = MF.getFrameInfo();
  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
    MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
}


static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
{

  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
    if (MRI->isPhysRegUsed(reg))
      return false;

  for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
    if (MRI->isPhysRegUsed(reg))
      return false;

  return true;
}

bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
{

  MachineRegisterInfo &MRI = MF.getRegInfo();
  MachineFrameInfo    *MFI = MF.getFrameInfo();

  return !(MFI->hasCalls()              // has calls
           || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
           || MRI.isPhysRegUsed(SP::O6) // %SP is used
           || hasFP(MF));               // need %FP
}

void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {

  MachineRegisterInfo &MRI = MF.getRegInfo();

  // Remap %i[0-7] to %o[0-7].
  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
    if (!MRI.isPhysRegUsed(reg))
      continue;
    unsigned mapped_reg = (reg - SP::I0 + SP::O0);
    assert(!MRI.isPhysRegUsed(mapped_reg));

    // Replace I register with O register.
    MRI.replaceRegWith(reg, mapped_reg);

    // Mark the reg unused.
    MRI.setPhysRegUnused(reg);
  }

  // Rewrite MBB's Live-ins.
  for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
       MBB != E; ++MBB) {
    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
      if (!MBB->isLiveIn(reg))
        continue;
      MBB->removeLiveIn(reg);
      MBB->addLiveIn(reg - SP::I0 + SP::O0);
    }
  }

  assert(verifyLeafProcRegUse(&MRI));
#ifdef XDEBUG
  MF.verify(0, "After LeafProc Remapping");
#endif
}

void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
                  (MachineFunction &MF, RegScavenger *RS) const {

  if (!DisableLeafProc && isLeafProc(MF)) {
    SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
    MFI->setLeafProc(true);

    remapRegsForLeafProc(MF);
  }

}
Commit	Line	Data
223e47cc LB	1	//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
	2	//
	3	// The LLVM Compiler Infrastructure
	4	//
	5	// This file is distributed under the University of Illinois Open Source
	6	// License. See LICENSE.TXT for details.
	7	//
	8	//===----------------------------------------------------------------------===//
	9	//
	10	// This file contains the Sparc implementation of TargetFrameLowering class.
	11	//
	12	//===----------------------------------------------------------------------===//
	13
	14	#include "SparcFrameLowering.h"
	15	#include "SparcInstrInfo.h"
	16	#include "SparcMachineFunctionInfo.h"
1a4d82fc	17	#include "SparcSubtarget.h"
223e47cc LB	18	#include "llvm/CodeGen/MachineFrameInfo.h"
	19	#include "llvm/CodeGen/MachineFunction.h"
	20	#include "llvm/CodeGen/MachineInstrBuilder.h"
	21	#include "llvm/CodeGen/MachineModuleInfo.h"
	22	#include "llvm/CodeGen/MachineRegisterInfo.h"
970d7e83 LB	23	#include "llvm/IR/DataLayout.h"
970d7e83 LB	24	#include "llvm/IR/Function.h"
223e47cc	25	#include "llvm/Support/CommandLine.h"
970d7e83	26	#include "llvm/Target/TargetOptions.h"
223e47cc LB	27
	28	using namespace llvm;
	29
1a4d82fc JJ	30	static cl::opt<bool>
	31	DisableLeafProc("disable-sparc-leaf-proc",
	32	cl::init(false),
	33	cl::desc("Disable Sparc leaf procedure optimization."),
	34	cl::Hidden);
	35
	36	SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
	37	: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
	38	ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
	39
	40	void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
	41	MachineBasicBlock &MBB,
	42	MachineBasicBlock::iterator MBBI,
	43	int NumBytes,
	44	unsigned ADDrr,
	45	unsigned ADDri) const {
	46
	47	DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
	48	const SparcInstrInfo &TII =
	49	static_cast<const SparcInstrInfo >(MF.getSubtarget().getInstrInfo());
	50
	51	if (NumBytes >= -4096 && NumBytes < 4096) {
	52	BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
	53	.addReg(SP::O6).addImm(NumBytes);
	54	return;
	55	}
	56
	57	// Emit this the hard way. This clobbers G1 which we always know is
	58	// available here.
	59	if (NumBytes >= 0) {
	60	// Emit nonnegative numbers with sethi + or.
	61	// sethi %hi(NumBytes), %g1
	62	// or %g1, %lo(NumBytes), %g1
	63	// add %sp, %g1, %sp
	64	BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
	65	.addImm(HI22(NumBytes));
	66	BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
	67	.addReg(SP::G1).addImm(LO10(NumBytes));
	68	BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
	69	.addReg(SP::O6).addReg(SP::G1);
	70	return ;
	71	}
	72
	73	// Emit negative numbers with sethi + xor.
	74	// sethi %hix(NumBytes), %g1
	75	// xor %g1, %lox(NumBytes), %g1
	76	// add %sp, %g1, %sp
	77	BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
	78	.addImm(HIX22(NumBytes));
	79	BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
	80	.addReg(SP::G1).addImm(LOX10(NumBytes));
	81	BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
	82	.addReg(SP::O6).addReg(SP::G1);
	83	}
	84
223e47cc	85	void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
1a4d82fc JJ	86	SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1a4d82fc JJ	87
223e47cc LB	88	MachineBasicBlock &MBB = MF.front();
	89	MachineFrameInfo *MFI = MF.getFrameInfo();
	90	const SparcInstrInfo &TII =
1a4d82fc	91	static_cast<const SparcInstrInfo >(MF.getSubtarget().getInstrInfo());
223e47cc LB	92	MachineBasicBlock::iterator MBBI = MBB.begin();
	93	DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
	94
	95	// Get the number of bytes to allocate from the FrameInfo
	96	int NumBytes = (int) MFI->getStackSize();
	97
1a4d82fc JJ	98	unsigned SAVEri = SP::SAVEri;
	99	unsigned SAVErr = SP::SAVErr;
	100	if (FuncInfo->isLeafProc()) {
	101	if (NumBytes == 0)
	102	return;
	103	SAVEri = SP::ADDri;
	104	SAVErr = SP::ADDrr;
223e47cc	105	}
1a4d82fc JJ	106	NumBytes =
	107	-MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
	108	NumBytes);
	109	emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
	110
	111	MachineModuleInfo &MMI = MF.getMMI();
	112	const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
	113	unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
	114
	115	// Emit ".cfi_def_cfa_register 30".
	116	unsigned CFIIndex =
	117	MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
	118	BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
	119	.addCFIIndex(CFIIndex);
	120
	121	// Emit ".cfi_window_save".
	122	CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
	123	BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
	124	.addCFIIndex(CFIIndex);
	125
	126	unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
	127	unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
	128	// Emit ".cfi_register 15, 31".
	129	CFIIndex = MMI.addFrameInst(
	130	MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
	131	BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
	132	.addCFIIndex(CFIIndex);
223e47cc LB	133	}
223e47cc LB	134
970d7e83 LB	135	void SparcFrameLowering::
	136	eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
	137	MachineBasicBlock::iterator I) const {
1a4d82fc JJ	138	if (!hasReservedCallFrame(MF)) {
	139	MachineInstr &MI = *I;
	140	int Size = MI.getOperand(0).getImm();
	141	if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
	142	Size = -Size;
	143
	144	if (Size)
	145	emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
	146	}
970d7e83 LB	147	MBB.erase(I);
	148	}
	149
	150
223e47cc LB	151	void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
223e47cc LB	152	MachineBasicBlock &MBB) const {
1a4d82fc	153	SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
223e47cc LB	154	MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
223e47cc LB	155	const SparcInstrInfo &TII =
1a4d82fc	156	static_cast<const SparcInstrInfo >(MF.getSubtarget().getInstrInfo());
223e47cc LB	157	DebugLoc dl = MBBI->getDebugLoc();
	158	assert(MBBI->getOpcode() == SP::RETL &&
	159	"Can only put epilog before 'retl' instruction!");
1a4d82fc JJ	160	if (!FuncInfo->isLeafProc()) {
	161	BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
	162	.addReg(SP::G0);
	163	return;
	164	}
	165	MachineFrameInfo *MFI = MF.getFrameInfo();
	166
	167	int NumBytes = (int) MFI->getStackSize();
	168	if (NumBytes == 0)
	169	return;
	170
	171	NumBytes = MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
	172	NumBytes);
	173	emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
	174	}
	175
	176	bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
	177	// Reserve call frame if there are no variable sized objects on the stack.
	178	return !MF.getFrameInfo()->hasVarSizedObjects();
	179	}
	180
	181	// hasFP - Return true if the specified function should have a dedicated frame
	182	// pointer register. This is true if the function has variable sized allocas or
	183	// if frame pointer elimination is disabled.
	184	bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
	185	const MachineFrameInfo *MFI = MF.getFrameInfo();
	186	return MF.getTarget().Options.DisableFramePointerElim(MF) \|\|
	187	MFI->hasVarSizedObjects() \|\| MFI->isFrameAddressTaken();
	188	}
	189
	190
	191	static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
	192	{
	193
	194	for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
	195	if (MRI->isPhysRegUsed(reg))
	196	return false;
	197
	198	for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
	199	if (MRI->isPhysRegUsed(reg))
	200	return false;
	201
	202	return true;
	203	}
	204
	205	bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
	206	{
	207
	208	MachineRegisterInfo &MRI = MF.getRegInfo();
	209	MachineFrameInfo *MFI = MF.getFrameInfo();
	210
	211	return !(MFI->hasCalls() // has calls
	212	\|\| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
	213	\|\| MRI.isPhysRegUsed(SP::O6) // %SP is used
	214	\|\| hasFP(MF)); // need %FP
	215	}
	216
	217	void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
	218
	219	MachineRegisterInfo &MRI = MF.getRegInfo();
	220
	221	// Remap %i[0-7] to %o[0-7].
	222	for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
	223	if (!MRI.isPhysRegUsed(reg))
224	continue;
225	unsigned mapped_reg = (reg - SP::I0 + SP::O0);
226	assert(!MRI.isPhysRegUsed(mapped_reg));
227
228	// Replace I register with O register.
229	MRI.replaceRegWith(reg, mapped_reg);
230
231	// Mark the reg unused.
232	MRI.setPhysRegUnused(reg);
233	}
234
235	// Rewrite MBB's Live-ins.
236	for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
237	MBB != E; ++MBB) {
238	for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
239	if (!MBB->isLiveIn(reg))
240	continue;
241	MBB->removeLiveIn(reg);
242	MBB->addLiveIn(reg - SP::I0 + SP::O0);
243	}
244	}
245
246	assert(verifyLeafProcRegUse(&MRI));
247	#ifdef XDEBUG
248	MF.verify(0, "After LeafProc Remapping");
249	#endif
250	}
251
252	void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
253	(MachineFunction &MF, RegScavenger *RS) const {
254
255	if (!DisableLeafProc && isLeafProc(MF)) {
256	SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
257	MFI->setLeafProc(true);
258
259	remapRegsForLeafProc(MF);
260	}
261
223e47cc	262	}